1/* 2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 3 * of PCI-SCSI IO processors. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * 7 * This driver is derived from the Linux sym53c8xx driver. 8 * Copyright (C) 1998-2000 Gerard Roudier 9 * 10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 11 * a port of the FreeBSD ncr driver to Linux-1.2.13. 12 * 13 * The original ncr driver has been written for 386bsd and FreeBSD by 14 * Wolfgang Stanglmeier <wolf@cologne.de> 15 * Stefan Esser <se@mi.Uni-Koeln.de> 16 * Copyright (C) 1994 Wolfgang Stanglmeier 17 * 18 * Other major contributions: 19 * 20 * NVRAM detection and reading. 21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 22 * 23 *----------------------------------------------------------------------------- 24 * 25 * This program is free software; you can redistribute it and/or modify 26 * it under the terms of the GNU General Public License as published by 27 * the Free Software Foundation; either version 2 of the License, or 28 * (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, write to the Free Software 37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 38 */ 39 40#include <linux/gfp.h> 41 42#ifndef SYM_HIPD_H 43#define SYM_HIPD_H 44 45/* 46 * Generic driver options. 47 * 48 * They may be defined in platform specific headers, if they 49 * are useful. 50 * 51 * SYM_OPT_HANDLE_DEVICE_QUEUEING 52 * When this option is set, the driver will use a queue per 53 * device and handle QUEUE FULL status requeuing internally. 54 * 55 * SYM_OPT_LIMIT_COMMAND_REORDERING 56 * When this option is set, the driver tries to limit tagged 57 * command reordering to some reasonnable value. 58 * (set for Linux) 59 */ 60 61/* 62 * Active debugging tags and verbosity. 63 * Both DEBUG_FLAGS and sym_verbose can be redefined 64 * by the platform specific code to something else. 65 */ 66#define DEBUG_ALLOC (0x0001) 67#define DEBUG_PHASE (0x0002) 68#define DEBUG_POLL (0x0004) 69#define DEBUG_QUEUE (0x0008) 70#define DEBUG_RESULT (0x0010) 71#define DEBUG_SCATTER (0x0020) 72#define DEBUG_SCRIPT (0x0040) 73#define DEBUG_TINY (0x0080) 74#define DEBUG_TIMING (0x0100) 75#define DEBUG_NEGO (0x0200) 76#define DEBUG_TAGS (0x0400) 77#define DEBUG_POINTER (0x0800) 78 79#ifndef DEBUG_FLAGS 80#define DEBUG_FLAGS (0x0000) 81#endif 82 83#ifndef sym_verbose 84#define sym_verbose (np->verbose) 85#endif 86 87/* 88 * These ones should have been already defined. 89 */ 90#ifndef assert 91#define assert(expression) { \ 92 if (!(expression)) { \ 93 (void)panic( \ 94 "assertion \"%s\" failed: file \"%s\", line %d\n", \ 95 #expression, \ 96 __FILE__, __LINE__); \ 97 } \ 98} 99#endif 100 101/* 102 * Number of tasks per device we want to handle. 103 */ 104#if SYM_CONF_MAX_TAG_ORDER > 8 105#error "more than 256 tags per logical unit not allowed." 106#endif 107#define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER) 108 109/* 110 * Donnot use more tasks that we can handle. 111 */ 112#ifndef SYM_CONF_MAX_TAG 113#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 114#endif 115#if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK 116#undef SYM_CONF_MAX_TAG 117#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK 118#endif 119 120/* 121 * This one means 'NO TAG for this job' 122 */ 123#define NO_TAG (256) 124 125/* 126 * Number of SCSI targets. 127 */ 128#if SYM_CONF_MAX_TARGET > 16 129#error "more than 16 targets not allowed." 130#endif 131 132/* 133 * Number of logical units per target. 134 */ 135#if SYM_CONF_MAX_LUN > 64 136#error "more than 64 logical units per target not allowed." 137#endif 138 139/* 140 * Asynchronous pre-scaler (ns). Shall be 40 for 141 * the SCSI timings to be compliant. 142 */ 143#define SYM_CONF_MIN_ASYNC (40) 144 145 146/* 147 * MEMORY ALLOCATOR. 148 */ 149 150#define SYM_MEM_WARN 1 /* Warn on failed operations */ 151 152#define SYM_MEM_PAGE_ORDER 0 /* 1 PAGE maximum */ 153#define SYM_MEM_CLUSTER_SHIFT (PAGE_SHIFT+SYM_MEM_PAGE_ORDER) 154#define SYM_MEM_FREE_UNUSED /* Free unused pages immediately */ 155/* 156 * Shortest memory chunk is (1<<SYM_MEM_SHIFT), currently 16. 157 * Actual allocations happen as SYM_MEM_CLUSTER_SIZE sized. 158 * (1 PAGE at a time is just fine). 159 */ 160#define SYM_MEM_SHIFT 4 161#define SYM_MEM_CLUSTER_SIZE (1UL << SYM_MEM_CLUSTER_SHIFT) 162#define SYM_MEM_CLUSTER_MASK (SYM_MEM_CLUSTER_SIZE-1) 163 164/* 165 * Number of entries in the START and DONE queues. 166 * 167 * We limit to 1 PAGE in order to succeed allocation of 168 * these queues. Each entry is 8 bytes long (2 DWORDS). 169 */ 170#ifdef SYM_CONF_MAX_START 171#define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2) 172#else 173#define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2) 174#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 175#endif 176 177#if SYM_CONF_MAX_QUEUE > SYM_MEM_CLUSTER_SIZE/8 178#undef SYM_CONF_MAX_QUEUE 179#define SYM_CONF_MAX_QUEUE (SYM_MEM_CLUSTER_SIZE/8) 180#undef SYM_CONF_MAX_START 181#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2) 182#endif 183 184/* 185 * For this one, we want a short name :-) 186 */ 187#define MAX_QUEUE SYM_CONF_MAX_QUEUE 188 189/* 190 * Common definitions for both bus space based and legacy IO methods. 191 */ 192 193#define INB_OFF(np, o) ioread8(np->s.ioaddr + (o)) 194#define INW_OFF(np, o) ioread16(np->s.ioaddr + (o)) 195#define INL_OFF(np, o) ioread32(np->s.ioaddr + (o)) 196 197#define OUTB_OFF(np, o, val) iowrite8((val), np->s.ioaddr + (o)) 198#define OUTW_OFF(np, o, val) iowrite16((val), np->s.ioaddr + (o)) 199#define OUTL_OFF(np, o, val) iowrite32((val), np->s.ioaddr + (o)) 200 201#define INB(np, r) INB_OFF(np, offsetof(struct sym_reg, r)) 202#define INW(np, r) INW_OFF(np, offsetof(struct sym_reg, r)) 203#define INL(np, r) INL_OFF(np, offsetof(struct sym_reg, r)) 204 205#define OUTB(np, r, v) OUTB_OFF(np, offsetof(struct sym_reg, r), (v)) 206#define OUTW(np, r, v) OUTW_OFF(np, offsetof(struct sym_reg, r), (v)) 207#define OUTL(np, r, v) OUTL_OFF(np, offsetof(struct sym_reg, r), (v)) 208 209#define OUTONB(np, r, m) OUTB(np, r, INB(np, r) | (m)) 210#define OUTOFFB(np, r, m) OUTB(np, r, INB(np, r) & ~(m)) 211#define OUTONW(np, r, m) OUTW(np, r, INW(np, r) | (m)) 212#define OUTOFFW(np, r, m) OUTW(np, r, INW(np, r) & ~(m)) 213#define OUTONL(np, r, m) OUTL(np, r, INL(np, r) | (m)) 214#define OUTOFFL(np, r, m) OUTL(np, r, INL(np, r) & ~(m)) 215 216/* 217 * We normally want the chip to have a consistent view 218 * of driver internal data structures when we restart it. 219 * Thus these macros. 220 */ 221#define OUTL_DSP(np, v) \ 222 do { \ 223 MEMORY_WRITE_BARRIER(); \ 224 OUTL(np, nc_dsp, (v)); \ 225 } while (0) 226 227#define OUTONB_STD() \ 228 do { \ 229 MEMORY_WRITE_BARRIER(); \ 230 OUTONB(np, nc_dcntl, (STD|NOCOM)); \ 231 } while (0) 232 233/* 234 * Command control block states. 235 */ 236#define HS_IDLE (0) 237#define HS_BUSY (1) 238#define HS_NEGOTIATE (2) /* sync/wide data transfer*/ 239#define HS_DISCONNECT (3) /* Disconnected by target */ 240#define HS_WAIT (4) /* waiting for resource */ 241 242#define HS_DONEMASK (0x80) 243#define HS_COMPLETE (4|HS_DONEMASK) 244#define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */ 245#define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */ 246#define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */ 247 248/* 249 * Software Interrupt Codes 250 */ 251#define SIR_BAD_SCSI_STATUS (1) 252#define SIR_SEL_ATN_NO_MSG_OUT (2) 253#define SIR_MSG_RECEIVED (3) 254#define SIR_MSG_WEIRD (4) 255#define SIR_NEGO_FAILED (5) 256#define SIR_NEGO_PROTO (6) 257#define SIR_SCRIPT_STOPPED (7) 258#define SIR_REJECT_TO_SEND (8) 259#define SIR_SWIDE_OVERRUN (9) 260#define SIR_SODL_UNDERRUN (10) 261#define SIR_RESEL_NO_MSG_IN (11) 262#define SIR_RESEL_NO_IDENTIFY (12) 263#define SIR_RESEL_BAD_LUN (13) 264#define SIR_TARGET_SELECTED (14) 265#define SIR_RESEL_BAD_I_T_L (15) 266#define SIR_RESEL_BAD_I_T_L_Q (16) 267#define SIR_ABORT_SENT (17) 268#define SIR_RESEL_ABORTED (18) 269#define SIR_MSG_OUT_DONE (19) 270#define SIR_COMPLETE_ERROR (20) 271#define SIR_DATA_OVERRUN (21) 272#define SIR_BAD_PHASE (22) 273#if SYM_CONF_DMA_ADDRESSING_MODE == 2 274#define SIR_DMAP_DIRTY (23) 275#define SIR_MAX (23) 276#else 277#define SIR_MAX (22) 278#endif 279 280/* 281 * Extended error bit codes. 282 * xerr_status field of struct sym_ccb. 283 */ 284#define XE_EXTRA_DATA (1) /* unexpected data phase */ 285#define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */ 286#define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */ 287#define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */ 288#define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */ 289 290/* 291 * Negotiation status. 292 * nego_status field of struct sym_ccb. 293 */ 294#define NS_SYNC (1) 295#define NS_WIDE (2) 296#define NS_PPR (3) 297 298/* 299 * A CCB hashed table is used to retrieve CCB address 300 * from DSA value. 301 */ 302#define CCB_HASH_SHIFT 8 303#define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT) 304#define CCB_HASH_MASK (CCB_HASH_SIZE-1) 305#define CCB_HASH_CODE(dsa) \ 306 (((dsa) >> (_LGRU16_(sizeof(struct sym_ccb)))) & CCB_HASH_MASK) 307 308#if SYM_CONF_DMA_ADDRESSING_MODE == 2 309/* 310 * We may want to use segment registers for 64 bit DMA. 311 * 16 segments registers -> up to 64 GB addressable. 312 */ 313#define SYM_DMAP_SHIFT (4) 314#define SYM_DMAP_SIZE (1u<<SYM_DMAP_SHIFT) 315#define SYM_DMAP_MASK (SYM_DMAP_SIZE-1) 316#endif 317 318/* 319 * Device flags. 320 */ 321#define SYM_DISC_ENABLED (1) 322#define SYM_TAGS_ENABLED (1<<1) 323#define SYM_SCAN_BOOT_DISABLED (1<<2) 324#define SYM_SCAN_LUNS_DISABLED (1<<3) 325 326/* 327 * Host adapter miscellaneous flags. 328 */ 329#define SYM_AVOID_BUS_RESET (1) 330 331/* 332 * Misc. 333 */ 334#define SYM_SNOOP_TIMEOUT (10000000) 335#define BUS_8_BIT 0 336#define BUS_16_BIT 1 337 338/* 339 * Gather negotiable parameters value 340 */ 341struct sym_trans { 342 u8 period; 343 u8 offset; 344 unsigned int width:1; 345 unsigned int iu:1; 346 unsigned int dt:1; 347 unsigned int qas:1; 348 unsigned int check_nego:1; 349}; 350 351/* 352 * Global TCB HEADER. 353 * 354 * Due to lack of indirect addressing on earlier NCR chips, 355 * this substructure is copied from the TCB to a global 356 * address after selection. 357 * For SYMBIOS chips that support LOAD/STORE this copy is 358 * not needed and thus not performed. 359 */ 360struct sym_tcbh { 361 /* 362 * Scripts bus addresses of LUN table accessed from scripts. 363 * LUN #0 is a special case, since multi-lun devices are rare, 364 * and we we want to speed-up the general case and not waste 365 * resources. 366 */ 367 u32 luntbl_sa; /* bus address of this table */ 368 u32 lun0_sa; /* bus address of LCB #0 */ 369 /* 370 * Actual SYNC/WIDE IO registers value for this target. 371 * 'sval', 'wval' and 'uval' are read from SCRIPTS and 372 * so have alignment constraints. 373 */ 374/*0*/ u_char uval; /* -> SCNTL4 register */ 375/*1*/ u_char sval; /* -> SXFER io register */ 376/*2*/ u_char filler1; 377/*3*/ u_char wval; /* -> SCNTL3 io register */ 378}; 379 380/* 381 * Target Control Block 382 */ 383struct sym_tcb { 384 /* 385 * TCB header. 386 * Assumed at offset 0. 387 */ 388/*0*/ struct sym_tcbh head; 389 390 /* 391 * LUN table used by the SCRIPTS processor. 392 * An array of bus addresses is used on reselection. 393 */ 394 u32 *luntbl; /* LCBs bus address table */ 395 396 /* 397 * LUN table used by the C code. 398 */ 399 struct sym_lcb *lun0p; /* LCB of LUN #0 (usual case) */ 400#if SYM_CONF_MAX_LUN > 1 401 struct sym_lcb **lunmp; /* Other LCBs [1..MAX_LUN] */ 402#endif 403 404#ifdef SYM_HAVE_STCB 405 /* 406 * O/S specific data structure. 407 */ 408 struct sym_stcb s; 409#endif 410 411 /* Transfer goal */ 412 struct sym_trans tgoal; 413 414 /* 415 * Keep track of the CCB used for the negotiation in order 416 * to ensure that only 1 negotiation is queued at a time. 417 */ 418 struct sym_ccb * nego_cp; /* CCB used for the nego */ 419 420 /* 421 * Set when we want to reset the device. 422 */ 423 u_char to_reset; 424 425 /* 426 * Other user settable limits and options. 427 * These limits are read from the NVRAM if present. 428 */ 429 unsigned char usrflags; 430 unsigned char usr_period; 431 unsigned char usr_width; 432 unsigned short usrtags; 433 struct scsi_target *starget; 434}; 435 436/* 437 * Global LCB HEADER. 438 * 439 * Due to lack of indirect addressing on earlier NCR chips, 440 * this substructure is copied from the LCB to a global 441 * address after selection. 442 * For SYMBIOS chips that support LOAD/STORE this copy is 443 * not needed and thus not performed. 444 */ 445struct sym_lcbh { 446 /* 447 * SCRIPTS address jumped by SCRIPTS on reselection. 448 * For not probed logical units, this address points to 449 * SCRIPTS that deal with bad LU handling (must be at 450 * offset zero of the LCB for that reason). 451 */ 452/*0*/ u32 resel_sa; 453 454 /* 455 * Task (bus address of a CCB) read from SCRIPTS that points 456 * to the unique ITL nexus allowed to be disconnected. 457 */ 458 u32 itl_task_sa; 459 460 /* 461 * Task table bus address (read from SCRIPTS). 462 */ 463 u32 itlq_tbl_sa; 464}; 465 466/* 467 * Logical Unit Control Block 468 */ 469struct sym_lcb { 470 /* 471 * TCB header. 472 * Assumed at offset 0. 473 */ 474/*0*/ struct sym_lcbh head; 475 476 /* 477 * Task table read from SCRIPTS that contains pointers to 478 * ITLQ nexuses. The bus address read from SCRIPTS is 479 * inside the header. 480 */ 481 u32 *itlq_tbl; /* Kernel virtual address */ 482 483 /* 484 * Busy CCBs management. 485 */ 486 u_short busy_itlq; /* Number of busy tagged CCBs */ 487 u_short busy_itl; /* Number of busy untagged CCBs */ 488 489 /* 490 * Circular tag allocation buffer. 491 */ 492 u_short ia_tag; /* Tag allocation index */ 493 u_short if_tag; /* Tag release index */ 494 u_char *cb_tags; /* Circular tags buffer */ 495 496 /* 497 * O/S specific data structure. 498 */ 499#ifdef SYM_HAVE_SLCB 500 struct sym_slcb s; 501#endif 502 503#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 504 /* 505 * Optionnaly the driver can handle device queueing, 506 * and requeues internally command to redo. 507 */ 508 SYM_QUEHEAD waiting_ccbq; 509 SYM_QUEHEAD started_ccbq; 510 int num_sgood; 511 u_short started_tags; 512 u_short started_no_tag; 513 u_short started_max; 514 u_short started_limit; 515#endif 516 517#ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 518 /* 519 * Optionally the driver can try to prevent SCSI 520 * IOs from being reordered too much. 521 */ 522 u_char tags_si; /* Current index to tags sum */ 523 u_short tags_sum[2]; /* Tags sum counters */ 524 u_short tags_since; /* # of tags since last switch */ 525#endif 526 527 /* 528 * Set when we want to clear all tasks. 529 */ 530 u_char to_clear; 531 532 /* 533 * Capabilities. 534 */ 535 u_char user_flags; 536 u_char curr_flags; 537}; 538 539/* 540 * Action from SCRIPTS on a task. 541 * Is part of the CCB, but is also used separately to plug 542 * error handling action to perform from SCRIPTS. 543 */ 544struct sym_actscr { 545 u32 start; /* Jumped by SCRIPTS after selection */ 546 u32 restart; /* Jumped by SCRIPTS on relection */ 547}; 548 549/* 550 * Phase mismatch context. 551 * 552 * It is part of the CCB and is used as parameters for the 553 * DATA pointer. We need two contexts to handle correctly the 554 * SAVED DATA POINTER. 555 */ 556struct sym_pmc { 557 struct sym_tblmove sg; /* Updated interrupted SG block */ 558 u32 ret; /* SCRIPT return address */ 559}; 560 561/* 562 * LUN control block lookup. 563 * We use a direct pointer for LUN #0, and a table of 564 * pointers which is only allocated for devices that support 565 * LUN(s) > 0. 566 */ 567#if SYM_CONF_MAX_LUN <= 1 568#define sym_lp(tp, lun) (!lun) ? (tp)->lun0p : NULL 569#else 570#define sym_lp(tp, lun) \ 571 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : NULL 572#endif 573 574/* 575 * Status are used by the host and the script processor. 576 * 577 * The last four bytes (status[4]) are copied to the 578 * scratchb register (declared as scr0..scr3) just after the 579 * select/reselect, and copied back just after disconnecting. 580 * Inside the script the XX_REG are used. 581 */ 582 583/* 584 * Last four bytes (script) 585 */ 586#define HX_REG scr0 587#define HX_PRT nc_scr0 588#define HS_REG scr1 589#define HS_PRT nc_scr1 590#define SS_REG scr2 591#define SS_PRT nc_scr2 592#define HF_REG scr3 593#define HF_PRT nc_scr3 594 595/* 596 * Last four bytes (host) 597 */ 598#define host_xflags phys.head.status[0] 599#define host_status phys.head.status[1] 600#define ssss_status phys.head.status[2] 601#define host_flags phys.head.status[3] 602 603/* 604 * Host flags 605 */ 606#define HF_IN_PM0 1u 607#define HF_IN_PM1 (1u<<1) 608#define HF_ACT_PM (1u<<2) 609#define HF_DP_SAVED (1u<<3) 610#define HF_SENSE (1u<<4) 611#define HF_EXT_ERR (1u<<5) 612#define HF_DATA_IN (1u<<6) 613#ifdef SYM_CONF_IARB_SUPPORT 614#define HF_HINT_IARB (1u<<7) 615#endif 616 617/* 618 * More host flags 619 */ 620#if SYM_CONF_DMA_ADDRESSING_MODE == 2 621#define HX_DMAP_DIRTY (1u<<7) 622#endif 623 624/* 625 * Global CCB HEADER. 626 * 627 * Due to lack of indirect addressing on earlier NCR chips, 628 * this substructure is copied from the ccb to a global 629 * address after selection (or reselection) and copied back 630 * before disconnect. 631 * For SYMBIOS chips that support LOAD/STORE this copy is 632 * not needed and thus not performed. 633 */ 634 635struct sym_ccbh { 636 /* 637 * Start and restart SCRIPTS addresses (must be at 0). 638 */ 639/*0*/ struct sym_actscr go; 640 641 /* 642 * SCRIPTS jump address that deal with data pointers. 643 * 'savep' points to the position in the script responsible 644 * for the actual transfer of data. 645 * It's written on reception of a SAVE_DATA_POINTER message. 646 */ 647 u32 savep; /* Jump address to saved data pointer */ 648 u32 lastp; /* SCRIPTS address at end of data */ 649 650 /* 651 * Status fields. 652 */ 653 u8 status[4]; 654}; 655 656/* 657 * GET/SET the value of the data pointer used by SCRIPTS. 658 * 659 * We must distinguish between the LOAD/STORE-based SCRIPTS 660 * that use directly the header in the CCB, and the NCR-GENERIC 661 * SCRIPTS that use the copy of the header in the HCB. 662 */ 663#if SYM_CONF_GENERIC_SUPPORT 664#define sym_set_script_dp(np, cp, dp) \ 665 do { \ 666 if (np->features & FE_LDSTR) \ 667 cp->phys.head.lastp = cpu_to_scr(dp); \ 668 else \ 669 np->ccb_head.lastp = cpu_to_scr(dp); \ 670 } while (0) 671#define sym_get_script_dp(np, cp) \ 672 scr_to_cpu((np->features & FE_LDSTR) ? \ 673 cp->phys.head.lastp : np->ccb_head.lastp) 674#else 675#define sym_set_script_dp(np, cp, dp) \ 676 do { \ 677 cp->phys.head.lastp = cpu_to_scr(dp); \ 678 } while (0) 679 680#define sym_get_script_dp(np, cp) (cp->phys.head.lastp) 681#endif 682 683/* 684 * Data Structure Block 685 * 686 * During execution of a ccb by the script processor, the 687 * DSA (data structure address) register points to this 688 * substructure of the ccb. 689 */ 690struct sym_dsb { 691 /* 692 * CCB header. 693 * Also assumed at offset 0 of the sym_ccb structure. 694 */ 695/*0*/ struct sym_ccbh head; 696 697 /* 698 * Phase mismatch contexts. 699 * We need two to handle correctly the SAVED DATA POINTER. 700 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic 701 * for address calculation from SCRIPTS. 702 */ 703 struct sym_pmc pm0; 704 struct sym_pmc pm1; 705 706 /* 707 * Table data for Script 708 */ 709 struct sym_tblsel select; 710 struct sym_tblmove smsg; 711 struct sym_tblmove smsg_ext; 712 struct sym_tblmove cmd; 713 struct sym_tblmove sense; 714 struct sym_tblmove wresid; 715 struct sym_tblmove data [SYM_CONF_MAX_SG]; 716}; 717 718/* 719 * Our Command Control Block 720 */ 721struct sym_ccb { 722 /* 723 * This is the data structure which is pointed by the DSA 724 * register when it is executed by the script processor. 725 * It must be the first entry. 726 */ 727 struct sym_dsb phys; 728 729 /* 730 * Pointer to CAM ccb and related stuff. 731 */ 732 struct scsi_cmnd *cmd; /* CAM scsiio ccb */ 733 u8 cdb_buf[16]; /* Copy of CDB */ 734#define SYM_SNS_BBUF_LEN 32 735 u8 sns_bbuf[SYM_SNS_BBUF_LEN]; /* Bounce buffer for sense data */ 736 int data_len; /* Total data length */ 737 int segments; /* Number of SG segments */ 738 739 u8 order; /* Tag type (if tagged command) */ 740 unsigned char odd_byte_adjustment; /* odd-sized req on wide bus */ 741 742 u_char nego_status; /* Negotiation status */ 743 u_char xerr_status; /* Extended error flags */ 744 u32 extra_bytes; /* Extraneous bytes transferred */ 745 746 /* 747 * Message areas. 748 * We prepare a message to be sent after selection. 749 * We may use a second one if the command is rescheduled 750 * due to CHECK_CONDITION or COMMAND TERMINATED. 751 * Contents are IDENTIFY and SIMPLE_TAG. 752 * While negotiating sync or wide transfer, 753 * a SDTR or WDTR message is appended. 754 */ 755 u_char scsi_smsg [12]; 756 u_char scsi_smsg2[12]; 757 758 /* 759 * Auto request sense related fields. 760 */ 761 u_char sensecmd[6]; /* Request Sense command */ 762 u_char sv_scsi_status; /* Saved SCSI status */ 763 u_char sv_xerr_status; /* Saved extended status */ 764 int sv_resid; /* Saved residual */ 765 766 /* 767 * Other fields. 768 */ 769 u32 ccb_ba; /* BUS address of this CCB */ 770 u_short tag; /* Tag for this transfer */ 771 /* NO_TAG means no tag */ 772 u_char target; 773 u_char lun; 774 struct sym_ccb *link_ccbh; /* Host adapter CCB hash chain */ 775 SYM_QUEHEAD link_ccbq; /* Link to free/busy CCB queue */ 776 u32 startp; /* Initial data pointer */ 777 u32 goalp; /* Expected last data pointer */ 778 int ext_sg; /* Extreme data pointer, used */ 779 int ext_ofs; /* to calculate the residual. */ 780#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 781 SYM_QUEHEAD link2_ccbq; /* Link for device queueing */ 782 u_char started; /* CCB queued to the squeue */ 783#endif 784 u_char to_abort; /* Want this IO to be aborted */ 785#ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 786 u_char tags_si; /* Lun tags sum index (0,1) */ 787#endif 788}; 789 790#define CCB_BA(cp,lbl) cpu_to_scr(cp->ccb_ba + offsetof(struct sym_ccb, lbl)) 791 792typedef struct device *m_pool_ident_t; 793 794/* 795 * Host Control Block 796 */ 797struct sym_hcb { 798 /* 799 * Global headers. 800 * Due to poorness of addressing capabilities, earlier 801 * chips (810, 815, 825) copy part of the data structures 802 * (CCB, TCB and LCB) in fixed areas. 803 */ 804#if SYM_CONF_GENERIC_SUPPORT 805 struct sym_ccbh ccb_head; 806 struct sym_tcbh tcb_head; 807 struct sym_lcbh lcb_head; 808#endif 809 /* 810 * Idle task and invalid task actions and 811 * their bus addresses. 812 */ 813 struct sym_actscr idletask, notask, bad_itl, bad_itlq; 814 u32 idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba; 815 816 /* 817 * Dummy lun table to protect us against target 818 * returning bad lun number on reselection. 819 */ 820 u32 *badluntbl; /* Table physical address */ 821 u32 badlun_sa; /* SCRIPT handler BUS address */ 822 823 /* 824 * Bus address of this host control block. 825 */ 826 u32 hcb_ba; 827 828 /* 829 * Bit 32-63 of the on-chip RAM bus address in LE format. 830 * The START_RAM64 script loads the MMRS and MMWS from this 831 * field. 832 */ 833 u32 scr_ram_seg; 834 835 /* 836 * Initial value of some IO register bits. 837 * These values are assumed to have been set by BIOS, and may 838 * be used to probe adapter implementation differences. 839 */ 840 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4, 841 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4, 842 sv_stest1; 843 844 /* 845 * Actual initial value of IO register bits used by the 846 * driver. They are loaded at initialisation according to 847 * features that are to be enabled/disabled. 848 */ 849 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4, 850 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4; 851 852 /* 853 * Target data. 854 */ 855 struct sym_tcb target[SYM_CONF_MAX_TARGET]; 856 857 /* 858 * Target control block bus address array used by the SCRIPT 859 * on reselection. 860 */ 861 u32 *targtbl; 862 u32 targtbl_ba; 863 864 /* 865 * DMA pool handle for this HBA. 866 */ 867 m_pool_ident_t bus_dmat; 868 869 /* 870 * O/S specific data structure 871 */ 872 struct sym_shcb s; 873 874 /* 875 * Physical bus addresses of the chip. 876 */ 877 u32 mmio_ba; /* MMIO 32 bit BUS address */ 878 int mmio_ws; /* MMIO Window size */ 879 880 u32 ram_ba; /* RAM 32 bit BUS address */ 881 int ram_ws; /* RAM window size */ 882 883 /* 884 * SCRIPTS virtual and physical bus addresses. 885 * 'script' is loaded in the on-chip RAM if present. 886 * 'scripth' stays in main memory for all chips except the 887 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM. 888 */ 889 u_char *scripta0; /* Copy of scripts A, B, Z */ 890 u_char *scriptb0; 891 u_char *scriptz0; 892 u32 scripta_ba; /* Actual scripts A, B, Z */ 893 u32 scriptb_ba; /* 32 bit bus addresses. */ 894 u32 scriptz_ba; 895 u_short scripta_sz; /* Actual size of script A, B, Z*/ 896 u_short scriptb_sz; 897 u_short scriptz_sz; 898 899 /* 900 * Bus addresses, setup and patch methods for 901 * the selected firmware. 902 */ 903 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */ 904 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */ 905 struct sym_fwz_ba fwz_bas; /* Useful SCRIPTZ bus addresses */ 906 void (*fw_setup)(struct sym_hcb *np, struct sym_fw *fw); 907 void (*fw_patch)(struct sym_hcb *np); 908 char *fw_name; 909 910 /* 911 * General controller parameters and configuration. 912 */ 913 u_short device_id; /* PCI device id */ 914 u_char revision_id; /* PCI device revision id */ 915 u_int features; /* Chip features map */ 916 u_char myaddr; /* SCSI id of the adapter */ 917 u_char maxburst; /* log base 2 of dwords burst */ 918 u_char maxwide; /* Maximum transfer width */ 919 u_char minsync; /* Min sync period factor (ST) */ 920 u_char maxsync; /* Max sync period factor (ST) */ 921 u_char maxoffs; /* Max scsi offset (ST) */ 922 u_char minsync_dt; /* Min sync period factor (DT) */ 923 u_char maxsync_dt; /* Max sync period factor (DT) */ 924 u_char maxoffs_dt; /* Max scsi offset (DT) */ 925 u_char multiplier; /* Clock multiplier (1,2,4) */ 926 u_char clock_divn; /* Number of clock divisors */ 927 u32 clock_khz; /* SCSI clock frequency in KHz */ 928 u32 pciclk_khz; /* Estimated PCI clock in KHz */ 929 /* 930 * Start queue management. 931 * It is filled up by the host processor and accessed by the 932 * SCRIPTS processor in order to start SCSI commands. 933 */ 934 volatile /* Prevent code optimizations */ 935 u32 *squeue; /* Start queue virtual address */ 936 u32 squeue_ba; /* Start queue BUS address */ 937 u_short squeueput; /* Next free slot of the queue */ 938 u_short actccbs; /* Number of allocated CCBs */ 939 940 /* 941 * Command completion queue. 942 * It is the same size as the start queue to avoid overflow. 943 */ 944 u_short dqueueget; /* Next position to scan */ 945 volatile /* Prevent code optimizations */ 946 u32 *dqueue; /* Completion (done) queue */ 947 u32 dqueue_ba; /* Done queue BUS address */ 948 949 /* 950 * Miscellaneous buffers accessed by the scripts-processor. 951 * They shall be DWORD aligned, because they may be read or 952 * written with a script command. 953 */ 954 u_char msgout[8]; /* Buffer for MESSAGE OUT */ 955 u_char msgin [8]; /* Buffer for MESSAGE IN */ 956 u32 lastmsg; /* Last SCSI message sent */ 957 u32 scratch; /* Scratch for SCSI receive */ 958 /* Also used for cache test */ 959 /* 960 * Miscellaneous configuration and status parameters. 961 */ 962 u_char usrflags; /* Miscellaneous user flags */ 963 u_char scsi_mode; /* Current SCSI BUS mode */ 964 u_char verbose; /* Verbosity for this controller*/ 965 966 /* 967 * CCB lists and queue. 968 */ 969 struct sym_ccb **ccbh; /* CCBs hashed by DSA value */ 970 /* CCB_HASH_SIZE lists of CCBs */ 971 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */ 972 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */ 973 974 /* 975 * During error handling and/or recovery, 976 * active CCBs that are to be completed with 977 * error or requeued are moved from the busy_ccbq 978 * to the comp_ccbq prior to completion. 979 */ 980 SYM_QUEHEAD comp_ccbq; 981 982#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 983 SYM_QUEHEAD dummy_ccbq; 984#endif 985 986 /* 987 * IMMEDIATE ARBITRATION (IARB) control. 988 * 989 * We keep track in 'last_cp' of the last CCB that has been 990 * queued to the SCRIPTS processor and clear 'last_cp' when 991 * this CCB completes. If last_cp is not zero at the moment 992 * we queue a new CCB, we set a flag in 'last_cp' that is 993 * used by the SCRIPTS as a hint for setting IARB. 994 * We donnot set more than 'iarb_max' consecutive hints for 995 * IARB in order to leave devices a chance to reselect. 996 * By the way, any non zero value of 'iarb_max' is unfair. :) 997 */ 998#ifdef SYM_CONF_IARB_SUPPORT 999 u_short iarb_max; /* Max. # consecutive IARB hints*/ 1000 u_short iarb_count; /* Actual # of these hints */ 1001 struct sym_ccb * last_cp; 1002#endif 1003 1004 /* 1005 * Command abort handling. 1006 * We need to synchronize tightly with the SCRIPTS 1007 * processor in order to handle things correctly. 1008 */ 1009 u_char abrt_msg[4]; /* Message to send buffer */ 1010 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */ 1011 struct sym_tblsel abrt_sel; /* Sync params for selection */ 1012 u_char istat_sem; /* Tells the chip to stop (SEM) */ 1013 1014 /* 1015 * 64 bit DMA handling. 1016 */ 1017#if SYM_CONF_DMA_ADDRESSING_MODE != 0 1018 u_char use_dac; /* Use PCI DAC cycles */ 1019#if SYM_CONF_DMA_ADDRESSING_MODE == 2 1020 u_char dmap_dirty; /* Dma segments registers dirty */ 1021 u32 dmap_bah[SYM_DMAP_SIZE];/* Segment registers map */ 1022#endif 1023#endif 1024}; 1025 1026#define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) 1027 1028 1029/* 1030 * FIRMWARES (sym_fw.c) 1031 */ 1032struct sym_fw * sym_find_firmware(struct sym_chip *chip); 1033void sym_fw_bind_script(struct sym_hcb *np, u32 *start, int len); 1034 1035/* 1036 * Driver methods called from O/S specific code. 1037 */ 1038char *sym_driver_name(void); 1039void sym_print_xerr(struct scsi_cmnd *cmd, int x_status); 1040int sym_reset_scsi_bus(struct sym_hcb *np, int enab_int); 1041struct sym_chip *sym_lookup_chip_table(u_short device_id, u_char revision); 1042#ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 1043void sym_start_next_ccbs(struct sym_hcb *np, struct sym_lcb *lp, int maxn); 1044#else 1045void sym_put_start_queue(struct sym_hcb *np, struct sym_ccb *cp); 1046#endif 1047void sym_start_up(struct sym_hcb *np, int reason); 1048void sym_interrupt(struct sym_hcb *np); 1049int sym_clear_tasks(struct sym_hcb *np, int cam_status, int target, int lun, int task); 1050struct sym_ccb *sym_get_ccb(struct sym_hcb *np, struct scsi_cmnd *cmd, u_char tag_order); 1051void sym_free_ccb(struct sym_hcb *np, struct sym_ccb *cp); 1052struct sym_lcb *sym_alloc_lcb(struct sym_hcb *np, u_char tn, u_char ln); 1053int sym_queue_scsiio(struct sym_hcb *np, struct scsi_cmnd *csio, struct sym_ccb *cp); 1054int sym_abort_scsiio(struct sym_hcb *np, struct scsi_cmnd *ccb, int timed_out); 1055int sym_reset_scsi_target(struct sym_hcb *np, int target); 1056void sym_hcb_free(struct sym_hcb *np); 1057int sym_hcb_attach(struct Scsi_Host *shost, struct sym_fw *fw, struct sym_nvram *nvram); 1058 1059/* 1060 * Build a scatter/gather entry. 1061 * 1062 * For 64 bit systems, we use the 8 upper bits of the size field 1063 * to provide bus address bits 32-39 to the SCRIPTS processor. 1064 * This allows the 895A, 896, 1010 to address up to 1 TB of memory. 1065 */ 1066 1067#if SYM_CONF_DMA_ADDRESSING_MODE == 0 1068#define sym_build_sge(np, data, badd, len) \ 1069do { \ 1070 (data)->addr = cpu_to_scr(badd); \ 1071 (data)->size = cpu_to_scr(len); \ 1072} while (0) 1073#elif SYM_CONF_DMA_ADDRESSING_MODE == 1 1074#define sym_build_sge(np, data, badd, len) \ 1075do { \ 1076 (data)->addr = cpu_to_scr(badd); \ 1077 (data)->size = cpu_to_scr((((badd) >> 8) & 0xff000000) + len); \ 1078} while (0) 1079#elif SYM_CONF_DMA_ADDRESSING_MODE == 2 1080int sym_lookup_dmap(struct sym_hcb *np, u32 h, int s); 1081static __inline void 1082sym_build_sge(struct sym_hcb *np, struct sym_tblmove *data, u64 badd, int len) 1083{ 1084 u32 h = (badd>>32); 1085 int s = (h&SYM_DMAP_MASK); 1086 1087 if (h != np->dmap_bah[s]) 1088 goto bad; 1089good: 1090 (data)->addr = cpu_to_scr(badd); 1091 (data)->size = cpu_to_scr((s<<24) + len); 1092 return; 1093bad: 1094 s = sym_lookup_dmap(np, h, s); 1095 goto good; 1096} 1097#else 1098#error "Unsupported DMA addressing mode" 1099#endif 1100 1101/* 1102 * MEMORY ALLOCATOR. 1103 */ 1104 1105#define sym_get_mem_cluster() \ 1106 (void *) __get_free_pages(GFP_ATOMIC, SYM_MEM_PAGE_ORDER) 1107#define sym_free_mem_cluster(p) \ 1108 free_pages((unsigned long)p, SYM_MEM_PAGE_ORDER) 1109 1110/* 1111 * Link between free memory chunks of a given size. 1112 */ 1113typedef struct sym_m_link { 1114 struct sym_m_link *next; 1115} *m_link_p; 1116 1117/* 1118 * Virtual to bus physical translation for a given cluster. 1119 * Such a structure is only useful with DMA abstraction. 1120 */ 1121typedef struct sym_m_vtob { /* Virtual to Bus address translation */ 1122 struct sym_m_vtob *next; 1123 void *vaddr; /* Virtual address */ 1124 dma_addr_t baddr; /* Bus physical address */ 1125} *m_vtob_p; 1126 1127/* Hash this stuff a bit to speed up translations */ 1128#define VTOB_HASH_SHIFT 5 1129#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT) 1130#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1) 1131#define VTOB_HASH_CODE(m) \ 1132 ((((unsigned long)(m)) >> SYM_MEM_CLUSTER_SHIFT) & VTOB_HASH_MASK) 1133 1134/* 1135 * Memory pool of a given kind. 1136 * Ideally, we want to use: 1137 * 1) 1 pool for memory we donnot need to involve in DMA. 1138 * 2) The same pool for controllers that require same DMA 1139 * constraints and features. 1140 * The OS specific m_pool_id_t thing and the sym_m_pool_match() 1141 * method are expected to tell the driver about. 1142 */ 1143typedef struct sym_m_pool { 1144 m_pool_ident_t dev_dmat; /* Identifies the pool (see above) */ 1145 void * (*get_mem_cluster)(struct sym_m_pool *); 1146#ifdef SYM_MEM_FREE_UNUSED 1147 void (*free_mem_cluster)(struct sym_m_pool *, void *); 1148#endif 1149#define M_GET_MEM_CLUSTER() mp->get_mem_cluster(mp) 1150#define M_FREE_MEM_CLUSTER(p) mp->free_mem_cluster(mp, p) 1151 int nump; 1152 m_vtob_p vtob[VTOB_HASH_SIZE]; 1153 struct sym_m_pool *next; 1154 struct sym_m_link h[SYM_MEM_CLUSTER_SHIFT - SYM_MEM_SHIFT + 1]; 1155} *m_pool_p; 1156 1157/* 1158 * Alloc, free and translate addresses to bus physical 1159 * for DMAable memory. 1160 */ 1161void *__sym_calloc_dma(m_pool_ident_t dev_dmat, int size, char *name); 1162void __sym_mfree_dma(m_pool_ident_t dev_dmat, void *m, int size, char *name); 1163dma_addr_t __vtobus(m_pool_ident_t dev_dmat, void *m); 1164 1165/* 1166 * Verbs used by the driver code for DMAable memory handling. 1167 * The _uvptv_ macro avoids a nasty warning about pointer to volatile 1168 * being discarded. 1169 */ 1170#define _uvptv_(p) ((void *)((u_long)(p))) 1171 1172#define _sym_calloc_dma(np, l, n) __sym_calloc_dma(np->bus_dmat, l, n) 1173#define _sym_mfree_dma(np, p, l, n) \ 1174 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), l, n) 1175#define sym_calloc_dma(l, n) _sym_calloc_dma(np, l, n) 1176#define sym_mfree_dma(p, l, n) _sym_mfree_dma(np, p, l, n) 1177#define vtobus(p) __vtobus(np->bus_dmat, _uvptv_(p)) 1178 1179/* 1180 * We have to provide the driver memory allocator with methods for 1181 * it to maintain virtual to bus physical address translations. 1182 */ 1183 1184#define sym_m_pool_match(mp_id1, mp_id2) (mp_id1 == mp_id2) 1185 1186static __inline void *sym_m_get_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp) 1187{ 1188 void *vaddr = NULL; 1189 dma_addr_t baddr = 0; 1190 1191 vaddr = dma_alloc_coherent(mp->dev_dmat, SYM_MEM_CLUSTER_SIZE, &baddr, 1192 GFP_ATOMIC); 1193 if (vaddr) { 1194 vbp->vaddr = vaddr; 1195 vbp->baddr = baddr; 1196 } 1197 return vaddr; 1198} 1199 1200static __inline void sym_m_free_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp) 1201{ 1202 dma_free_coherent(mp->dev_dmat, SYM_MEM_CLUSTER_SIZE, vbp->vaddr, 1203 vbp->baddr); 1204} 1205 1206#endif /* SYM_HIPD_H */ 1207