1/****************************************************************************** 2** Device driver for the PCI-SCSI NCR538XX controller family. 3** 4** Copyright (C) 1994 Wolfgang Stanglmeier 5** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr> 6** 7** This program is free software; you can redistribute it and/or modify 8** it under the terms of the GNU General Public License as published by 9** the Free Software Foundation; either version 2 of the License, or 10** (at your option) any later version. 11** 12** This program is distributed in the hope that it will be useful, 13** but WITHOUT ANY WARRANTY; without even the implied warranty of 14** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15** GNU General Public License for more details. 16** 17** You should have received a copy of the GNU General Public License 18** along with this program; if not, write to the Free Software 19** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20** 21**----------------------------------------------------------------------------- 22** 23** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver 24** and is currently maintained by 25** 26** Gerard Roudier <groudier@free.fr> 27** 28** Being given that this driver originates from the FreeBSD version, and 29** in order to keep synergy on both, any suggested enhancements and corrections 30** received on Linux are automatically a potential candidate for the FreeBSD 31** version. 32** 33** The original driver has been written for 386bsd and FreeBSD by 34** Wolfgang Stanglmeier <wolf@cologne.de> 35** Stefan Esser <se@mi.Uni-Koeln.de> 36** 37** And has been ported to NetBSD by 38** Charles M. Hannum <mycroft@gnu.ai.mit.edu> 39** 40** NVRAM detection and reading. 41** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 42** 43** Added support for MIPS big endian systems. 44** Carsten Langgaard, carstenl@mips.com 45** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 46** 47** Added support for HP PARISC big endian systems. 48** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 49** 50******************************************************************************* 51*/ 52 53#ifndef NCR53C8XX_H 54#define NCR53C8XX_H 55 56#include <scsi/scsi_host.h> 57 58 59/* 60** If you want a driver as small as possible, donnot define the 61** following options. 62*/ 63#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT 64#define SCSI_NCR_DEBUG_INFO_SUPPORT 65 66/* 67** To disable integrity checking, do not define the 68** following option. 69*/ 70#ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK 71# define SCSI_NCR_ENABLE_INTEGRITY_CHECK 72#endif 73 74/* --------------------------------------------------------------------- 75** Take into account kernel configured parameters. 76** Most of these options can be overridden at startup by a command line. 77** --------------------------------------------------------------------- 78*/ 79 80/* 81 * For Ultra2 and Ultra3 SCSI support option, use special features. 82 * 83 * Value (default) means: 84 * bit 0 : all features enabled, except: 85 * bit 1 : PCI Write And Invalidate. 86 * bit 2 : Data Phase Mismatch handling from SCRIPTS. 87 * 88 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be 89 * enabled by the driver. 90 */ 91#define SCSI_NCR_SETUP_SPECIAL_FEATURES (3) 92 93#define SCSI_NCR_MAX_SYNC (80) 94 95/* 96 * Allow tags from 2 to 256, default 8 97 */ 98#ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS 99#if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2 100#define SCSI_NCR_MAX_TAGS (2) 101#elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256 102#define SCSI_NCR_MAX_TAGS (256) 103#else 104#define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS 105#endif 106#else 107#define SCSI_NCR_MAX_TAGS (8) 108#endif 109 110/* 111 * Allow tagged command queuing support if configured with default number 112 * of tags set to max (see above). 113 */ 114#ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS 115#define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS 116#elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE 117#define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS 118#else 119#define SCSI_NCR_SETUP_DEFAULT_TAGS (0) 120#endif 121 122/* 123 * Immediate arbitration 124 */ 125#if defined(CONFIG_SCSI_NCR53C8XX_IARB) 126#define SCSI_NCR_IARB_SUPPORT 127#endif 128 129/* 130 * Sync transfer frequency at startup. 131 * Allow from 5Mhz to 80Mhz default 20 Mhz. 132 */ 133#ifndef CONFIG_SCSI_NCR53C8XX_SYNC 134#define CONFIG_SCSI_NCR53C8XX_SYNC (20) 135#elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC 136#undef CONFIG_SCSI_NCR53C8XX_SYNC 137#define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC 138#endif 139 140#if CONFIG_SCSI_NCR53C8XX_SYNC == 0 141#define SCSI_NCR_SETUP_DEFAULT_SYNC (255) 142#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5 143#define SCSI_NCR_SETUP_DEFAULT_SYNC (50) 144#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20 145#define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC)) 146#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33 147#define SCSI_NCR_SETUP_DEFAULT_SYNC (11) 148#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40 149#define SCSI_NCR_SETUP_DEFAULT_SYNC (10) 150#else 151#define SCSI_NCR_SETUP_DEFAULT_SYNC (9) 152#endif 153 154/* 155 * Disallow disconnections at boot-up 156 */ 157#ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT 158#define SCSI_NCR_SETUP_DISCONNECTION (0) 159#else 160#define SCSI_NCR_SETUP_DISCONNECTION (1) 161#endif 162 163/* 164 * Force synchronous negotiation for all targets 165 */ 166#ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO 167#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1) 168#else 169#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0) 170#endif 171 172/* 173 * Disable master parity checking (flawed hardwares need that) 174 */ 175#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK 176#define SCSI_NCR_SETUP_MASTER_PARITY (0) 177#else 178#define SCSI_NCR_SETUP_MASTER_PARITY (1) 179#endif 180 181/* 182 * Disable scsi parity checking (flawed devices may need that) 183 */ 184#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK 185#define SCSI_NCR_SETUP_SCSI_PARITY (0) 186#else 187#define SCSI_NCR_SETUP_SCSI_PARITY (1) 188#endif 189 190/* 191 * Settle time after reset at boot-up 192 */ 193#define SCSI_NCR_SETUP_SETTLE_TIME (2) 194 195#ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT 196#define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1 197#endif 198 199#if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1 200#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM 201#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES 202#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS 203 204/* 205** Same as option 1, but also deal with 206** misconfigured interrupts. 207** 208** - Edge triggered instead of level sensitive. 209** - No interrupt line connected. 210** - IRQ number misconfigured. 211** 212** If no interrupt is delivered, the driver will 213** catch the interrupt conditions 10 times per 214** second. No need to say that this option is 215** not recommended. 216*/ 217#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2 218#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM 219#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES 220#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS 221#define SCSI_NCR_PCIQ_BROKEN_INTR 222 223/* 224** Some bridge designers decided to flush 225** everything prior to deliver the interrupt. 226** This option tries to deal with such a 227** behaviour. 228*/ 229#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3 230#define SCSI_NCR_PCIQ_SYNC_ON_INTR 231#endif 232 233/* 234** Other parameters not configurable with "make config" 235** Avoid to change these constants, unless you know what you are doing. 236*/ 237 238#define SCSI_NCR_ALWAYS_SIMPLE_TAG 239#define SCSI_NCR_MAX_SCATTER (127) 240#define SCSI_NCR_MAX_TARGET (16) 241 242/* 243** Compute some desirable value for CAN_QUEUE 244** and CMD_PER_LUN. 245** The driver will use lower values if these 246** ones appear to be too large. 247*/ 248#define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET) 249#define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS) 250 251#define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER) 252#define SCSI_NCR_TIMER_INTERVAL (HZ) 253 254#define SCSI_NCR_MAX_LUN (16) 255 256/* 257 * IO functions definition for big/little endian CPU support. 258 * For now, the NCR is only supported in little endian addressing mode, 259 */ 260 261#ifdef __BIG_ENDIAN 262 263#define inw_l2b inw 264#define inl_l2b inl 265#define outw_b2l outw 266#define outl_b2l outl 267 268#define readb_raw readb 269#define writeb_raw writeb 270 271#if defined(SCSI_NCR_BIG_ENDIAN) 272#define readw_l2b __raw_readw 273#define readl_l2b __raw_readl 274#define writew_b2l __raw_writew 275#define writel_b2l __raw_writel 276#define readw_raw __raw_readw 277#define readl_raw __raw_readl 278#define writew_raw __raw_writew 279#define writel_raw __raw_writel 280#else /* Other big-endian */ 281#define readw_l2b readw 282#define readl_l2b readl 283#define writew_b2l writew 284#define writel_b2l writel 285#define readw_raw readw 286#define readl_raw readl 287#define writew_raw writew 288#define writel_raw writel 289#endif 290 291#else /* little endian */ 292 293#define inw_raw inw 294#define inl_raw inl 295#define outw_raw outw 296#define outl_raw outl 297 298#define readb_raw readb 299#define readw_raw readw 300#define readl_raw readl 301#define writeb_raw writeb 302#define writew_raw writew 303#define writel_raw writel 304 305#endif 306 307#if !defined(__hppa__) && !defined(__mips__) 308#ifdef SCSI_NCR_BIG_ENDIAN 309#error "The NCR in BIG ENDIAN addressing mode is not (yet) supported" 310#endif 311#endif 312 313#define MEMORY_BARRIER() mb() 314 315 316/* 317 * If the NCR uses big endian addressing mode over the 318 * PCI, actual io register addresses for byte and word 319 * accesses must be changed according to lane routing. 320 * Btw, ncr_offb() and ncr_offw() macros only apply to 321 * constants and so donnot generate bloated code. 322 */ 323 324#if defined(SCSI_NCR_BIG_ENDIAN) 325 326#define ncr_offb(o) (((o)&~3)+((~((o)&3))&3)) 327#define ncr_offw(o) (((o)&~3)+((~((o)&3))&2)) 328 329#else 330 331#define ncr_offb(o) (o) 332#define ncr_offw(o) (o) 333 334#endif 335 336/* 337 * If the CPU and the NCR use same endian-ness addressing, 338 * no byte reordering is needed for script patching. 339 * Macro cpu_to_scr() is to be used for script patching. 340 * Macro scr_to_cpu() is to be used for getting a DWORD 341 * from the script. 342 */ 343 344#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) 345 346#define cpu_to_scr(dw) cpu_to_le32(dw) 347#define scr_to_cpu(dw) le32_to_cpu(dw) 348 349#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) 350 351#define cpu_to_scr(dw) cpu_to_be32(dw) 352#define scr_to_cpu(dw) be32_to_cpu(dw) 353 354#else 355 356#define cpu_to_scr(dw) (dw) 357#define scr_to_cpu(dw) (dw) 358 359#endif 360 361/* 362 * Access to the controller chip. 363 * 364 * If the CPU and the NCR use same endian-ness addressing, 365 * no byte reordering is needed for accessing chip io 366 * registers. Functions suffixed by '_raw' are assumed 367 * to access the chip over the PCI without doing byte 368 * reordering. Functions suffixed by '_l2b' are 369 * assumed to perform little-endian to big-endian byte 370 * reordering, those suffixed by '_b2l' blah, blah, 371 * blah, ... 372 */ 373 374/* 375 * MEMORY mapped IO input / output 376 */ 377 378#define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o)) 379#define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o)) 380 381#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) 382 383#define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o)) 384#define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o)) 385 386#define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o)) 387#define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o)) 388 389#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) 390 391#define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o)) 392#define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o)) 393 394#define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o)) 395#define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o)) 396 397#else 398 399#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS 400/* Only 8 or 32 bit transfers allowed */ 401#define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1)) 402#else 403#define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o)) 404#endif 405#define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o)) 406 407#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS 408/* Only 8 or 32 bit transfers allowed */ 409#define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0) 410#else 411#define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o)) 412#endif 413#define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o)) 414 415#endif 416 417#define INB(r) INB_OFF (offsetof(struct ncr_reg,r)) 418#define INW(r) INW_OFF (offsetof(struct ncr_reg,r)) 419#define INL(r) INL_OFF (offsetof(struct ncr_reg,r)) 420 421#define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val)) 422#define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val)) 423#define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val)) 424 425/* 426 * Set bit field ON, OFF 427 */ 428 429#define OUTONB(r, m) OUTB(r, INB(r) | (m)) 430#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 431#define OUTONW(r, m) OUTW(r, INW(r) | (m)) 432#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 433#define OUTONL(r, m) OUTL(r, INL(r) | (m)) 434#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 435 436/* 437 * We normally want the chip to have a consistent view 438 * of driver internal data structures when we restart it. 439 * Thus these macros. 440 */ 441#define OUTL_DSP(v) \ 442 do { \ 443 MEMORY_BARRIER(); \ 444 OUTL (nc_dsp, (v)); \ 445 } while (0) 446 447#define OUTONB_STD() \ 448 do { \ 449 MEMORY_BARRIER(); \ 450 OUTONB (nc_dcntl, (STD|NOCOM)); \ 451 } while (0) 452 453 454/* 455** NCR53C8XX devices features table. 456*/ 457struct ncr_chip { 458 unsigned short revision_id; 459 unsigned char burst_max; /* log-base-2 of max burst */ 460 unsigned char offset_max; 461 unsigned char nr_divisor; 462 unsigned int features; 463#define FE_LED0 (1<<0) 464#define FE_WIDE (1<<1) /* Wide data transfers */ 465#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */ 466#define FE_DBLR (1<<4) /* Clock doubler present */ 467#define FE_QUAD (1<<5) /* Clock quadrupler present */ 468#define FE_ERL (1<<6) /* Enable read line */ 469#define FE_CLSE (1<<7) /* Cache line size enable */ 470#define FE_WRIE (1<<8) /* Write & Invalidate enable */ 471#define FE_ERMP (1<<9) /* Enable read multiple */ 472#define FE_BOF (1<<10) /* Burst opcode fetch */ 473#define FE_DFS (1<<11) /* DMA fifo size */ 474#define FE_PFEN (1<<12) /* Prefetch enable */ 475#define FE_LDSTR (1<<13) /* Load/Store supported */ 476#define FE_RAM (1<<14) /* On chip RAM present */ 477#define FE_VARCLK (1<<15) /* SCSI clock may vary */ 478#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */ 479#define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */ 480#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */ 481#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */ 482#define FE_LEDC (1<<20) /* Hardware control of LED */ 483#define FE_DIFF (1<<21) /* Support Differential SCSI */ 484#define FE_66MHZ (1<<23) /* 66MHz PCI Support */ 485#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */ 486#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */ 487#define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */ 488#define FE_EHP (1<<27) /* 720: Even host parity */ 489#define FE_MUX (1<<28) /* 720: Multiplexed bus */ 490#define FE_EA (1<<29) /* 720: Enable Ack */ 491 492#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 493#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80) 494#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 495}; 496 497 498/* 499** Driver setup structure. 500** 501** This structure is initialized from linux config options. 502** It can be overridden at boot-up by the boot command line. 503*/ 504#define SCSI_NCR_MAX_EXCLUDES 8 505struct ncr_driver_setup { 506 u8 master_parity; 507 u8 scsi_parity; 508 u8 disconnection; 509 u8 special_features; 510 u8 force_sync_nego; 511 u8 reverse_probe; 512 u8 pci_fix_up; 513 u8 use_nvram; 514 u8 verbose; 515 u8 default_tags; 516 u16 default_sync; 517 u16 debug; 518 u8 burst_max; 519 u8 led_pin; 520 u8 max_wide; 521 u8 settle_delay; 522 u8 diff_support; 523 u8 irqm; 524 u8 bus_check; 525 u8 optimize; 526 u8 recovery; 527 u8 host_id; 528 u16 iarb; 529 u32 excludes[SCSI_NCR_MAX_EXCLUDES]; 530 char tag_ctrl[100]; 531}; 532 533/* 534** Initial setup. 535** Can be overridden at startup by a command line. 536*/ 537#define SCSI_NCR_DRIVER_SETUP \ 538{ \ 539 SCSI_NCR_SETUP_MASTER_PARITY, \ 540 SCSI_NCR_SETUP_SCSI_PARITY, \ 541 SCSI_NCR_SETUP_DISCONNECTION, \ 542 SCSI_NCR_SETUP_SPECIAL_FEATURES, \ 543 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \ 544 0, \ 545 0, \ 546 1, \ 547 0, \ 548 SCSI_NCR_SETUP_DEFAULT_TAGS, \ 549 SCSI_NCR_SETUP_DEFAULT_SYNC, \ 550 0x00, \ 551 7, \ 552 0, \ 553 1, \ 554 SCSI_NCR_SETUP_SETTLE_TIME, \ 555 0, \ 556 0, \ 557 1, \ 558 0, \ 559 0, \ 560 255, \ 561 0x00 \ 562} 563 564/* 565** Boot fail safe setup. 566** Override initial setup from boot command line: 567** ncr53c8xx=safe:y 568*/ 569#define SCSI_NCR_DRIVER_SAFE_SETUP \ 570{ \ 571 0, \ 572 1, \ 573 0, \ 574 0, \ 575 0, \ 576 0, \ 577 0, \ 578 1, \ 579 2, \ 580 0, \ 581 255, \ 582 0x00, \ 583 255, \ 584 0, \ 585 0, \ 586 10, \ 587 1, \ 588 1, \ 589 1, \ 590 0, \ 591 0, \ 592 255 \ 593} 594 595/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/ 596 597/*----------------------------------------------------------------- 598** 599** The ncr 53c810 register structure. 600** 601**----------------------------------------------------------------- 602*/ 603 604struct ncr_reg { 605/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */ 606 607/*01*/ u8 nc_scntl1; /* no reset */ 608 #define ISCON 0x10 /* connected to scsi */ 609 #define CRST 0x08 /* force reset */ 610 #define IARB 0x02 /* immediate arbitration */ 611 612/*02*/ u8 nc_scntl2; /* no disconnect expected */ 613 #define SDU 0x80 /* cmd: disconnect will raise error */ 614 #define CHM 0x40 /* sta: chained mode */ 615 #define WSS 0x08 /* sta: wide scsi send [W]*/ 616 #define WSR 0x01 /* sta: wide scsi received [W]*/ 617 618/*03*/ u8 nc_scntl3; /* cnf system clock dependent */ 619 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 620 #define ULTRA 0x80 /* cmd: ULTRA enable */ 621 /* bits 0-2, 7 rsvd for C1010 */ 622 623/*04*/ u8 nc_scid; /* cnf host adapter scsi address */ 624 #define RRE 0x40 /* r/w:e enable response to resel. */ 625 #define SRE 0x20 /* r/w:e enable response to select */ 626 627/*05*/ u8 nc_sxfer; /* ### Sync speed and count */ 628 /* bits 6-7 rsvd for C1010 */ 629 630/*06*/ u8 nc_sdid; /* ### Destination-ID */ 631 632/*07*/ u8 nc_gpreg; /* ??? IO-Pins */ 633 634/*08*/ u8 nc_sfbr; /* ### First byte in phase */ 635 636/*09*/ u8 nc_socl; 637 #define CREQ 0x80 /* r/w: SCSI-REQ */ 638 #define CACK 0x40 /* r/w: SCSI-ACK */ 639 #define CBSY 0x20 /* r/w: SCSI-BSY */ 640 #define CSEL 0x10 /* r/w: SCSI-SEL */ 641 #define CATN 0x08 /* r/w: SCSI-ATN */ 642 #define CMSG 0x04 /* r/w: SCSI-MSG */ 643 #define CC_D 0x02 /* r/w: SCSI-C_D */ 644 #define CI_O 0x01 /* r/w: SCSI-I_O */ 645 646/*0a*/ u8 nc_ssid; 647 648/*0b*/ u8 nc_sbcl; 649 650/*0c*/ u8 nc_dstat; 651 #define DFE 0x80 /* sta: dma fifo empty */ 652 #define MDPE 0x40 /* int: master data parity error */ 653 #define BF 0x20 /* int: script: bus fault */ 654 #define ABRT 0x10 /* int: script: command aborted */ 655 #define SSI 0x08 /* int: script: single step */ 656 #define SIR 0x04 /* int: script: interrupt instruct. */ 657 #define IID 0x01 /* int: script: illegal instruct. */ 658 659/*0d*/ u8 nc_sstat0; 660 #define ILF 0x80 /* sta: data in SIDL register lsb */ 661 #define ORF 0x40 /* sta: data in SODR register lsb */ 662 #define OLF 0x20 /* sta: data in SODL register lsb */ 663 #define AIP 0x10 /* sta: arbitration in progress */ 664 #define LOA 0x08 /* sta: arbitration lost */ 665 #define WOA 0x04 /* sta: arbitration won */ 666 #define IRST 0x02 /* sta: scsi reset signal */ 667 #define SDP 0x01 /* sta: scsi parity signal */ 668 669/*0e*/ u8 nc_sstat1; 670 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 671 672/*0f*/ u8 nc_sstat2; 673 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 674 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 675 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 676 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 677 #define LDSC 0x02 /* sta: disconnect & reconnect */ 678 679/*10*/ u8 nc_dsa; /* --> Base page */ 680/*11*/ u8 nc_dsa1; 681/*12*/ u8 nc_dsa2; 682/*13*/ u8 nc_dsa3; 683 684/*14*/ u8 nc_istat; /* --> Main Command and status */ 685 #define CABRT 0x80 /* cmd: abort current operation */ 686 #define SRST 0x40 /* mod: reset chip */ 687 #define SIGP 0x20 /* r/w: message from host to ncr */ 688 #define SEM 0x10 /* r/w: message between host + ncr */ 689 #define CON 0x08 /* sta: connected to scsi */ 690 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 691 #define SIP 0x02 /* sta: scsi-interrupt */ 692 #define DIP 0x01 /* sta: host/script interrupt */ 693 694/*15*/ u8 nc_istat1; /* 896 and later cores only */ 695 #define FLSH 0x04 /* sta: chip is flushing */ 696 #define SRUN 0x02 /* sta: scripts are running */ 697 #define SIRQD 0x01 /* r/w: disable INT pin */ 698 699/*16*/ u8 nc_mbox0; /* 896 and later cores only */ 700/*17*/ u8 nc_mbox1; /* 896 and later cores only */ 701 702/*18*/ u8 nc_ctest0; 703 #define EHP 0x04 /* 720 even host parity */ 704/*19*/ u8 nc_ctest1; 705 706/*1a*/ u8 nc_ctest2; 707 #define CSIGP 0x40 708 /* bits 0-2,7 rsvd for C1010 */ 709 710/*1b*/ u8 nc_ctest3; 711 #define FLF 0x08 /* cmd: flush dma fifo */ 712 #define CLF 0x04 /* cmd: clear dma fifo */ 713 #define FM 0x02 /* mod: fetch pin mode */ 714 #define WRIE 0x01 /* mod: write and invalidate enable */ 715 /* bits 4-7 rsvd for C1010 */ 716 717/*1c*/ u32 nc_temp; /* ### Temporary stack */ 718 719/*20*/ u8 nc_dfifo; 720/*21*/ u8 nc_ctest4; 721 #define MUX 0x80 /* 720 host bus multiplex mode */ 722 #define BDIS 0x80 /* mod: burst disable */ 723 #define MPEE 0x08 /* mod: master parity error enable */ 724 725/*22*/ u8 nc_ctest5; 726 #define DFS 0x20 /* mod: dma fifo size */ 727 /* bits 0-1, 3-7 rsvd for C1010 */ 728/*23*/ u8 nc_ctest6; 729 730/*24*/ u32 nc_dbc; /* ### Byte count and command */ 731/*28*/ u32 nc_dnad; /* ### Next command register */ 732/*2c*/ u32 nc_dsp; /* --> Script Pointer */ 733/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */ 734 735/*34*/ u8 nc_scratcha; /* Temporary register a */ 736/*35*/ u8 nc_scratcha1; 737/*36*/ u8 nc_scratcha2; 738/*37*/ u8 nc_scratcha3; 739 740/*38*/ u8 nc_dmode; 741 #define BL_2 0x80 /* mod: burst length shift value +2 */ 742 #define BL_1 0x40 /* mod: burst length shift value +1 */ 743 #define ERL 0x08 /* mod: enable read line */ 744 #define ERMP 0x04 /* mod: enable read multiple */ 745 #define BOF 0x02 /* mod: burst op code fetch */ 746 747/*39*/ u8 nc_dien; 748/*3a*/ u8 nc_sbr; 749 750/*3b*/ u8 nc_dcntl; /* --> Script execution control */ 751 #define CLSE 0x80 /* mod: cache line size enable */ 752 #define PFF 0x40 /* cmd: pre-fetch flush */ 753 #define PFEN 0x20 /* mod: pre-fetch enable */ 754 #define EA 0x20 /* mod: 720 enable-ack */ 755 #define SSM 0x10 /* mod: single step mode */ 756 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 757 #define STD 0x04 /* cmd: start dma mode */ 758 #define IRQD 0x02 /* mod: irq disable */ 759 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 760 /* bits 0-1 rsvd for C1010 */ 761 762/*3c*/ u32 nc_adder; 763 764/*40*/ u16 nc_sien; /* -->: interrupt enable */ 765/*42*/ u16 nc_sist; /* <--: interrupt status */ 766 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 767 #define STO 0x0400/* sta: timeout (select) */ 768 #define GEN 0x0200/* sta: timeout (general) */ 769 #define HTH 0x0100/* sta: timeout (handshake) */ 770 #define MA 0x80 /* sta: phase mismatch */ 771 #define CMP 0x40 /* sta: arbitration complete */ 772 #define SEL 0x20 /* sta: selected by another device */ 773 #define RSL 0x10 /* sta: reselected by another device*/ 774 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 775 #define UDC 0x04 /* sta: unexpected disconnect */ 776 #define RST 0x02 /* sta: scsi bus reset detected */ 777 #define PAR 0x01 /* sta: scsi parity error */ 778 779/*44*/ u8 nc_slpar; 780/*45*/ u8 nc_swide; 781/*46*/ u8 nc_macntl; 782/*47*/ u8 nc_gpcntl; 783/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/ 784/*49*/ u8 nc_stime1; /* cmd: timeout user defined */ 785/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */ 786 787/*4c*/ u8 nc_stest0; 788 789/*4d*/ u8 nc_stest1; 790 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 791 #define DBLEN 0x08 /* clock doubler running */ 792 #define DBLSEL 0x04 /* clock doubler selected */ 793 794 795/*4e*/ u8 nc_stest2; 796 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 797 #define DIF 0x20 /* 720 SCSI differential mode */ 798 #define EXT 0x02 /* extended filtering */ 799 800/*4f*/ u8 nc_stest3; 801 #define TE 0x80 /* c: tolerAnt enable */ 802 #define HSC 0x20 /* c: Halt SCSI Clock */ 803 #define CSF 0x02 /* c: clear scsi fifo */ 804 805/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */ 806/*52*/ u8 nc_stest4; 807 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 808 #define SMODE_HVD 0x40 /* High Voltage Differential */ 809 #define SMODE_SE 0x80 /* Single Ended */ 810 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 811 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 812 /* bits 0-5 rsvd for C1010 */ 813 814/*53*/ u8 nc_53_; 815/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */ 816/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */ 817 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */ 818 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */ 819 #define ENNDJ 0x20 /* Enable Non Data PM Jump */ 820 #define DISFC 0x10 /* Disable Auto FIFO Clear */ 821 #define DILS 0x02 /* Disable Internal Load/Store */ 822 #define DPR 0x01 /* Disable Pipe Req */ 823 824/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */ 825 #define ZMOD 0x80 /* High Impedance Mode */ 826 #define DIC 0x10 /* Disable Internal Cycles */ 827 #define DDAC 0x08 /* Disable Dual Address Cycle */ 828 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */ 829 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */ 830 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */ 831 832/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */ 833/*5a*/ u16 nc_5a_; 834 835/*5c*/ u8 nc_scr0; /* Working register B */ 836/*5d*/ u8 nc_scr1; /* */ 837/*5e*/ u8 nc_scr2; /* */ 838/*5f*/ u8 nc_scr3; /* */ 839 840/*60*/ u8 nc_scrx[64]; /* Working register C-R */ 841/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */ 842/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */ 843/*a8*/ u32 nc_sfs; /* Script Fetch Selector */ 844/*ac*/ u32 nc_drs; /* DSA Relative Selector */ 845/*b0*/ u32 nc_sbms; /* Static Block Move Selector */ 846/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */ 847/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */ 848/*bc*/ u16 nc_scntl4; /* C1010 only */ 849 #define U3EN 0x80 /* Enable Ultra 3 */ 850 #define AIPEN 0x40 /* Allow check upper byte lanes */ 851 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT 852 transfer edge */ 853 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST 854 transfer edge */ 855 856/*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */ 857/*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */ 858 859/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */ 860/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */ 861/*c8*/ u8 nc_rbc; /* Remaining Byte Count */ 862/*c9*/ u8 nc_rbc1; /* */ 863/*ca*/ u8 nc_rbc2; /* */ 864/*cb*/ u8 nc_rbc3; /* */ 865 866/*cc*/ u8 nc_ua; /* Updated Address */ 867/*cd*/ u8 nc_ua1; /* */ 868/*ce*/ u8 nc_ua2; /* */ 869/*cf*/ u8 nc_ua3; /* */ 870/*d0*/ u32 nc_esa; /* Entry Storage Address */ 871/*d4*/ u8 nc_ia; /* Instruction Address */ 872/*d5*/ u8 nc_ia1; 873/*d6*/ u8 nc_ia2; 874/*d7*/ u8 nc_ia3; 875/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */ 876/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */ 877 878 /* Following for C1010 only */ 879/*e0*/ u16 nc_crcpad; /* CRC Value */ 880/*e2*/ u8 nc_crccntl0; /* CRC control register */ 881 #define SNDCRC 0x10 /* Send CRC Request */ 882/*e3*/ u8 nc_crccntl1; /* CRC control register */ 883/*e4*/ u32 nc_crcdata; /* CRC data register */ 884/*e8*/ u32 nc_e8_; /* rsvd */ 885/*ec*/ u32 nc_ec_; /* rsvd */ 886/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */ 887 888}; 889 890/*----------------------------------------------------------- 891** 892** Utility macros for the script. 893** 894**----------------------------------------------------------- 895*/ 896 897#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r)) 898#define REG(r) REGJ (nc_, r) 899 900typedef u32 ncrcmd; 901 902/*----------------------------------------------------------- 903** 904** SCSI phases 905** 906** DT phases illegal for ncr driver. 907** 908**----------------------------------------------------------- 909*/ 910 911#define SCR_DATA_OUT 0x00000000 912#define SCR_DATA_IN 0x01000000 913#define SCR_COMMAND 0x02000000 914#define SCR_STATUS 0x03000000 915#define SCR_DT_DATA_OUT 0x04000000 916#define SCR_DT_DATA_IN 0x05000000 917#define SCR_MSG_OUT 0x06000000 918#define SCR_MSG_IN 0x07000000 919 920#define SCR_ILG_OUT 0x04000000 921#define SCR_ILG_IN 0x05000000 922 923/*----------------------------------------------------------- 924** 925** Data transfer via SCSI. 926** 927**----------------------------------------------------------- 928** 929** MOVE_ABS (LEN) 930** <<start address>> 931** 932** MOVE_IND (LEN) 933** <<dnad_offset>> 934** 935** MOVE_TBL 936** <<dnad_offset>> 937** 938**----------------------------------------------------------- 939*/ 940 941#define OPC_MOVE 0x08000000 942 943#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 944#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 945#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 946 947#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 948#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 949#define SCR_CHMOV_TBL (0x10000000) 950 951struct scr_tblmove { 952 u32 size; 953 u32 addr; 954}; 955 956/*----------------------------------------------------------- 957** 958** Selection 959** 960**----------------------------------------------------------- 961** 962** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 963** <<alternate_address>> 964** 965** SEL_TBL | << dnad_offset>> [ | REL_JMP] 966** <<alternate_address>> 967** 968**----------------------------------------------------------- 969*/ 970 971#define SCR_SEL_ABS 0x40000000 972#define SCR_SEL_ABS_ATN 0x41000000 973#define SCR_SEL_TBL 0x42000000 974#define SCR_SEL_TBL_ATN 0x43000000 975 976 977#ifdef SCSI_NCR_BIG_ENDIAN 978struct scr_tblsel { 979 u8 sel_scntl3; 980 u8 sel_id; 981 u8 sel_sxfer; 982 u8 sel_scntl4; 983}; 984#else 985struct scr_tblsel { 986 u8 sel_scntl4; 987 u8 sel_sxfer; 988 u8 sel_id; 989 u8 sel_scntl3; 990}; 991#endif 992 993#define SCR_JMP_REL 0x04000000 994#define SCR_ID(id) (((u32)(id)) << 16) 995 996/*----------------------------------------------------------- 997** 998** Waiting for Disconnect or Reselect 999** 1000**----------------------------------------------------------- 1001** 1002** WAIT_DISC 1003** dummy: <<alternate_address>> 1004** 1005** WAIT_RESEL 1006** <<alternate_address>> 1007** 1008**----------------------------------------------------------- 1009*/ 1010 1011#define SCR_WAIT_DISC 0x48000000 1012#define SCR_WAIT_RESEL 0x50000000 1013 1014/*----------------------------------------------------------- 1015** 1016** Bit Set / Reset 1017** 1018**----------------------------------------------------------- 1019** 1020** SET (flags {|.. }) 1021** 1022** CLR (flags {|.. }) 1023** 1024**----------------------------------------------------------- 1025*/ 1026 1027#define SCR_SET(f) (0x58000000 | (f)) 1028#define SCR_CLR(f) (0x60000000 | (f)) 1029 1030#define SCR_CARRY 0x00000400 1031#define SCR_TRG 0x00000200 1032#define SCR_ACK 0x00000040 1033#define SCR_ATN 0x00000008 1034 1035 1036 1037 1038/*----------------------------------------------------------- 1039** 1040** Memory to memory move 1041** 1042**----------------------------------------------------------- 1043** 1044** COPY (bytecount) 1045** << source_address >> 1046** << destination_address >> 1047** 1048** SCR_COPY sets the NO FLUSH option by default. 1049** SCR_COPY_F does not set this option. 1050** 1051** For chips which do not support this option, 1052** ncr_copy_and_bind() will remove this bit. 1053**----------------------------------------------------------- 1054*/ 1055 1056#define SCR_NO_FLUSH 0x01000000 1057 1058#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 1059#define SCR_COPY_F(n) (0xc0000000 | (n)) 1060 1061/*----------------------------------------------------------- 1062** 1063** Register move and binary operations 1064** 1065**----------------------------------------------------------- 1066** 1067** SFBR_REG (reg, op, data) reg = SFBR op data 1068** << 0 >> 1069** 1070** REG_SFBR (reg, op, data) SFBR = reg op data 1071** << 0 >> 1072** 1073** REG_REG (reg, op, data) reg = reg op data 1074** << 0 >> 1075** 1076**----------------------------------------------------------- 1077** On 810A, 860, 825A, 875, 895 and 896 chips the content 1078** of SFBR register can be used as data (SCR_SFBR_DATA). 1079** The 896 has additional IO registers starting at 1080** offset 0x80. Bit 7 of register offset is stored in 1081** bit 7 of the SCRIPTS instruction first DWORD. 1082**----------------------------------------------------------- 1083*/ 1084 1085#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80)) 1086 1087#define SCR_SFBR_REG(reg,op,data) \ 1088 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 1089 1090#define SCR_REG_SFBR(reg,op,data) \ 1091 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 1092 1093#define SCR_REG_REG(reg,op,data) \ 1094 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 1095 1096 1097#define SCR_LOAD 0x00000000 1098#define SCR_SHL 0x01000000 1099#define SCR_OR 0x02000000 1100#define SCR_XOR 0x03000000 1101#define SCR_AND 0x04000000 1102#define SCR_SHR 0x05000000 1103#define SCR_ADD 0x06000000 1104#define SCR_ADDC 0x07000000 1105 1106#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 1107 1108/*----------------------------------------------------------- 1109** 1110** FROM_REG (reg) SFBR = reg 1111** << 0 >> 1112** 1113** TO_REG (reg) reg = SFBR 1114** << 0 >> 1115** 1116** LOAD_REG (reg, data) reg = <data> 1117** << 0 >> 1118** 1119** LOAD_SFBR(data) SFBR = <data> 1120** << 0 >> 1121** 1122**----------------------------------------------------------- 1123*/ 1124 1125#define SCR_FROM_REG(reg) \ 1126 SCR_REG_SFBR(reg,SCR_OR,0) 1127 1128#define SCR_TO_REG(reg) \ 1129 SCR_SFBR_REG(reg,SCR_OR,0) 1130 1131#define SCR_LOAD_REG(reg,data) \ 1132 SCR_REG_REG(reg,SCR_LOAD,data) 1133 1134#define SCR_LOAD_SFBR(data) \ 1135 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 1136 1137/*----------------------------------------------------------- 1138** 1139** LOAD from memory to register. 1140** STORE from register to memory. 1141** 1142** Only supported by 810A, 860, 825A, 875, 895 and 896. 1143** 1144**----------------------------------------------------------- 1145** 1146** LOAD_ABS (LEN) 1147** <<start address>> 1148** 1149** LOAD_REL (LEN) (DSA relative) 1150** <<dsa_offset>> 1151** 1152**----------------------------------------------------------- 1153*/ 1154 1155#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 1156#define SCR_NO_FLUSH2 0x02000000 1157#define SCR_DSA_REL2 0x10000000 1158 1159#define SCR_LOAD_R(reg, how, n) \ 1160 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 1161 1162#define SCR_STORE_R(reg, how, n) \ 1163 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 1164 1165#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 1166#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 1167#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 1168#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 1169 1170#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 1171#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 1172#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 1173#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 1174 1175 1176/*----------------------------------------------------------- 1177** 1178** Waiting for Disconnect or Reselect 1179** 1180**----------------------------------------------------------- 1181** 1182** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 1183** <<address>> 1184** 1185** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 1186** <<distance>> 1187** 1188** CALL [ | IFTRUE/IFFALSE ( ... ) ] 1189** <<address>> 1190** 1191** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 1192** <<distance>> 1193** 1194** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 1195** <<dummy>> 1196** 1197** INT [ | IFTRUE/IFFALSE ( ... ) ] 1198** <<ident>> 1199** 1200** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 1201** <<ident>> 1202** 1203** Conditions: 1204** WHEN (phase) 1205** IF (phase) 1206** CARRYSET 1207** DATA (data, mask) 1208** 1209**----------------------------------------------------------- 1210*/ 1211 1212#define SCR_NO_OP 0x80000000 1213#define SCR_JUMP 0x80080000 1214#define SCR_JUMP64 0x80480000 1215#define SCR_JUMPR 0x80880000 1216#define SCR_CALL 0x88080000 1217#define SCR_CALLR 0x88880000 1218#define SCR_RETURN 0x90080000 1219#define SCR_INT 0x98080000 1220#define SCR_INT_FLY 0x98180000 1221 1222#define IFFALSE(arg) (0x00080000 | (arg)) 1223#define IFTRUE(arg) (0x00000000 | (arg)) 1224 1225#define WHEN(phase) (0x00030000 | (phase)) 1226#define IF(phase) (0x00020000 | (phase)) 1227 1228#define DATA(D) (0x00040000 | ((D) & 0xff)) 1229#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 1230 1231#define CARRYSET (0x00200000) 1232 1233/*----------------------------------------------------------- 1234** 1235** SCSI constants. 1236** 1237**----------------------------------------------------------- 1238*/ 1239 1240/* 1241** Status 1242*/ 1243 1244#define S_GOOD (0x00) 1245#define S_CHECK_COND (0x02) 1246#define S_COND_MET (0x04) 1247#define S_BUSY (0x08) 1248#define S_INT (0x10) 1249#define S_INT_COND_MET (0x14) 1250#define S_CONFLICT (0x18) 1251#define S_TERMINATED (0x20) 1252#define S_QUEUE_FULL (0x28) 1253#define S_ILLEGAL (0xff) 1254#define S_SENSE (0x80) 1255 1256/* 1257 * End of ncrreg from FreeBSD 1258 */ 1259 1260/* 1261 Build a scatter/gather entry. 1262 see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge() 1263 implementation ;) 1264 */ 1265 1266#define ncr_build_sge(np, data, badd, len) \ 1267do { \ 1268 (data)->addr = cpu_to_scr(badd); \ 1269 (data)->size = cpu_to_scr(len); \ 1270} while (0) 1271 1272/*========================================================== 1273** 1274** Structures used by the detection routine to transmit 1275** device configuration to the attach function. 1276** 1277**========================================================== 1278*/ 1279struct ncr_slot { 1280 u_long base; 1281 u_long base_2; 1282 u_long base_c; 1283 u_long base_2_c; 1284 void __iomem *base_v; 1285 void __iomem *base_2_v; 1286 int irq; 1287/* port and reg fields to use INB, OUTB macros */ 1288 volatile struct ncr_reg __iomem *reg; 1289}; 1290 1291/*========================================================== 1292** 1293** Structure used by detection routine to save data on 1294** each detected board for attach. 1295** 1296**========================================================== 1297*/ 1298struct ncr_device { 1299 struct device *dev; 1300 struct ncr_slot slot; 1301 struct ncr_chip chip; 1302 u_char host_id; 1303 u8 differential; 1304}; 1305 1306extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device); 1307extern int ncr53c8xx_release(struct Scsi_Host *host); 1308irqreturn_t ncr53c8xx_intr(int irq, void *dev_id); 1309extern int ncr53c8xx_init(void); 1310extern void ncr53c8xx_exit(void); 1311 1312#endif /* NCR53C8XX_H */ 1313