1/************************************************************************** 2 * Initio 9100 device driver for Linux. 3 * 4 * Copyright (c) 1994-1998 Initio Corporation 5 * All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; see the file COPYING. If not, write to 19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 * -------------------------------------------------------------------------- 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions, and the following disclaimer, 28 * without modification, immediately at the beginning of the file. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. The name of the author may not be used to endorse or promote products 33 * derived from this software without specific prior written permission. 34 * 35 * Where this Software is combined with software released under the terms of 36 * the GNU General Public License ("GPL") and the terms of the GPL would require the 37 * combined work to also be released under the terms of the GPL, the terms 38 * and conditions of this License will apply in addition to those of the 39 * GPL with the exception of any terms or conditions of this License that 40 * conflict with, or are expressly prohibited by, the GPL. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 46 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 * 54 **************************************************************************/ 55 56 57#include <linux/types.h> 58 59#define ULONG unsigned long 60#define USHORT unsigned short 61#define UCHAR unsigned char 62#define BYTE unsigned char 63#define WORD unsigned short 64#define DWORD unsigned long 65#define UBYTE unsigned char 66#define UWORD unsigned short 67#define UDWORD unsigned long 68#define U32 u32 69 70#define TOTAL_SG_ENTRY 32 71#define MAX_SUPPORTED_ADAPTERS 8 72#define MAX_OFFSET 15 73#define MAX_TARGETS 16 74 75typedef struct { 76 unsigned short base; 77 unsigned short vec; 78} i91u_config; 79 80/***************************************/ 81/* Tulip Configuration Register Set */ 82/***************************************/ 83#define TUL_PVID 0x00 /* Vendor ID */ 84#define TUL_PDID 0x02 /* Device ID */ 85#define TUL_PCMD 0x04 /* Command */ 86#define TUL_PSTUS 0x06 /* Status */ 87#define TUL_PRID 0x08 /* Revision number */ 88#define TUL_PPI 0x09 /* Programming interface */ 89#define TUL_PSC 0x0A /* Sub Class */ 90#define TUL_PBC 0x0B /* Base Class */ 91#define TUL_PCLS 0x0C /* Cache line size */ 92#define TUL_PLTR 0x0D /* Latency timer */ 93#define TUL_PHDT 0x0E /* Header type */ 94#define TUL_PBIST 0x0F /* BIST */ 95#define TUL_PBAD 0x10 /* Base address */ 96#define TUL_PBAD1 0x14 /* Base address */ 97#define TUL_PBAD2 0x18 /* Base address */ 98#define TUL_PBAD3 0x1C /* Base address */ 99#define TUL_PBAD4 0x20 /* Base address */ 100#define TUL_PBAD5 0x24 /* Base address */ 101#define TUL_PRSVD 0x28 /* Reserved */ 102#define TUL_PRSVD1 0x2C /* Reserved */ 103#define TUL_PRAD 0x30 /* Expansion ROM base address */ 104#define TUL_PRSVD2 0x34 /* Reserved */ 105#define TUL_PRSVD3 0x38 /* Reserved */ 106#define TUL_PINTL 0x3C /* Interrupt line */ 107#define TUL_PINTP 0x3D /* Interrupt pin */ 108#define TUL_PIGNT 0x3E /* MIN_GNT */ 109#define TUL_PMGNT 0x3F /* MAX_GNT */ 110 111/************************/ 112/* Jasmin Register Set */ 113/************************/ 114#define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */ 115#define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */ 116#define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */ 117 118#define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */ 119#define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */ 120#define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */ 121#define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */ 122 123#define TUL_GINTS 0x50 /* Global Interrupt Status Register */ 124#define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */ 125#define TUL_GCTRL 0x54 /* Global Control Register */ 126#define TUL_GCTRL_EEPROM_BIT 0x04 127#define TUL_GCTRL1 0x55 /* Global Control Register */ 128#define TUL_DMACFG 0x5B /* DMA configuration */ 129#define TUL_NVRAM 0x5D /* Non-volatile RAM port */ 130 131#define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */ 132#define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */ 133#define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */ 134#define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */ 135#define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */ 136#define TUL_SInt 0x84 /* 04 R Interrupt Register */ 137#define TUL_SCtrl0 0x85 /* 05 W Control 0 */ 138#define TUL_SStatus0 0x85 /* 05 R Status 0 */ 139#define TUL_SCtrl1 0x86 /* 06 W Control 1 */ 140#define TUL_SStatus1 0x86 /* 06 R Status 1 */ 141#define TUL_SConfig 0x87 /* 07 W Configuration */ 142#define TUL_SStatus2 0x87 /* 07 R Status 2 */ 143#define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */ 144#define TUL_SOffset 0x88 /* 08 R Offset */ 145#define TUL_SScsiId 0x89 /* 09 W SCSI ID */ 146#define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */ 147#define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */ 148#define TUL_SIdent 0x8A /* 0A R Identify Message Register */ 149#define TUL_SAvail 0x8A /* 0A R Availiable Counter Register */ 150#define TUL_SData 0x8B /* 0B R/W SCSI data in/out */ 151#define TUL_SFifo 0x8C /* 0C R/W FIFO */ 152#define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */ 153#define TUL_SCmd 0x91 /* 11 R/W Command */ 154#define TUL_STest0 0x92 /* 12 R/W Test0 */ 155#define TUL_STest1 0x93 /* 13 R/W Test1 */ 156#define TUL_SCFG1 0x94 /* 14 R/W Configuration */ 157 158#define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */ 159#define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */ 160#define TUL_XCntH 0xD0 /*DMA Transfer Counter */ 161#define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */ 162#define TUL_XCmd 0xD8 /*DMA Command Register */ 163#define TUL_Int 0xDC /*Interrupt Register */ 164#define TUL_XStatus 0xDD /*DMA status Register */ 165#define TUL_Mask 0xE0 /*Interrupt Mask Register */ 166#define TUL_XCtrl 0xE4 /*DMA Control Register */ 167#define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */ 168#define TUL_XFifo 0xE8 /*DMA FIFO */ 169 170#define TUL_WCtrl 0xF7 /*Bus master wait state control */ 171#define TUL_DCtrl 0xFB /*DMA delay control */ 172 173/*----------------------------------------------------------------------*/ 174/* bit definition for Command register of Configuration Space Header */ 175/*----------------------------------------------------------------------*/ 176#define BUSMS 0x04 /* BUS MASTER Enable */ 177#define IOSPA 0x01 /* IO Space Enable */ 178 179/*----------------------------------------------------------------------*/ 180/* Command Codes of Tulip SCSI Command register */ 181/*----------------------------------------------------------------------*/ 182#define TSC_EN_RESEL 0x80 /* Enable Reselection */ 183#define TSC_CMD_COMP 0x84 /* Command Complete Sequence */ 184#define TSC_SEL 0x01 /* Select Without ATN Sequence */ 185#define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */ 186#define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */ 187#define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */ 188#define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */ 189#define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */ 190 191#define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */ 192#define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */ 193#define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */ 194#define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */ 195#define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Information out */ 196#define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Information in */ 197 198#define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Information out */ 199#define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Information in */ 200#define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Information out */ 201#define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Information in */ 202 203#define TSC_MSG_ACCEPT 0x0F /* Message Accept */ 204 205/*----------------------------------------------------------------------*/ 206/* bit definition for Tulip SCSI Control 0 Register */ 207/*----------------------------------------------------------------------*/ 208#define TSC_RST_SEQ 0x20 /* Reset sequence counter */ 209#define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */ 210#define TSC_ABT_CMD 0x04 /* Abort command (sequence) */ 211#define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */ 212#define TSC_RST_BUS 0x01 /* Reset SCSI Bus */ 213 214/*----------------------------------------------------------------------*/ 215/* bit definition for Tulip SCSI Control 1 Register */ 216/*----------------------------------------------------------------------*/ 217#define TSC_EN_SCAM 0x80 /* Enable SCAM */ 218#define TSC_TIMER 0x40 /* Select timeout unit */ 219#define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */ 220#define TSC_PWDN 0x10 /* Power down mode */ 221#define TSC_WIDE_CPU 0x08 /* Wide CPU */ 222#define TSC_HW_RESELECT 0x04 /* Enable HW reselect */ 223#define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */ 224#define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */ 225 226/*----------------------------------------------------------------------*/ 227/* bit definition for Tulip SCSI Configuration Register */ 228/*----------------------------------------------------------------------*/ 229#define TSC_EN_LATCH 0x80 /* Enable phase latch */ 230#define TSC_INITIATOR 0x40 /* Initiator mode */ 231#define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */ 232#define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */ 233#define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */ 234#define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */ 235#define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */ 236#define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */ 237 238#define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST) 239 240#define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */ 241 242/*----------------------------------------------------------------------*/ 243/* bit definition for Tulip SCSI signal Register */ 244/*----------------------------------------------------------------------*/ 245#define TSC_RST_ACK 0x00 /* Release ACK signal */ 246#define TSC_RST_ATN 0x00 /* Release ATN signal */ 247#define TSC_RST_BSY 0x00 /* Release BSY signal */ 248 249#define TSC_SET_ACK 0x40 /* ACK signal */ 250#define TSC_SET_ATN 0x08 /* ATN signal */ 251 252#define TSC_REQI 0x80 /* REQ signal */ 253#define TSC_ACKI 0x40 /* ACK signal */ 254#define TSC_BSYI 0x20 /* BSY signal */ 255#define TSC_SELI 0x10 /* SEL signal */ 256#define TSC_ATNI 0x08 /* ATN signal */ 257#define TSC_MSGI 0x04 /* MSG signal */ 258#define TSC_CDI 0x02 /* C/D signal */ 259#define TSC_IOI 0x01 /* I/O signal */ 260 261 262/*----------------------------------------------------------------------*/ 263/* bit definition for Tulip SCSI Status 0 Register */ 264/*----------------------------------------------------------------------*/ 265#define TSS_INT_PENDING 0x80 /* Interrupt pending */ 266#define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */ 267#define TSS_XFER_CNT 0x20 /* Transfer counter zero */ 268#define TSS_FIFO_EMPTY 0x10 /* FIFO empty */ 269#define TSS_PAR_ERROR 0x08 /* SCSI parity error */ 270#define TSS_PH_MASK 0x07 /* SCSI phase mask */ 271 272/*----------------------------------------------------------------------*/ 273/* bit definition for Tulip SCSI Status 1 Register */ 274/*----------------------------------------------------------------------*/ 275#define TSS_STATUS_RCV 0x08 /* Status received */ 276#define TSS_MSG_SEND 0x40 /* Message sent */ 277#define TSS_CMD_PH_CMP 0x20 /* command phase done */ 278#define TSS_DATA_PH_CMP 0x10 /* Data phase done */ 279#define TSS_STATUS_SEND 0x08 /* Status sent */ 280#define TSS_XFER_CMP 0x04 /* Transfer completed */ 281#define TSS_SEL_CMP 0x02 /* Selection completed */ 282#define TSS_ARB_CMP 0x01 /* Arbitration completed */ 283 284/*----------------------------------------------------------------------*/ 285/* bit definition for Tulip SCSI Status 2 Register */ 286/*----------------------------------------------------------------------*/ 287#define TSS_CMD_ABTED 0x80 /* Command aborted */ 288#define TSS_OFFSET_0 0x40 /* Offset counter zero */ 289#define TSS_FIFO_FULL 0x20 /* FIFO full */ 290#define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */ 291#define TSS_BUSY_RLS 0x08 /* Busy release */ 292#define TSS_PH_MISMATCH 0x04 /* Phase mismatch */ 293#define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */ 294#define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */ 295 296/*----------------------------------------------------------------------*/ 297/* bit definition for Tulip SCSI Interrupt Register */ 298/*----------------------------------------------------------------------*/ 299#define TSS_RESEL_INT 0x80 /* Reselected interrupt */ 300#define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */ 301#define TSS_BUS_SERV 0x20 302#define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */ 303#define TSS_DISC_INT 0x08 /* Disconnected interrupt */ 304#define TSS_SEL_INT 0x04 /* Select interrupt */ 305#define TSS_SCAM_SEL 0x02 /* SCAM selected */ 306#define TSS_FUNC_COMP 0x01 307 308/*----------------------------------------------------------------------*/ 309/* SCSI Phase Codes. */ 310/*----------------------------------------------------------------------*/ 311#define DATA_OUT 0 312#define DATA_IN 1 /* 4 */ 313#define CMD_OUT 2 314#define STATUS_IN 3 /* 6 */ 315#define MSG_OUT 6 /* 3 */ 316#define MSG_IN 7 317 318 319 320/*----------------------------------------------------------------------*/ 321/* Command Codes of Tulip xfer Command register */ 322/*----------------------------------------------------------------------*/ 323#define TAX_X_FORC 0x02 324#define TAX_X_ABT 0x04 325#define TAX_X_CLR_FIFO 0x08 326 327#define TAX_X_IN 0x21 328#define TAX_X_OUT 0x01 329#define TAX_SG_IN 0xA1 330#define TAX_SG_OUT 0x81 331 332/*----------------------------------------------------------------------*/ 333/* Tulip Interrupt Register */ 334/*----------------------------------------------------------------------*/ 335#define XCMP 0x01 336#define FCMP 0x02 337#define XABT 0x04 338#define XERR 0x08 339#define SCMP 0x10 340#define IPEND 0x80 341 342/*----------------------------------------------------------------------*/ 343/* Tulip DMA Status Register */ 344/*----------------------------------------------------------------------*/ 345#define XPEND 0x01 /* Transfer pending */ 346#define FEMPTY 0x02 /* FIFO empty */ 347 348 349 350/*----------------------------------------------------------------------*/ 351/* bit definition for TUL_GCTRL */ 352/*----------------------------------------------------------------------*/ 353#define EXTSG 0x80 354#define EXTAD 0x60 355#define SEG4K 0x08 356#define EEPRG 0x04 357#define MRMUL 0x02 358 359/*----------------------------------------------------------------------*/ 360/* bit definition for TUL_NVRAM */ 361/*----------------------------------------------------------------------*/ 362#define SE2CS 0x08 363#define SE2CLK 0x04 364#define SE2DO 0x02 365#define SE2DI 0x01 366 367 368/************************************************************************/ 369/* Scatter-Gather Element Structure */ 370/************************************************************************/ 371typedef struct SG_Struc { 372 U32 SG_Ptr; /* Data Pointer */ 373 U32 SG_Len; /* Data Length */ 374} SG; 375 376/*********************************************************************** 377 SCSI Control Block 378************************************************************************/ 379typedef struct Scsi_Ctrl_Blk { 380 struct Scsi_Ctrl_Blk *SCB_NxtScb; 381 UBYTE SCB_Status; /*4 */ 382 UBYTE SCB_NxtStat; /*5 */ 383 UBYTE SCB_Mode; /*6 */ 384 UBYTE SCB_Msgin; /*7 SCB_Res0 */ 385 UWORD SCB_SGIdx; /*8 */ 386 UWORD SCB_SGMax; /*A */ 387#ifdef ALPHA 388 U32 SCB_Reserved[2]; /*C */ 389#else 390 U32 SCB_Reserved[3]; /*C */ 391#endif 392 393 U32 SCB_XferLen; /*18 Current xfer len */ 394 U32 SCB_TotXLen; /*1C Total xfer len */ 395 U32 SCB_PAddr; /*20 SCB phy. Addr. */ 396 397 UBYTE SCB_Opcode; /*24 SCB command code */ 398 UBYTE SCB_Flags; /*25 SCB Flags */ 399 UBYTE SCB_Target; /*26 Target Id */ 400 UBYTE SCB_Lun; /*27 Lun */ 401 U32 SCB_BufPtr; /*28 Data Buffer Pointer */ 402 U32 SCB_BufLen; /*2C Data Allocation Length */ 403 UBYTE SCB_SGLen; /*30 SG list # */ 404 UBYTE SCB_SenseLen; /*31 Sense Allocation Length */ 405 UBYTE SCB_HaStat; /*32 */ 406 UBYTE SCB_TaStat; /*33 */ 407 UBYTE SCB_CDBLen; /*34 CDB Length */ 408 UBYTE SCB_Ident; /*35 Identify */ 409 UBYTE SCB_TagMsg; /*36 Tag Message */ 410 UBYTE SCB_TagId; /*37 Queue Tag */ 411 UBYTE SCB_CDB[12]; /*38 */ 412 U32 SCB_SGPAddr; /*44 SG List/Sense Buf phy. Addr. */ 413 U32 SCB_SensePtr; /*48 Sense data pointer */ 414 void (*SCB_Post) (BYTE *, BYTE *); /*4C POST routine */ 415 struct scsi_cmnd *SCB_Srb; /*50 SRB Pointer */ 416 SG SCB_SGList[TOTAL_SG_ENTRY]; /*54 Start of SG list */ 417} SCB; 418 419/* Bit Definition for SCB_Status */ 420#define SCB_RENT 0x01 421#define SCB_PEND 0x02 422#define SCB_CONTIG 0x04 /* Contigent Allegiance */ 423#define SCB_SELECT 0x08 424#define SCB_BUSY 0x10 425#define SCB_DONE 0x20 426 427 428/* Opcodes of SCB_Opcode */ 429#define ExecSCSI 0x1 430#define BusDevRst 0x2 431#define AbortCmd 0x3 432 433 434/* Bit Definition for SCB_Mode */ 435#define SCM_RSENS 0x01 /* request sense mode */ 436 437 438/* Bit Definition for SCB_Flags */ 439#define SCF_DONE 0x01 440#define SCF_POST 0x02 441#define SCF_SENSE 0x04 442#define SCF_DIR 0x18 443#define SCF_NO_DCHK 0x00 444#define SCF_DIN 0x08 445#define SCF_DOUT 0x10 446#define SCF_NO_XF 0x18 447#define SCF_WR_VF 0x20 /* Write verify turn on */ 448#define SCF_POLL 0x40 449#define SCF_SG 0x80 450 451/* Error Codes for SCB_HaStat */ 452#define HOST_SEL_TOUT 0x11 453#define HOST_DO_DU 0x12 454#define HOST_BUS_FREE 0x13 455#define HOST_BAD_PHAS 0x14 456#define HOST_INV_CMD 0x16 457#define HOST_ABORTED 0x1A /* 07/21/98 */ 458#define HOST_SCSI_RST 0x1B 459#define HOST_DEV_RST 0x1C 460 461/* Error Codes for SCB_TaStat */ 462#define TARGET_CHKCOND 0x02 463#define TARGET_BUSY 0x08 464#define INI_QUEUE_FULL 0x28 465 466/* SCSI MESSAGE */ 467#define MSG_COMP 0x00 468#define MSG_EXTEND 0x01 469#define MSG_SDP 0x02 470#define MSG_RESTORE 0x03 471#define MSG_DISC 0x04 472#define MSG_IDE 0x05 473#define MSG_ABORT 0x06 474#define MSG_REJ 0x07 475#define MSG_NOP 0x08 476#define MSG_PARITY 0x09 477#define MSG_LINK_COMP 0x0A 478#define MSG_LINK_FLAG 0x0B 479#define MSG_DEVRST 0x0C 480#define MSG_ABORT_TAG 0x0D 481 482/* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */ 483#define MSG_STAG 0x20 484#define MSG_HTAG 0x21 485#define MSG_OTAG 0x22 486 487#define MSG_IGNOREWIDE 0x23 488 489#define MSG_IDENT 0x80 490 491/*********************************************************************** 492 Target Device Control Structure 493**********************************************************************/ 494 495typedef struct Tar_Ctrl_Struc { 496 UWORD TCS_Flags; /* 0 */ 497 UBYTE TCS_JS_Period; /* 2 */ 498 UBYTE TCS_SConfig0; /* 3 */ 499 500 UWORD TCS_DrvFlags; /* 4 */ 501 UBYTE TCS_DrvHead; /* 6 */ 502 UBYTE TCS_DrvSector; /* 7 */ 503} TCS; 504 505/*********************************************************************** 506 Target Device Control Structure 507**********************************************************************/ 508 509/* Bit Definition for TCF_Flags */ 510#define TCF_SCSI_RATE 0x0007 511#define TCF_EN_DISC 0x0008 512#define TCF_NO_SYNC_NEGO 0x0010 513#define TCF_NO_WDTR 0x0020 514#define TCF_EN_255 0x0040 515#define TCF_EN_START 0x0080 516#define TCF_WDTR_DONE 0x0100 517#define TCF_SYNC_DONE 0x0200 518#define TCF_BUSY 0x0400 519 520 521/* Bit Definition for TCF_DrvFlags */ 522#define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */ 523#define TCF_DRV_EN_TAG 0x0800 524#define TCF_DRV_255_63 0x0400 525 526typedef struct I91u_Adpt_Struc { 527 UWORD ADPT_BIOS; /* 0 */ 528 UWORD ADPT_BASE; /* 1 */ 529 UBYTE ADPT_Bus; /* 2 */ 530 UBYTE ADPT_Device; /* 3 */ 531 UBYTE ADPT_INTR; /* 4 */ 532} INI_ADPT_STRUCT; 533 534 535/*********************************************************************** 536 Host Adapter Control Structure 537************************************************************************/ 538typedef struct Ha_Ctrl_Struc { 539 UWORD HCS_Base; /* 00 */ 540 UWORD HCS_BIOS; /* 02 */ 541 UBYTE HCS_Intr; /* 04 */ 542 UBYTE HCS_SCSI_ID; /* 05 */ 543 UBYTE HCS_MaxTar; /* 06 */ 544 UBYTE HCS_NumScbs; /* 07 */ 545 546 UBYTE HCS_Flags; /* 08 */ 547 UBYTE HCS_Index; /* 09 */ 548 UBYTE HCS_HaId; /* 0A */ 549 UBYTE HCS_Config; /* 0B */ 550 UWORD HCS_IdMask; /* 0C */ 551 UBYTE HCS_Semaph; /* 0E */ 552 UBYTE HCS_Phase; /* 0F */ 553 UBYTE HCS_JSStatus0; /* 10 */ 554 UBYTE HCS_JSInt; /* 11 */ 555 UBYTE HCS_JSStatus1; /* 12 */ 556 UBYTE HCS_SConf1; /* 13 */ 557 558 UBYTE HCS_Msg[8]; /* 14 */ 559 SCB *HCS_NxtAvail; /* 1C */ 560 SCB *HCS_Scb; /* 20 */ 561 SCB *HCS_ScbEnd; /* 24 */ 562 SCB *HCS_NxtPend; /* 28 */ 563 SCB *HCS_NxtContig; /* 2C */ 564 SCB *HCS_ActScb; /* 30 */ 565 TCS *HCS_ActTcs; /* 34 */ 566 567 SCB *HCS_FirstAvail; /* 38 */ 568 SCB *HCS_LastAvail; /* 3C */ 569 SCB *HCS_FirstPend; /* 40 */ 570 SCB *HCS_LastPend; /* 44 */ 571 SCB *HCS_FirstBusy; /* 48 */ 572 SCB *HCS_LastBusy; /* 4C */ 573 SCB *HCS_FirstDone; /* 50 */ 574 SCB *HCS_LastDone; /* 54 */ 575 UBYTE HCS_MaxTags[16]; /* 58 */ 576 UBYTE HCS_ActTags[16]; /* 68 */ 577 TCS HCS_Tcs[MAX_TARGETS]; /* 78 */ 578 spinlock_t HCS_AvailLock; 579 spinlock_t HCS_SemaphLock; 580 struct pci_dev *pci_dev; 581} HCS; 582 583/* Bit Definition for HCB_Config */ 584#define HCC_SCSI_RESET 0x01 585#define HCC_EN_PAR 0x02 586#define HCC_ACT_TERM1 0x04 587#define HCC_ACT_TERM2 0x08 588#define HCC_AUTO_TERM 0x10 589#define HCC_EN_PWR 0x80 590 591/* Bit Definition for HCB_Flags */ 592#define HCF_EXPECT_DISC 0x01 593#define HCF_EXPECT_SELECT 0x02 594#define HCF_EXPECT_RESET 0x10 595#define HCF_EXPECT_DONE_DISC 0x20 596 597/****************************************************************** 598 Serial EEProm 599*******************************************************************/ 600 601typedef struct _NVRAM_SCSI { /* SCSI channel configuration */ 602 UCHAR NVM_ChSCSIID; /* 0Ch -> Channel SCSI ID */ 603 UCHAR NVM_ChConfig1; /* 0Dh -> Channel config 1 */ 604 UCHAR NVM_ChConfig2; /* 0Eh -> Channel config 2 */ 605 UCHAR NVM_NumOfTarg; /* 0Fh -> Number of SCSI target */ 606 /* SCSI target configuration */ 607 UCHAR NVM_Targ0Config; /* 10h -> Target 0 configuration */ 608 UCHAR NVM_Targ1Config; /* 11h -> Target 1 configuration */ 609 UCHAR NVM_Targ2Config; /* 12h -> Target 2 configuration */ 610 UCHAR NVM_Targ3Config; /* 13h -> Target 3 configuration */ 611 UCHAR NVM_Targ4Config; /* 14h -> Target 4 configuration */ 612 UCHAR NVM_Targ5Config; /* 15h -> Target 5 configuration */ 613 UCHAR NVM_Targ6Config; /* 16h -> Target 6 configuration */ 614 UCHAR NVM_Targ7Config; /* 17h -> Target 7 configuration */ 615 UCHAR NVM_Targ8Config; /* 18h -> Target 8 configuration */ 616 UCHAR NVM_Targ9Config; /* 19h -> Target 9 configuration */ 617 UCHAR NVM_TargAConfig; /* 1Ah -> Target A configuration */ 618 UCHAR NVM_TargBConfig; /* 1Bh -> Target B configuration */ 619 UCHAR NVM_TargCConfig; /* 1Ch -> Target C configuration */ 620 UCHAR NVM_TargDConfig; /* 1Dh -> Target D configuration */ 621 UCHAR NVM_TargEConfig; /* 1Eh -> Target E configuration */ 622 UCHAR NVM_TargFConfig; /* 1Fh -> Target F configuration */ 623} NVRAM_SCSI; 624 625typedef struct _NVRAM { 626/*----------header ---------------*/ 627 USHORT NVM_Signature; /* 0,1: Signature */ 628 UCHAR NVM_Size; /* 2: Size of data structure */ 629 UCHAR NVM_Revision; /* 3: Revision of data structure */ 630 /* ----Host Adapter Structure ---- */ 631 UCHAR NVM_ModelByte0; /* 4: Model number (byte 0) */ 632 UCHAR NVM_ModelByte1; /* 5: Model number (byte 1) */ 633 UCHAR NVM_ModelInfo; /* 6: Model information */ 634 UCHAR NVM_NumOfCh; /* 7: Number of SCSI channel */ 635 UCHAR NVM_BIOSConfig1; /* 8: BIOS configuration 1 */ 636 UCHAR NVM_BIOSConfig2; /* 9: BIOS configuration 2 */ 637 UCHAR NVM_HAConfig1; /* A: Hoat adapter configuration 1 */ 638 UCHAR NVM_HAConfig2; /* B: Hoat adapter configuration 2 */ 639 NVRAM_SCSI NVM_SCSIInfo[2]; 640 UCHAR NVM_reserved[10]; 641 /* ---------- CheckSum ---------- */ 642 USHORT NVM_CheckSum; /* 0x3E, 0x3F: Checksum of NVRam */ 643} NVRAM, *PNVRAM; 644 645/* Bios Configuration for nvram->BIOSConfig1 */ 646#define NBC1_ENABLE 0x01 /* BIOS enable */ 647#define NBC1_8DRIVE 0x02 /* Support more than 2 drives */ 648#define NBC1_REMOVABLE 0x04 /* Support removable drive */ 649#define NBC1_INT19 0x08 /* Intercept int 19h */ 650#define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */ 651#define NBC1_LUNSUPPORT 0x40 /* Support LUN */ 652 653/* HA Configuration Byte 1 */ 654#define NHC1_BOOTIDMASK 0x0F /* Boot ID number */ 655#define NHC1_LUNMASK 0x70 /* Boot LUN number */ 656#define NHC1_CHANMASK 0x80 /* Boot Channel number */ 657 658/* Bit definition for nvram->SCSIconfig1 */ 659#define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */ 660#define NCC1_PARITYCHK 0x02 /* SCSI parity enable */ 661#define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */ 662#define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */ 663#define NCC1_AUTOTERM 0x10 /* Enable auto terminator */ 664#define NCC1_PWRMGR 0x80 /* Enable power management */ 665 666/* Bit definition for SCSI Target configuration byte */ 667#define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */ 668#define NTC_SYNC 0x10 /* SYNC_NEGO */ 669#define NTC_NO_WDTR 0x20 /* SYNC_NEGO */ 670#define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */ 671#define NTC_SPINUP 0x80 /* Start disk drive */ 672 673/* Default NVRam values */ 674#define INI_SIGNATURE 0xC925 675#define NBC1_DEFAULT (NBC1_ENABLE) 676#define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK) 677#define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT) 678 679/* SCSI related definition */ 680#define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */ 681#define DISC_ALLOW 0xC0 /* Disconnect is allowed */ 682#define SCSICMD_RequestSense 0x03 683 684typedef struct _HCSinfo { 685 ULONG base; 686 UCHAR vec; 687 UCHAR bios; /* High byte of BIOS address */ 688 USHORT BaseAndBios; /* high byte: pHcsInfo->bios,low byte:pHcsInfo->base */ 689} HCSINFO; 690 691#define TUL_RD(x,y) (UCHAR)(inb( (int)((ULONG)(x+y)) )) 692#define TUL_RDLONG(x,y) (ULONG)(inl((int)((ULONG)(x+y)) )) 693#define TUL_WR( adr,data) outb( (UCHAR)(data), (int)(adr)) 694#define TUL_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr)) 695#define TUL_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr)) 696 697#define SCSI_ABORT_SNOOZE 0 698#define SCSI_ABORT_SUCCESS 1 699#define SCSI_ABORT_PENDING 2 700#define SCSI_ABORT_BUSY 3 701#define SCSI_ABORT_NOT_RUNNING 4 702#define SCSI_ABORT_ERROR 5 703 704#define SCSI_RESET_SNOOZE 0 705#define SCSI_RESET_PUNT 1 706#define SCSI_RESET_SUCCESS 2 707#define SCSI_RESET_PENDING 3 708#define SCSI_RESET_WAKEUP 4 709#define SCSI_RESET_NOT_RUNNING 5 710#define SCSI_RESET_ERROR 6 711 712#define SCSI_RESET_SYNCHRONOUS 0x01 713#define SCSI_RESET_ASYNCHRONOUS 0x02 714#define SCSI_RESET_SUGGEST_BUS_RESET 0x04 715#define SCSI_RESET_SUGGEST_HOST_RESET 0x08 716 717#define SCSI_RESET_BUS_RESET 0x100 718#define SCSI_RESET_HOST_RESET 0x200 719#define SCSI_RESET_ACTION 0xff 720