1/* cyberstorm.c: Driver for CyberStorm SCSI Controller. 2 * 3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk) 4 * 5 * The CyberStorm SCSI driver is based on David S. Miller's ESP driver 6 * for the Sparc computers. 7 * 8 * This work was made possible by Phase5 who willingly (and most generously) 9 * supported me with hardware and all the information I needed. 10 */ 11 12/* TODO: 13 * 14 * 1) Figure out how to make a cleaner merge with the sparc driver with regard 15 * to the caches and the Sparc MMU mapping. 16 * 2) Make as few routines required outside the generic driver. A lot of the 17 * routines in this file used to be inline! 18 */ 19 20#include <linux/module.h> 21 22#include <linux/init.h> 23#include <linux/kernel.h> 24#include <linux/delay.h> 25#include <linux/types.h> 26#include <linux/string.h> 27#include <linux/slab.h> 28#include <linux/blkdev.h> 29#include <linux/proc_fs.h> 30#include <linux/stat.h> 31#include <linux/interrupt.h> 32 33#include "scsi.h" 34#include <scsi/scsi_host.h> 35#include "NCR53C9x.h" 36 37#include <linux/zorro.h> 38#include <asm/irq.h> 39#include <asm/amigaints.h> 40#include <asm/amigahw.h> 41 42#include <asm/pgtable.h> 43 44/* The controller registers can be found in the Z2 config area at these 45 * offsets: 46 */ 47#define CYBER_ESP_ADDR 0xf400 48#define CYBER_DMA_ADDR 0xf800 49 50 51/* The CyberStorm DMA interface */ 52struct cyber_dma_registers { 53 volatile unsigned char dma_addr0; /* DMA address (MSB) [0x000] */ 54 unsigned char dmapad1[1]; 55 volatile unsigned char dma_addr1; /* DMA address [0x002] */ 56 unsigned char dmapad2[1]; 57 volatile unsigned char dma_addr2; /* DMA address [0x004] */ 58 unsigned char dmapad3[1]; 59 volatile unsigned char dma_addr3; /* DMA address (LSB) [0x006] */ 60 unsigned char dmapad4[0x3fb]; 61 volatile unsigned char cond_reg; /* DMA cond (ro) [0x402] */ 62#define ctrl_reg cond_reg /* DMA control (wo) [0x402] */ 63}; 64 65/* DMA control bits */ 66#define CYBER_DMA_LED 0x80 /* HD led control 1 = on */ 67#define CYBER_DMA_WRITE 0x40 /* DMA direction. 1 = write */ 68#define CYBER_DMA_Z3 0x20 /* 16 (Z2) or 32 (CHIP/Z3) bit DMA transfer */ 69 70/* DMA status bits */ 71#define CYBER_DMA_HNDL_INTR 0x80 /* DMA IRQ pending? */ 72 73/* The bits below appears to be Phase5 Debug bits only; they were not 74 * described by Phase5 so using them may seem a bit stupid... 75 */ 76#define CYBER_HOST_ID 0x02 /* If set, host ID should be 7, otherwise 77 * it should be 6. 78 */ 79#define CYBER_SLOW_CABLE 0x08 /* If *not* set, assume SLOW_CABLE */ 80 81static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); 82static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp); 83static void dma_dump_state(struct NCR_ESP *esp); 84static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length); 85static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length); 86static void dma_ints_off(struct NCR_ESP *esp); 87static void dma_ints_on(struct NCR_ESP *esp); 88static int dma_irq_p(struct NCR_ESP *esp); 89static void dma_led_off(struct NCR_ESP *esp); 90static void dma_led_on(struct NCR_ESP *esp); 91static int dma_ports_p(struct NCR_ESP *esp); 92static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write); 93 94static unsigned char ctrl_data = 0; /* Keep backup of the stuff written 95 * to ctrl_reg. Always write a copy 96 * to this register when writing to 97 * the hardware register! 98 */ 99 100static volatile unsigned char cmd_buffer[16]; 101 /* This is where all commands are put 102 * before they are transferred to the ESP chip 103 * via PIO. 104 */ 105 106/***************************************************************** Detection */ 107int __init cyber_esp_detect(struct scsi_host_template *tpnt) 108{ 109 struct NCR_ESP *esp; 110 struct zorro_dev *z = NULL; 111 unsigned long address; 112 113 while ((z = zorro_find_device(ZORRO_WILDCARD, z))) { 114 unsigned long board = z->resource.start; 115 if ((z->id == ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM || 116 z->id == ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060) && 117 request_mem_region(board+CYBER_ESP_ADDR, 118 sizeof(struct ESP_regs), "NCR53C9x")) { 119 /* Figure out if this is a CyberStorm or really a 120 * Fastlane/Blizzard Mk II by looking at the board size. 121 * CyberStorm maps 64kB 122 * (ZORRO_PROD_PHASE5_BLIZZARD_1220_CYBERSTORM does anyway) 123 */ 124 if(z->resource.end-board != 0xffff) { 125 release_mem_region(board+CYBER_ESP_ADDR, 126 sizeof(struct ESP_regs)); 127 return 0; 128 } 129 esp = esp_allocate(tpnt, (void *)board + CYBER_ESP_ADDR, 0); 130 131 /* Do command transfer with programmed I/O */ 132 esp->do_pio_cmds = 1; 133 134 /* Required functions */ 135 esp->dma_bytes_sent = &dma_bytes_sent; 136 esp->dma_can_transfer = &dma_can_transfer; 137 esp->dma_dump_state = &dma_dump_state; 138 esp->dma_init_read = &dma_init_read; 139 esp->dma_init_write = &dma_init_write; 140 esp->dma_ints_off = &dma_ints_off; 141 esp->dma_ints_on = &dma_ints_on; 142 esp->dma_irq_p = &dma_irq_p; 143 esp->dma_ports_p = &dma_ports_p; 144 esp->dma_setup = &dma_setup; 145 146 /* Optional functions */ 147 esp->dma_barrier = 0; 148 esp->dma_drain = 0; 149 esp->dma_invalidate = 0; 150 esp->dma_irq_entry = 0; 151 esp->dma_irq_exit = 0; 152 esp->dma_led_on = &dma_led_on; 153 esp->dma_led_off = &dma_led_off; 154 esp->dma_poll = 0; 155 esp->dma_reset = 0; 156 157 /* SCSI chip speed */ 158 esp->cfreq = 40000000; 159 160 /* The DMA registers on the CyberStorm are mapped 161 * relative to the device (i.e. in the same Zorro 162 * I/O block). 163 */ 164 address = (unsigned long)ZTWO_VADDR(board); 165 esp->dregs = (void *)(address + CYBER_DMA_ADDR); 166 167 /* ESP register base */ 168 esp->eregs = (struct ESP_regs *)(address + CYBER_ESP_ADDR); 169 170 /* Set the command buffer */ 171 esp->esp_command = cmd_buffer; 172 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer); 173 174 esp->irq = IRQ_AMIGA_PORTS; 175 request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED, 176 "CyberStorm SCSI", esp->ehost); 177 /* Figure out our scsi ID on the bus */ 178 /* The DMA cond flag contains a hardcoded jumper bit 179 * which can be used to select host number 6 or 7. 180 * However, even though it may change, we use a hardcoded 181 * value of 7. 182 */ 183 esp->scsi_id = 7; 184 185 /* We don't have a differential SCSI-bus. */ 186 esp->diff = 0; 187 188 esp_initialize(esp); 189 190 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use); 191 esps_running = esps_in_use; 192 return esps_in_use; 193 } 194 } 195 return 0; 196} 197 198/************************************************************* DMA Functions */ 199static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count) 200{ 201 return fifo_count; 202} 203 204static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp) 205{ 206 /* I don't think there's any limit on the CyberDMA. So we use what 207 * the ESP chip can handle (24 bit). 208 */ 209 unsigned long sz = sp->SCp.this_residual; 210 if(sz > 0x1000000) 211 sz = 0x1000000; 212 return sz; 213} 214 215static void dma_dump_state(struct NCR_ESP *esp) 216{ 217 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n", 218 esp->esp_id, ((struct cyber_dma_registers *) 219 (esp->dregs))->cond_reg)); 220 ESPLOG(("intreq:<%04x>, intena:<%04x>\n", 221 amiga_custom.intreqr, amiga_custom.intenar)); 222} 223 224static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length) 225{ 226 struct cyber_dma_registers *dregs = 227 (struct cyber_dma_registers *) esp->dregs; 228 229 cache_clear(addr, length); 230 231 addr &= ~(1); 232 dregs->dma_addr0 = (addr >> 24) & 0xff; 233 dregs->dma_addr1 = (addr >> 16) & 0xff; 234 dregs->dma_addr2 = (addr >> 8) & 0xff; 235 dregs->dma_addr3 = (addr ) & 0xff; 236 ctrl_data &= ~(CYBER_DMA_WRITE); 237 238 /* Check if physical address is outside Z2 space and of 239 * block length/block aligned in memory. If this is the 240 * case, enable 32 bit transfer. In all other cases, fall back 241 * to 16 bit transfer. 242 * Obviously 32 bit transfer should be enabled if the DMA address 243 * and length are 32 bit aligned. However, this leads to some 244 * strange behavior. Even 64 bit aligned addr/length fails. 245 * Until I've found a reason for this, 32 bit transfer is only 246 * used for full-block transfers (1kB). 247 * -jskov 248 */ 249 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */ 250 dregs->ctrl_reg = ctrl_data; 251} 252 253static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length) 254{ 255 struct cyber_dma_registers *dregs = 256 (struct cyber_dma_registers *) esp->dregs; 257 258 cache_push(addr, length); 259 260 addr |= 1; 261 dregs->dma_addr0 = (addr >> 24) & 0xff; 262 dregs->dma_addr1 = (addr >> 16) & 0xff; 263 dregs->dma_addr2 = (addr >> 8) & 0xff; 264 dregs->dma_addr3 = (addr ) & 0xff; 265 ctrl_data |= CYBER_DMA_WRITE; 266 267 /* See comment above */ 268 ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */ 269 dregs->ctrl_reg = ctrl_data; 270} 271 272static void dma_ints_off(struct NCR_ESP *esp) 273{ 274 disable_irq(esp->irq); 275} 276 277static void dma_ints_on(struct NCR_ESP *esp) 278{ 279 enable_irq(esp->irq); 280} 281 282static int dma_irq_p(struct NCR_ESP *esp) 283{ 284 /* It's important to check the DMA IRQ bit in the correct way! */ 285 return ((esp_read(esp->eregs->esp_status) & ESP_STAT_INTR) && 286 ((((struct cyber_dma_registers *)(esp->dregs))->cond_reg) & 287 CYBER_DMA_HNDL_INTR)); 288} 289 290static void dma_led_off(struct NCR_ESP *esp) 291{ 292 ctrl_data &= ~CYBER_DMA_LED; 293 ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data; 294} 295 296static void dma_led_on(struct NCR_ESP *esp) 297{ 298 ctrl_data |= CYBER_DMA_LED; 299 ((struct cyber_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data; 300} 301 302static int dma_ports_p(struct NCR_ESP *esp) 303{ 304 return ((amiga_custom.intenar) & IF_PORTS); 305} 306 307static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write) 308{ 309 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory" 310 * so when (write) is true, it actually means READ! 311 */ 312 if(write){ 313 dma_init_read(esp, addr, count); 314 } else { 315 dma_init_write(esp, addr, count); 316 } 317} 318 319#define HOSTS_C 320 321int cyber_esp_release(struct Scsi_Host *instance) 322{ 323#ifdef MODULE 324 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev; 325 326 esp_deallocate((struct NCR_ESP *)instance->hostdata); 327 esp_release(); 328 release_mem_region(address, sizeof(struct ESP_regs)); 329 free_irq(IRQ_AMIGA_PORTS, esp_intr); 330#endif 331 return 1; 332} 333 334 335static struct scsi_host_template driver_template = { 336 .proc_name = "esp-cyberstorm", 337 .proc_info = esp_proc_info, 338 .name = "CyberStorm SCSI", 339 .detect = cyber_esp_detect, 340 .slave_alloc = esp_slave_alloc, 341 .slave_destroy = esp_slave_destroy, 342 .release = cyber_esp_release, 343 .queuecommand = esp_queue, 344 .eh_abort_handler = esp_abort, 345 .eh_bus_reset_handler = esp_reset, 346 .can_queue = 7, 347 .this_id = 7, 348 .sg_tablesize = SG_ALL, 349 .cmd_per_lun = 1, 350 .use_clustering = ENABLE_CLUSTERING 351}; 352 353 354#include "scsi_module.c" 355 356MODULE_LICENSE("GPL"); 357