1/* 2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. 3 * 4 * (C) 1999-2000 Magnus Damm <damm@bitsmart.com> 5 * (C) 2001-2002 Montavista Software, Inc. 6 * <mlocke@mvista.com> 7 * 8 * Support for two slots by Cyclades Corporation 9 * <oliver.kurth@cyclades.de> 10 * Further fixes, v2.6 kernel port 11 * <marcelo.tosatti@cyclades.com> 12 * 13 * Some fixes, additions (C) 2005 Montavista Software, Inc. 14 * <vbordug@ru.mvista.com> 15 * 16 * "The ExCA standard specifies that socket controllers should provide 17 * two IO and five memory windows per socket, which can be independently 18 * configured and positioned in the host address space and mapped to 19 * arbitrary segments of card address space. " - David A Hinds. 1999 20 * 21 * This controller does _not_ meet the ExCA standard. 22 * 23 * m8xx pcmcia controller brief info: 24 * + 8 windows (attrib, mem, i/o) 25 * + up to two slots (SLOT_A and SLOT_B) 26 * + inputpins, outputpins, event and mask registers. 27 * - no offset register. sigh. 28 * 29 * Because of the lacking offset register we must map the whole card. 30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. 31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO 32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. 33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. 34 * They are maximum 64KByte each... 35 */ 36 37#include <linux/module.h> 38#include <linux/init.h> 39#include <linux/types.h> 40#include <linux/fcntl.h> 41#include <linux/string.h> 42 43#include <asm/io.h> 44#include <asm/bitops.h> 45#include <asm/system.h> 46 47#include <linux/kernel.h> 48#include <linux/errno.h> 49#include <linux/slab.h> 50#include <linux/timer.h> 51#include <linux/ioport.h> 52#include <linux/delay.h> 53#include <linux/interrupt.h> 54#include <linux/platform_device.h> 55 56#include <asm/mpc8xx.h> 57#include <asm/8xx_immap.h> 58#include <asm/irq.h> 59 60#include <pcmcia/version.h> 61#include <pcmcia/cs_types.h> 62#include <pcmcia/cs.h> 63#include <pcmcia/ss.h> 64 65#ifdef PCMCIA_DEBUG 66static int pc_debug = PCMCIA_DEBUG; 67module_param(pc_debug, int, 0); 68#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args); 69#else 70#define dprintk(args...) 71#endif 72 73#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) 74#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) 75 76static const char *version = "Version 0.06, Aug 2005"; 77MODULE_LICENSE("Dual MPL/GPL"); 78 79#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 80 81/* The RPX series use SLOT_B */ 82#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) 83#define CONFIG_PCMCIA_SLOT_B 84#define CONFIG_BD_IS_MHZ 85#endif 86 87/* The ADS board use SLOT_A */ 88#ifdef CONFIG_ADS 89#define CONFIG_PCMCIA_SLOT_A 90#define CONFIG_BD_IS_MHZ 91#endif 92 93/* The FADS series are a mess */ 94#ifdef CONFIG_FADS 95#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) 96#define CONFIG_PCMCIA_SLOT_A 97#else 98#define CONFIG_PCMCIA_SLOT_B 99#endif 100#endif 101 102#if defined(CONFIG_MPC885ADS) 103#define CONFIG_PCMCIA_SLOT_A 104#define PCMCIA_GLITCHY_CD 105#endif 106 107/* Cyclades ACS uses both slots */ 108#ifdef CONFIG_PRxK 109#define CONFIG_PCMCIA_SLOT_A 110#define CONFIG_PCMCIA_SLOT_B 111#endif 112 113#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 114 115#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 116 117#define PCMCIA_SOCKETS_NO 2 118/* We have only 8 windows, dualsocket support will be limited. */ 119#define PCMCIA_MEM_WIN_NO 2 120#define PCMCIA_IO_WIN_NO 2 121#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" 122 123#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) 124 125#define PCMCIA_SOCKETS_NO 1 126/* full support for one slot */ 127#define PCMCIA_MEM_WIN_NO 5 128#define PCMCIA_IO_WIN_NO 2 129 130/* define _slot_ to be able to optimize macros */ 131 132#ifdef CONFIG_PCMCIA_SLOT_A 133#define _slot_ 0 134#define PCMCIA_SLOT_MSG "SLOT_A" 135#else 136#define _slot_ 1 137#define PCMCIA_SLOT_MSG "SLOT_B" 138#endif 139 140#else 141#error m8xx_pcmcia: Bad configuration! 142#endif 143 144/* ------------------------------------------------------------------------- */ 145 146#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ 147#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ 148#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ 149 150#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */ 151 152/* ------------------------------------------------------------------------- */ 153 154/* 2.4.x and newer has this always in HZ */ 155#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq)) 156 157static int pcmcia_schlvl = PCMCIA_SCHLVL; 158 159static DEFINE_SPINLOCK(events_lock); 160 161 162#define PCMCIA_SOCKET_KEY_5V 1 163#define PCMCIA_SOCKET_KEY_LV 2 164 165/* look up table for pgcrx registers */ 166static u32 *m8xx_pgcrx[2] = { 167 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra, 168 &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb 169}; 170 171/* 172 * This structure is used to address each window in the PCMCIA controller. 173 * 174 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly 175 * after pcmcia_win[n]... 176 */ 177 178struct pcmcia_win { 179 u32 br; 180 u32 or; 181}; 182 183/* 184 * For some reason the hardware guys decided to make both slots share 185 * some registers. 186 * 187 * Could someone invent object oriented hardware ? 188 * 189 * The macros are used to get the right bit from the registers. 190 * SLOT_A : slot = 0 191 * SLOT_B : slot = 1 192 */ 193 194#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) 195#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) 196#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) 197#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) 198 199#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) 200#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) 201#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) 202#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) 203#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) 204#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) 205#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) 206#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) 207#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) 208#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) 209#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) 210 211#define M8XX_PCMCIA_POR_VALID 0x00000001 212#define M8XX_PCMCIA_POR_WRPROT 0x00000002 213#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 214#define M8XX_PCMCIA_POR_IO 0x00000018 215#define M8XX_PCMCIA_POR_16BIT 0x00000040 216 217#define M8XX_PGCRX(slot) m8xx_pgcrx[slot] 218 219#define M8XX_PGCRX_CXOE 0x00000080 220#define M8XX_PGCRX_CXRESET 0x00000040 221 222/* we keep one lookup table per socket to check flags */ 223 224#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ 225 226struct event_table { 227 u32 regbit; 228 u32 eventbit; 229}; 230 231struct socket_info { 232 void (*handler)(void *info, u32 events); 233 void *info; 234 235 u32 slot; 236 237 socket_state_t state; 238 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; 239 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; 240 struct event_table events[PCMCIA_EVENTS_MAX]; 241 struct pcmcia_socket socket; 242}; 243 244static struct socket_info socket[PCMCIA_SOCKETS_NO]; 245 246/* 247 * Search this table to see if the windowsize is 248 * supported... 249 */ 250 251#define M8XX_SIZES_NO 32 252 253static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = 254{ 255 0x00000001, 0x00000002, 0x00000008, 0x00000004, 256 0x00000080, 0x00000040, 0x00000010, 0x00000020, 257 0x00008000, 0x00004000, 0x00001000, 0x00002000, 258 0x00000100, 0x00000200, 0x00000800, 0x00000400, 259 260 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, 261 0x01000000, 0x02000000, 0xffffffff, 0x04000000, 262 0x00010000, 0x00020000, 0x00080000, 0x00040000, 263 0x00800000, 0x00400000, 0x00100000, 0x00200000 264}; 265 266/* ------------------------------------------------------------------------- */ 267 268static irqreturn_t m8xx_interrupt(int irq, void *dev); 269 270#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ 271 272/* ------------------------------------------------------------------------- */ 273/* board specific stuff: */ 274/* voltage_set(), hardware_enable() and hardware_disable() */ 275/* ------------------------------------------------------------------------- */ 276/* RPX Boards from Embedded Planet */ 277 278#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) 279 280/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. 281 * SYPCR is write once only, therefore must the slowest memory be faster 282 * than the bus monitor or we will get a machine check due to the bus timeout. 283 */ 284 285#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" 286 287#undef PCMCIA_BMT_LIMIT 288#define PCMCIA_BMT_LIMIT (6*8) 289 290static int voltage_set(int slot, int vcc, int vpp) 291{ 292 u32 reg = 0; 293 294 switch(vcc) { 295 case 0: break; 296 case 33: 297 reg |= BCSR1_PCVCTL4; 298 break; 299 case 50: 300 reg |= BCSR1_PCVCTL5; 301 break; 302 default: 303 return 1; 304 } 305 306 switch(vpp) { 307 case 0: break; 308 case 33: 309 case 50: 310 if(vcc == vpp) 311 reg |= BCSR1_PCVCTL6; 312 else 313 return 1; 314 break; 315 case 120: 316 reg |= BCSR1_PCVCTL7; 317 default: 318 return 1; 319 } 320 321 if(!((vcc == 50) || (vcc == 0))) 322 return 1; 323 324 /* first, turn off all power */ 325 326 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7)); 327 328 /* enable new powersettings */ 329 330 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg); 331 332 return 0; 333} 334 335#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V 336#define hardware_enable(_slot_) /* No hardware to enable */ 337#define hardware_disable(_slot_) /* No hardware to disable */ 338 339#endif /* CONFIG_RPXCLASSIC */ 340 341/* FADS Boards from Motorola */ 342 343#if defined(CONFIG_FADS) 344 345#define PCMCIA_BOARD_MSG "FADS" 346 347static int voltage_set(int slot, int vcc, int vpp) 348{ 349 u32 reg = 0; 350 351 switch(vcc) { 352 case 0: 353 break; 354 case 33: 355 reg |= BCSR1_PCCVCC0; 356 break; 357 case 50: 358 reg |= BCSR1_PCCVCC1; 359 break; 360 default: 361 return 1; 362 } 363 364 switch(vpp) { 365 case 0: 366 break; 367 case 33: 368 case 50: 369 if(vcc == vpp) 370 reg |= BCSR1_PCCVPP1; 371 else 372 return 1; 373 break; 374 case 120: 375 if ((vcc == 33) || (vcc == 50)) 376 reg |= BCSR1_PCCVPP0; 377 else 378 return 1; 379 default: 380 return 1; 381 } 382 383 /* first, turn off all power */ 384 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); 385 386 /* enable new powersettings */ 387 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | reg); 388 389 return 0; 390} 391 392#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V 393 394static void hardware_enable(int slot) 395{ 396 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~BCSR1_PCCEN); 397} 398 399static void hardware_disable(int slot) 400{ 401 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | BCSR1_PCCEN); 402} 403 404#endif 405 406/* MPC885ADS Boards */ 407 408#if defined(CONFIG_MPC885ADS) 409 410#define PCMCIA_BOARD_MSG "MPC885ADS" 411 412static int voltage_set(int slot, int vcc, int vpp) 413{ 414 u32 reg = 0; 415 unsigned *bcsr_io; 416 417 bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); 418 419 switch(vcc) { 420 case 0: 421 break; 422 case 33: 423 reg |= BCSR1_PCCVCC0; 424 break; 425 case 50: 426 reg |= BCSR1_PCCVCC1; 427 break; 428 default: 429 goto out_unmap; 430 } 431 432 switch(vpp) { 433 case 0: 434 break; 435 case 33: 436 case 50: 437 if(vcc == vpp) 438 reg |= BCSR1_PCCVPP1; 439 else 440 goto out_unmap; 441 break; 442 case 120: 443 if ((vcc == 33) || (vcc == 50)) 444 reg |= BCSR1_PCCVPP0; 445 else 446 goto out_unmap; 447 default: 448 goto out_unmap; 449 } 450 451 /* first, turn off all power */ 452 out_be32(bcsr_io, in_be32(bcsr_io) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); 453 454 /* enable new powersettings */ 455 out_be32(bcsr_io, in_be32(bcsr_io) | reg); 456 457 iounmap(bcsr_io); 458 return 0; 459 460out_unmap: 461 iounmap(bcsr_io); 462 return 1; 463} 464 465#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V 466 467static void hardware_enable(int slot) 468{ 469 unsigned *bcsr_io; 470 471 bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); 472 out_be32(bcsr_io, in_be32(bcsr_io) & ~BCSR1_PCCEN); 473 iounmap(bcsr_io); 474} 475 476static void hardware_disable(int slot) 477{ 478 unsigned *bcsr_io; 479 480 bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); 481 out_be32(bcsr_io, in_be32(bcsr_io) | BCSR1_PCCEN); 482 iounmap(bcsr_io); 483} 484 485#endif 486 487/* ------------------------------------------------------------------------- */ 488/* Motorola MBX860 */ 489 490#if defined(CONFIG_MBX) 491 492#define PCMCIA_BOARD_MSG "MBX" 493 494static int voltage_set(int slot, int vcc, int vpp) 495{ 496 u8 reg = 0; 497 498 switch(vcc) { 499 case 0: 500 break; 501 case 33: 502 reg |= CSR2_VCC_33; 503 break; 504 case 50: 505 reg |= CSR2_VCC_50; 506 break; 507 default: 508 return 1; 509 } 510 511 switch(vpp) { 512 case 0: 513 break; 514 case 33: 515 case 50: 516 if(vcc == vpp) 517 reg |= CSR2_VPP_VCC; 518 else 519 return 1; 520 break; 521 case 120: 522 if ((vcc == 33) || (vcc == 50)) 523 reg |= CSR2_VPP_12; 524 else 525 return 1; 526 default: 527 return 1; 528 } 529 530 /* first, turn off all power */ 531 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); 532 533 /* enable new powersettings */ 534 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) | reg); 535 536 return 0; 537} 538 539#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V 540#define hardware_enable(_slot_) /* No hardware to enable */ 541#define hardware_disable(_slot_) /* No hardware to disable */ 542 543#endif /* CONFIG_MBX */ 544 545#if defined(CONFIG_PRxK) 546#include <asm/cpld.h> 547extern volatile fpga_pc_regs *fpga_pc; 548 549#define PCMCIA_BOARD_MSG "MPC855T" 550 551static int voltage_set(int slot, int vcc, int vpp) 552{ 553 u8 reg = 0; 554 u8 regread; 555 cpld_regs *ccpld = get_cpld(); 556 557 switch(vcc) { 558 case 0: 559 break; 560 case 33: 561 reg |= PCMCIA_VCC_33; 562 break; 563 case 50: 564 reg |= PCMCIA_VCC_50; 565 break; 566 default: 567 return 1; 568 } 569 570 switch(vpp) { 571 case 0: 572 break; 573 case 33: 574 case 50: 575 if(vcc == vpp) 576 reg |= PCMCIA_VPP_VCC; 577 else 578 return 1; 579 break; 580 case 120: 581 if ((vcc == 33) || (vcc == 50)) 582 reg |= PCMCIA_VPP_12; 583 else 584 return 1; 585 default: 586 return 1; 587 } 588 589 reg = reg >> (slot << 2); 590 regread = in_8(&ccpld->fpga_pc_ctl); 591 if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { 592 /* enable new powersettings */ 593 regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)); 594 out_8(&ccpld->fpga_pc_ctl, reg | regread); 595 msleep(100); 596 } 597 598 return 0; 599} 600 601#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV 602#define hardware_enable(_slot_) /* No hardware to enable */ 603#define hardware_disable(_slot_) /* No hardware to disable */ 604 605#endif /* CONFIG_PRxK */ 606 607static void m8xx_shutdown(void) 608{ 609 u32 m, i; 610 struct pcmcia_win *w; 611 612 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){ 613 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; 614 615 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i)); 616 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i)); 617 618 /* turn off interrupt and disable CxOE */ 619 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); 620 621 /* turn off memory windows */ 622 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) { 623 out_be32(&w->or, 0); /* set to not valid */ 624 w++; 625 } 626 627 /* turn off voltage */ 628 voltage_set(i, 0, 0); 629 630 /* disable external hardware */ 631 hardware_disable(i); 632 } 633 634 free_irq(pcmcia_schlvl, NULL); 635} 636 637static struct device_driver m8xx_driver = { 638 .name = "m8xx-pcmcia", 639 .bus = &platform_bus_type, 640 .suspend = pcmcia_socket_dev_suspend, 641 .resume = pcmcia_socket_dev_resume, 642}; 643 644static struct platform_device m8xx_device = { 645 .name = "m8xx-pcmcia", 646 .id = 0, 647}; 648 649static u32 pending_events[PCMCIA_SOCKETS_NO]; 650static DEFINE_SPINLOCK(pending_event_lock); 651 652static irqreturn_t m8xx_interrupt(int irq, void *dev) 653{ 654 struct socket_info *s; 655 struct event_table *e; 656 unsigned int i, events, pscr, pipr, per; 657 658 dprintk("Interrupt!\n"); 659 /* get interrupt sources */ 660 661 pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr); 662 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr); 663 per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per); 664 665 for(i = 0; i < PCMCIA_SOCKETS_NO; i++) { 666 s = &socket[i]; 667 e = &s->events[0]; 668 events = 0; 669 670 while(e->regbit) { 671 if(pscr & e->regbit) 672 events |= e->eventbit; 673 674 e++; 675 } 676 677 /* 678 * report only if both card detect signals are the same 679 * not too nice done, 680 * we depend on that CD2 is the bit to the left of CD1... 681 */ 682 if(events & SS_DETECT) 683 if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ 684 (pipr & M8XX_PCMCIA_CD1(i))) 685 { 686 events &= ~SS_DETECT; 687 } 688 689#ifdef PCMCIA_GLITCHY_CD 690 /* 691 * I've experienced CD problems with my ADS board. 692 * We make an extra check to see if there was a 693 * real change of Card detection. 694 */ 695 696 if((events & SS_DETECT) && 697 ((pipr & 698 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && 699 (s->state.Vcc | s->state.Vpp)) { 700 events &= ~SS_DETECT; 701 } 702#endif 703 704 /* call the handler */ 705 706 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, " 707 "pipr = 0x%08x\n", 708 i, events, pscr, pipr); 709 710 if(events) { 711 spin_lock(&pending_event_lock); 712 pending_events[i] |= events; 713 spin_unlock(&pending_event_lock); 714 /* 715 * Turn off RDY_L bits in the PER mask on 716 * CD interrupt receival. 717 * 718 * They can generate bad interrupts on the 719 * ACS4,8,16,32. - marcelo 720 */ 721 per &= ~M8XX_PCMCIA_RDY_L(0); 722 per &= ~M8XX_PCMCIA_RDY_L(1); 723 724 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per); 725 726 if (events) 727 pcmcia_parse_events(&socket[i].socket, events); 728 } 729 } 730 731 /* clear the interrupt sources */ 732 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr); 733 734 dprintk("Interrupt done.\n"); 735 736 return IRQ_HANDLED; 737} 738 739static u32 m8xx_get_graycode(u32 size) 740{ 741 u32 k; 742 743 for(k = 0; k < M8XX_SIZES_NO; k++) 744 if(m8xx_size_to_gray[k] == size) 745 break; 746 747 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) 748 k = -1; 749 750 return k; 751} 752 753static u32 m8xx_get_speed(u32 ns, u32 is_io) 754{ 755 u32 reg, clocks, psst, psl, psht; 756 757 if(!ns) { 758 759 /* 760 * We get called with IO maps setup to 0ns 761 * if not specified by the user. 762 * They should be 255ns. 763 */ 764 765 if(is_io) 766 ns = 255; 767 else 768 ns = 100; /* fast memory if 0 */ 769 } 770 771 /* 772 * In PSST, PSL, PSHT fields we tell the controller 773 * timing parameters in CLKOUT clock cycles. 774 * CLKOUT is the same as GCLK2_50. 775 */ 776 777/* how we want to adjust the timing - in percent */ 778 779#define ADJ 180 /* 80 % longer accesstime - to be sure */ 780 781 clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; 782 clocks = (clocks * ADJ) / (100*1000); 783 if(clocks >= PCMCIA_BMT_LIMIT) { 784 printk( "Max access time limit reached\n"); 785 clocks = PCMCIA_BMT_LIMIT-1; 786 } 787 788 psst = clocks / 7; /* setup time */ 789 psht = clocks / 7; /* hold time */ 790 psl = (clocks * 5) / 7; /* strobe length */ 791 792 psst += clocks - (psst + psht + psl); 793 794 reg = psst << 12; 795 reg |= psl << 7; 796 reg |= psht << 16; 797 798 return reg; 799} 800 801static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) 802{ 803 int lsock = container_of(sock, struct socket_info, socket)->slot; 804 struct socket_info *s = &socket[lsock]; 805 unsigned int pipr, reg; 806 807 pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr); 808 809 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) 810 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; 811 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; 812 813 if (s->state.flags & SS_IOCARD) 814 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; 815 else { 816 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; 817 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; 818 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; 819 } 820 821 if (s->state.Vcc | s->state.Vpp) 822 *value |= SS_POWERON; 823 824 /* 825 * Voltage detection: 826 * This driver only supports 16-Bit pc-cards. 827 * Cardbus is not handled here. 828 * 829 * To determine what voltage to use we must read the VS1 and VS2 pin. 830 * Depending on what socket type is present, 831 * different combinations mean different things. 832 * 833 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse 834 * 835 * 5V 5V, LV* NC NC 5V only 5V (if available) 836 * 837 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible 838 * 839 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible 840 * 841 * LV* 5V - - shall not fit into socket 842 * 843 * LV* LV* GND NC 3.3V only 3.3V 844 * 845 * LV* LV* NC GND x.xV x.xV (if avail.) 846 * 847 * LV* LV* GND GND 3.3 or x.xV as low as possible 848 * 849 * *LV means Low Voltage 850 * 851 * 852 * That gives us the following table: 853 * 854 * Socket VS1 VS2 Voltage 855 * 856 * 5V NC NC 5V 857 * 5V NC GND none (should not be possible) 858 * 5V GND NC >= 3.3V 859 * 5V GND GND >= x.xV 860 * 861 * LV NC NC 5V (if available) 862 * LV NC GND x.xV (if available) 863 * LV GND NC 3.3V 864 * LV GND GND >= x.xV 865 * 866 * So, how do I determine if I have a 5V or a LV 867 * socket on my board? Look at the socket! 868 * 869 * 870 * Socket with 5V key: 871 * ++--------------------------------------------+ 872 * || | 873 * || || 874 * || || 875 * | | 876 * +---------------------------------------------+ 877 * 878 * Socket with LV key: 879 * ++--------------------------------------------+ 880 * || | 881 * | || 882 * | || 883 * | | 884 * +---------------------------------------------+ 885 * 886 * 887 * With other words - LV only cards does not fit 888 * into the 5V socket! 889 */ 890 891 /* read out VS1 and VS2 */ 892 893 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) 894 >> M8XX_PCMCIA_VS_SHIFT(lsock); 895 896 if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { 897 switch(reg) { 898 case 1: 899 *value |= SS_3VCARD; 900 break; /* GND, NC - 3.3V only */ 901 case 2: 902 *value |= SS_XVCARD; 903 break; /* NC. GND - x.xV only */ 904 }; 905 } 906 907 dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value); 908 return 0; 909} 910 911static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state) 912{ 913 int lsock = container_of(sock, struct socket_info, socket)->slot; 914 struct socket_info *s = &socket[lsock]; 915 struct event_table *e; 916 unsigned int reg; 917 unsigned long flags; 918 919 dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " 920 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, 921 state->Vcc, state->Vpp, state->io_irq, state->csc_mask); 922 923 /* First, set voltage - bail out if invalid */ 924 if(voltage_set(lsock, state->Vcc, state->Vpp)) 925 return -EINVAL; 926 927 /* Take care of reset... */ 928 if(state->flags & SS_RESET) 929 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ 930 else 931 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); 932 933 /* ... and output enable. */ 934 935 /* The CxOE signal is connected to a 74541 on the ADS. 936 I guess most other boards used the ADS as a reference. 937 I tried to control the CxOE signal with SS_OUTPUT_ENA, 938 but the reset signal seems connected via the 541. 939 If the CxOE is left high are some signals tristated and 940 no pullups are present -> the cards act wierd. 941 So right now the buffers are enabled if the power is on. */ 942 943 if(state->Vcc || state->Vpp) 944 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ 945 else 946 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); 947 948 /* 949 * We'd better turn off interrupts before 950 * we mess with the events-table.. 951 */ 952 953 spin_lock_irqsave(&events_lock, flags); 954 955 /* 956 * Play around with the interrupt mask to be able to 957 * give the events the generic pcmcia driver wants us to. 958 */ 959 960 e = &s->events[0]; 961 reg = 0; 962 963 if(state->csc_mask & SS_DETECT) { 964 e->eventbit = SS_DETECT; 965 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) 966 | M8XX_PCMCIA_CD1(lsock)); 967 e++; 968 } 969 if(state->flags & SS_IOCARD) { 970 /* 971 * I/O card 972 */ 973 if(state->csc_mask & SS_STSCHG) { 974 e->eventbit = SS_STSCHG; 975 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); 976 e++; 977 } 978 /* 979 * If io_irq is non-zero we should enable irq. 980 */ 981 if(state->io_irq) { 982 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24); 983 /* 984 * Strange thing here: 985 * The manual does not tell us which interrupt 986 * the sources generate. 987 * Anyhow, I found out that RDY_L generates IREQLVL. 988 * 989 * We use level triggerd interrupts, and they don't 990 * have to be cleared in PSCR in the interrupt handler. 991 */ 992 reg |= M8XX_PCMCIA_RDY_L(lsock); 993 } 994 else 995 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); 996 } 997 else { 998 /* 999 * Memory card 1000 */ 1001 if(state->csc_mask & SS_BATDEAD) { 1002 e->eventbit = SS_BATDEAD; 1003 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); 1004 e++; 1005 } 1006 if(state->csc_mask & SS_BATWARN) { 1007 e->eventbit = SS_BATWARN; 1008 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); 1009 e++; 1010 } 1011 /* What should I trigger on - low/high,raise,fall? */ 1012 if(state->csc_mask & SS_READY) { 1013 e->eventbit = SS_READY; 1014 reg |= e->regbit = 0; //?? 1015 e++; 1016 } 1017 } 1018 1019 e->regbit = 0; /* terminate list */ 1020 1021 /* 1022 * Clear the status changed . 1023 * Port A and Port B share the same port. 1024 * Writing ones will clear the bits. 1025 */ 1026 1027 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg); 1028 1029 /* 1030 * Write the mask. 1031 * Port A and Port B share the same port. 1032 * Need for read-modify-write. 1033 * Ones will enable the interrupt. 1034 */ 1035 1036 /* 1037 reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per 1038 & M8XX_PCMCIA_MASK(lsock); 1039 */ 1040 1041 reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & 1042 (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); 1043 1044 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg); 1045 1046 spin_unlock_irqrestore(&events_lock, flags); 1047 1048 /* copy the struct and modify the copy */ 1049 1050 s->state = *state; 1051 1052 return 0; 1053} 1054 1055static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) 1056{ 1057 int lsock = container_of(sock, struct socket_info, socket)->slot; 1058 1059 struct socket_info *s = &socket[lsock]; 1060 struct pcmcia_win *w; 1061 unsigned int reg, winnr; 1062 1063#define M8XX_SIZE (io->stop - io->start + 1) 1064#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) 1065 1066 dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, " 1067 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags, 1068 io->speed, io->start, io->stop); 1069 1070 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) 1071 || (io->stop > 0xffff) || (io->stop < io->start)) 1072 return -EINVAL; 1073 1074 if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) 1075 return -EINVAL; 1076 1077 if(io->flags & MAP_ACTIVE) { 1078 1079 dprintk( "io->flags & MAP_ACTIVE\n"); 1080 1081 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) 1082 + (lsock * PCMCIA_IO_WIN_NO) + io->map; 1083 1084 /* setup registers */ 1085 1086 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; 1087 w += winnr; 1088 1089 out_be32(&w->or, 0); /* turn off window first */ 1090 out_be32(&w->br, M8XX_BASE); 1091 1092 reg <<= 27; 1093 reg |= M8XX_PCMCIA_POR_IO |(lsock << 2); 1094 1095 reg |= m8xx_get_speed(io->speed, 1); 1096 1097 if(io->flags & MAP_WRPROT) 1098 reg |= M8XX_PCMCIA_POR_WRPROT; 1099 1100 if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) 1101 reg |= M8XX_PCMCIA_POR_16BIT; 1102 1103 if(io->flags & MAP_ACTIVE) 1104 reg |= M8XX_PCMCIA_POR_VALID; 1105 1106 out_be32(&w->or, reg); 1107 1108 dprintk("Socket %u: Mapped io window %u at %#8.8x, " 1109 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); 1110 } else { 1111 /* shutdown IO window */ 1112 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) 1113 + (lsock * PCMCIA_IO_WIN_NO) + io->map; 1114 1115 /* setup registers */ 1116 1117 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; 1118 w += winnr; 1119 1120 out_be32(&w->or, 0); /* turn off window */ 1121 out_be32(&w->br, 0); /* turn off base address */ 1122 1123 dprintk("Socket %u: Unmapped io window %u at %#8.8x, " 1124 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); 1125 } 1126 1127 /* copy the struct and modify the copy */ 1128 s->io_win[io->map] = *io; 1129 s->io_win[io->map].flags &= (MAP_WRPROT 1130 | MAP_16BIT 1131 | MAP_ACTIVE); 1132 dprintk("SetIOMap exit\n"); 1133 1134 return 0; 1135} 1136 1137static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem) 1138{ 1139 int lsock = container_of(sock, struct socket_info, socket)->slot; 1140 struct socket_info *s = &socket[lsock]; 1141 struct pcmcia_win *w; 1142 struct pccard_mem_map *old; 1143 unsigned int reg, winnr; 1144 1145 dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, " 1146 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, 1147 mem->speed, mem->static_start, mem->card_start); 1148 1149 if ((mem->map >= PCMCIA_MEM_WIN_NO) 1150// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) 1151 || (mem->card_start >= 0x04000000) 1152 || (mem->static_start & 0xfff) /* 4KByte resolution */ 1153 || (mem->card_start & 0xfff)) 1154 return -EINVAL; 1155 1156 if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { 1157 printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); 1158 return -EINVAL; 1159 } 1160 reg <<= 27; 1161 1162 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; 1163 1164 /* Setup the window in the pcmcia controller */ 1165 1166 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; 1167 w += winnr; 1168 1169 reg |= lsock << 2; 1170 1171 reg |= m8xx_get_speed(mem->speed, 0); 1172 1173 if(mem->flags & MAP_ATTRIB) 1174 reg |= M8XX_PCMCIA_POR_ATTRMEM; 1175 1176 if(mem->flags & MAP_WRPROT) 1177 reg |= M8XX_PCMCIA_POR_WRPROT; 1178 1179 if(mem->flags & MAP_16BIT) 1180 reg |= M8XX_PCMCIA_POR_16BIT; 1181 1182 if(mem->flags & MAP_ACTIVE) 1183 reg |= M8XX_PCMCIA_POR_VALID; 1184 1185 out_be32(&w->or, reg); 1186 1187 dprintk("Socket %u: Mapped memory window %u at %#8.8x, " 1188 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); 1189 1190 if(mem->flags & MAP_ACTIVE) { 1191 /* get the new base address */ 1192 mem->static_start = PCMCIA_MEM_WIN_BASE + 1193 (PCMCIA_MEM_WIN_SIZE * winnr) 1194 + mem->card_start; 1195 } 1196 1197 dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, " 1198 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, 1199 mem->speed, mem->static_start, mem->card_start); 1200 1201 /* copy the struct and modify the copy */ 1202 1203 old = &s->mem_win[mem->map]; 1204 1205 *old = *mem; 1206 old->flags &= (MAP_ATTRIB 1207 | MAP_WRPROT 1208 | MAP_16BIT 1209 | MAP_ACTIVE); 1210 1211 return 0; 1212} 1213 1214static int m8xx_sock_init(struct pcmcia_socket *sock) 1215{ 1216 int i; 1217 pccard_io_map io = { 0, 0, 0, 0, 1 }; 1218 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; 1219 1220 dprintk( "sock_init(%d)\n", s); 1221 1222 m8xx_set_socket(sock, &dead_socket); 1223 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { 1224 io.map = i; 1225 m8xx_set_io_map(sock, &io); 1226 } 1227 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { 1228 mem.map = i; 1229 m8xx_set_mem_map(sock, &mem); 1230 } 1231 1232 return 0; 1233 1234} 1235 1236static int m8xx_suspend(struct pcmcia_socket *sock) 1237{ 1238 return m8xx_set_socket(sock, &dead_socket); 1239} 1240 1241static struct pccard_operations m8xx_services = { 1242 .init = m8xx_sock_init, 1243 .suspend = m8xx_suspend, 1244 .get_status = m8xx_get_status, 1245 .set_socket = m8xx_set_socket, 1246 .set_io_map = m8xx_set_io_map, 1247 .set_mem_map = m8xx_set_mem_map, 1248}; 1249 1250static int __init m8xx_init(void) 1251{ 1252 struct pcmcia_win *w; 1253 unsigned int i,m; 1254 1255 pcmcia_info("%s\n", version); 1256 1257 if (driver_register(&m8xx_driver)) 1258 return -1; 1259 1260 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG 1261 " with IRQ %u.\n", pcmcia_schlvl); 1262 1263 /* Configure Status change interrupt */ 1264 1265 if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0, 1266 "m8xx_pcmcia", NULL)) { 1267 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", 1268 pcmcia_schlvl); 1269 return -1; 1270 } 1271 1272 w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; 1273 1274 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, 1275 M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)); 1276 1277 out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, 1278 in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & 1279 ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1))); 1280 1281/* connect interrupt and disable CxOE */ 1282 1283 out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16)); 1284 out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16)); 1285 1286/* intialize the fixed memory windows */ 1287 1288 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){ 1289 for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) { 1290 out_be32(&w->br, PCMCIA_MEM_WIN_BASE + 1291 (PCMCIA_MEM_WIN_SIZE 1292 * (m + i * PCMCIA_MEM_WIN_NO))); 1293 1294 out_be32(&w->or, 0); /* set to not valid */ 1295 1296 w++; 1297 } 1298 } 1299 1300/* turn off voltage */ 1301 voltage_set(0, 0, 0); 1302 voltage_set(1, 0, 0); 1303 1304/* Enable external hardware */ 1305 hardware_enable(0); 1306 hardware_enable(1); 1307 1308 platform_device_register(&m8xx_device); 1309 1310 for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) { 1311 socket[i].slot = i; 1312 socket[i].socket.owner = THIS_MODULE; 1313 socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; 1314 socket[i].socket.irq_mask = 0x000; 1315 socket[i].socket.map_size = 0x1000; 1316 socket[i].socket.io_offset = 0; 1317 socket[i].socket.pci_irq = i ? 7 : 9; 1318 socket[i].socket.ops = &m8xx_services; 1319 socket[i].socket.resource_ops = &pccard_iodyn_ops; 1320 socket[i].socket.cb_dev = NULL; 1321 socket[i].socket.dev.parent = &m8xx_device.dev; 1322 } 1323 1324 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) 1325 pcmcia_register_socket(&socket[i].socket); 1326 1327 return 0; 1328} 1329 1330static void __exit m8xx_exit(void) 1331{ 1332 int i; 1333 1334 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) 1335 pcmcia_unregister_socket(&socket[i].socket); 1336 1337 m8xx_shutdown(); 1338 1339 platform_device_unregister(&m8xx_device); 1340 driver_unregister(&m8xx_driver); 1341} 1342 1343module_init(m8xx_init); 1344module_exit(m8xx_exit); 1345