1/* 2 * drivers/pcmcia/m32r_cfc.c 3 * 4 * Device driver for the CFC functionality of M32R. 5 * 6 * Copyright (c) 2001, 2002, 2003, 2004 7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara 8 */ 9 10#include <linux/module.h> 11#include <linux/moduleparam.h> 12#include <linux/init.h> 13#include <linux/types.h> 14#include <linux/fcntl.h> 15#include <linux/string.h> 16#include <linux/kernel.h> 17#include <linux/errno.h> 18#include <linux/timer.h> 19#include <linux/slab.h> 20#include <linux/ioport.h> 21#include <linux/delay.h> 22#include <linux/workqueue.h> 23#include <linux/interrupt.h> 24#include <linux/platform_device.h> 25#include <linux/bitops.h> 26#include <asm/irq.h> 27#include <asm/io.h> 28#include <asm/system.h> 29 30#include <pcmcia/cs_types.h> 31#include <pcmcia/ss.h> 32#include <pcmcia/cs.h> 33 34#undef MAX_IO_WIN 35#define MAX_IO_WIN 1 36#undef MAX_WIN 37#define MAX_WIN 1 38 39#include "m32r_cfc.h" 40 41#ifdef DEBUG 42static int m32r_cfc_debug; 43module_param(m32r_cfc_debug, int, 0644); 44#define debug(lvl, fmt, arg...) do { \ 45 if (m32r_cfc_debug > (lvl)) \ 46 printk(KERN_DEBUG "m32r_cfc: " fmt , ## arg); \ 47} while (0) 48#else 49#define debug(n, args...) do { } while (0) 50#endif 51 52/* Poll status interval -- 0 means default to interrupt */ 53static int poll_interval = 0; 54 55typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t; 56 57typedef struct pcc_socket { 58 u_short type, flags; 59 struct pcmcia_socket socket; 60 unsigned int number; 61 kio_addr_t ioaddr; 62 u_long mapaddr; 63 u_long base; /* PCC register base */ 64 u_char cs_irq1, cs_irq2, intr; 65 pccard_io_map io_map[MAX_IO_WIN]; 66 pccard_mem_map mem_map[MAX_WIN]; 67 u_char io_win; 68 u_char mem_win; 69 pcc_as_t current_space; 70 u_char last_iodbex; 71#ifdef CONFIG_PROC_FS 72 struct proc_dir_entry *proc; 73#endif 74} pcc_socket_t; 75 76static int pcc_sockets = 0; 77static pcc_socket_t socket[M32R_MAX_PCC] = { 78 { 0, }, /* ... */ 79}; 80 81/*====================================================================*/ 82 83static unsigned int pcc_get(u_short, unsigned int); 84static void pcc_set(u_short, unsigned int , unsigned int ); 85 86static DEFINE_SPINLOCK(pcc_lock); 87 88#if !defined(CONFIG_PLAT_USRV) 89static inline u_long pcc_port2addr(unsigned long port, int size) { 90 u_long addr = 0; 91 u_long odd; 92 93 if (size == 1) { /* byte access */ 94 odd = (port&1) << 11; 95 port -= port & 1; 96 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port; 97 } else if (size == 2) 98 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port; 99 100 return addr; 101} 102#else /* CONFIG_PLAT_USRV */ 103static inline u_long pcc_port2addr(unsigned long port, int size) { 104 u_long odd; 105 u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8; 106 107 if (size == 1) { /* byte access */ 108 odd = port & 1; 109 port -= odd; 110 odd <<= 11; 111 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff); 112 } else if (size == 2) /* word access */ 113 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff); 114 115 return addr; 116} 117#endif /* CONFIG_PLAT_USRV */ 118 119void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size, 120 size_t nmemb, int flag) 121{ 122 u_long addr; 123 unsigned char *bp = (unsigned char *)buf; 124 unsigned long flags; 125 126 debug(3, "m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, " 127 "size=%u, nmemb=%d, flag=%d\n", 128 sock, port, buf, size, nmemb, flag); 129 130 addr = pcc_port2addr(port, 1); 131 if (!addr) { 132 printk("m32r_cfc:ioread_byte null port :%#lx\n",port); 133 return; 134 } 135 debug(3, "m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr); 136 137 spin_lock_irqsave(&pcc_lock, flags); 138 /* read Byte */ 139 while (nmemb--) 140 *bp++ = readb(addr); 141 spin_unlock_irqrestore(&pcc_lock, flags); 142} 143 144void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size, 145 size_t nmemb, int flag) 146{ 147 u_long addr; 148 unsigned short *bp = (unsigned short *)buf; 149 unsigned long flags; 150 151 debug(3, "m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, " 152 "buf=%p, size=%u, nmemb=%d, flag=%d\n", 153 sock, port, buf, size, nmemb, flag); 154 155 if (size != 2) 156 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size, 157 port); 158 if (size == 9) 159 printk("m32r_cfc: ioread_word :insw \n"); 160 161 addr = pcc_port2addr(port, 2); 162 if (!addr) { 163 printk("m32r_cfc:ioread_word null port :%#lx\n",port); 164 return; 165 } 166 debug(3, "m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr); 167 168 spin_lock_irqsave(&pcc_lock, flags); 169 /* read Word */ 170 while (nmemb--) 171 *bp++ = readw(addr); 172 spin_unlock_irqrestore(&pcc_lock, flags); 173} 174 175void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size, 176 size_t nmemb, int flag) 177{ 178 u_long addr; 179 unsigned char *bp = (unsigned char *)buf; 180 unsigned long flags; 181 182 debug(3, "m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, " 183 "buf=%p, size=%u, nmemb=%d, flag=%d\n", 184 sock, port, buf, size, nmemb, flag); 185 186 /* write Byte */ 187 addr = pcc_port2addr(port, 1); 188 if (!addr) { 189 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port); 190 return; 191 } 192 debug(3, "m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr); 193 194 spin_lock_irqsave(&pcc_lock, flags); 195 while (nmemb--) 196 writeb(*bp++, addr); 197 spin_unlock_irqrestore(&pcc_lock, flags); 198} 199 200void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size, 201 size_t nmemb, int flag) 202{ 203 u_long addr; 204 unsigned short *bp = (unsigned short *)buf; 205 unsigned long flags; 206 207 debug(3, "m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, " 208 "buf=%p, size=%u, nmemb=%d, flag=%d\n", 209 sock, port, buf, size, nmemb, flag); 210 211 if(size != 2) 212 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n", 213 size, port); 214 if(size == 9) 215 printk("m32r_cfc: iowrite_word :outsw \n"); 216 217 addr = pcc_port2addr(port, 2); 218 if (!addr) { 219 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port); 220 return; 221 } 222 if (addr & 1) { 223 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port, 224 addr); 225 return; 226 } 227 debug(3, "m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr); 228 229 spin_lock_irqsave(&pcc_lock, flags); 230 while (nmemb--) 231 writew(*bp++, addr); 232 spin_unlock_irqrestore(&pcc_lock, flags); 233} 234 235/*====================================================================*/ 236 237#define IS_REGISTERED 0x2000 238#define IS_ALIVE 0x8000 239 240typedef struct pcc_t { 241 char *name; 242 u_short flags; 243} pcc_t; 244 245static pcc_t pcc[] = { 246#if !defined(CONFIG_PLAT_USRV) 247 { "m32r_cfc", 0 }, { "", 0 }, 248#else /* CONFIG_PLAT_USRV */ 249 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, 250 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 }, 251#endif /* CONFIG_PLAT_USRV */ 252}; 253 254static irqreturn_t pcc_interrupt(int, void *); 255 256/*====================================================================*/ 257 258static struct timer_list poll_timer; 259 260static unsigned int pcc_get(u_short sock, unsigned int reg) 261{ 262 unsigned int val = inw(reg); 263 debug(3, "m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val); 264 return val; 265} 266 267 268static void pcc_set(u_short sock, unsigned int reg, unsigned int data) 269{ 270 outw(data, reg); 271 debug(3, "m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data); 272} 273 274/*====================================================================== 275 276 See if a card is present, powered up, in IO mode, and already 277 bound to a (non PC Card) Linux driver. We leave these alone. 278 279 We make an exception for cards that seem to be serial devices. 280 281======================================================================*/ 282 283static int __init is_alive(u_short sock) 284{ 285 unsigned int stat; 286 287 debug(3, "m32r_cfc: is_alive:\n"); 288 289 printk("CF: "); 290 stat = pcc_get(sock, (unsigned int)PLD_CFSTS); 291 if (!stat) 292 printk("No "); 293 printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat); 294 debug(3, "m32r_cfc: is_alive: sock stat is 0x%04x\n", stat); 295 296 return 0; 297} 298 299static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr) 300{ 301 pcc_socket_t *t = &socket[pcc_sockets]; 302 303 debug(3, "m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, " 304 "mapaddr=%#lx, ioaddr=%08x\n", 305 base, irq, mapaddr, ioaddr); 306 307 /* add sockets */ 308 t->ioaddr = ioaddr; 309 t->mapaddr = mapaddr; 310#if !defined(CONFIG_PLAT_USRV) 311 t->base = 0; 312 t->flags = 0; 313 t->cs_irq1 = irq; // insert irq 314 t->cs_irq2 = irq + 1; // eject irq 315#else /* CONFIG_PLAT_USRV */ 316 t->base = base; 317 t->flags = 0; 318 t->cs_irq1 = 0; // insert irq 319 t->cs_irq2 = 0; // eject irq 320#endif /* CONFIG_PLAT_USRV */ 321 322 if (is_alive(pcc_sockets)) 323 t->flags |= IS_ALIVE; 324 325 /* add pcc */ 326#if !defined(CONFIG_PLAT_USRV) 327 request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc"); 328#else /* CONFIG_PLAT_USRV */ 329 { 330 unsigned int reg_base; 331 332 reg_base = (unsigned int)PLD_CFRSTCR; 333 reg_base |= pcc_sockets << 8; 334 request_region(reg_base, 0x20, "m32r_cfc"); 335 } 336#endif /* CONFIG_PLAT_USRV */ 337 printk(KERN_INFO " %s ", pcc[pcc_sockets].name); 338 printk("pcc at 0x%08lx\n", t->base); 339 340 /* Update socket interrupt information, capabilities */ 341 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP); 342 t->socket.map_size = M32R_PCC_MAPSIZE; 343 t->socket.io_offset = ioaddr; /* use for io access offset */ 344 t->socket.irq_mask = 0; 345#if !defined(CONFIG_PLAT_USRV) 346 t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */ 347#else /* CONFIG_PLAT_USRV */ 348 t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets; 349#endif /* CONFIG_PLAT_USRV */ 350 351#ifndef CONFIG_PLAT_USRV 352 /* insert interrupt */ 353 request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt); 354#ifndef CONFIG_PLAT_MAPPI3 355 /* eject interrupt */ 356 request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt); 357#endif 358 debug(3, "m32r_cfc: enable CFMSK, RDYSEL\n"); 359 pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01); 360#endif /* CONFIG_PLAT_USRV */ 361#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || \ 362 defined(CONFIG_PLAT_OPSPUT) 363 pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200); 364#endif 365 pcc_sockets++; 366 367 return; 368} 369 370 371/*====================================================================*/ 372 373static irqreturn_t pcc_interrupt(int irq, void *dev) 374{ 375 int i; 376 u_int events = 0; 377 int handled = 0; 378 379 debug(3, "m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev); 380 for (i = 0; i < pcc_sockets; i++) { 381 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq) 382 continue; 383 384 handled = 1; 385 debug(3, "m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ", 386 i, irq); 387 events |= SS_DETECT; /* insert or eject */ 388 if (events) 389 pcmcia_parse_events(&socket[i].socket, events); 390 } 391 debug(3, "m32r_cfc: pcc_interrupt: done\n"); 392 393 return IRQ_RETVAL(handled); 394} /* pcc_interrupt */ 395 396static void pcc_interrupt_wrapper(u_long data) 397{ 398 debug(3, "m32r_cfc: pcc_interrupt_wrapper:\n"); 399 pcc_interrupt(0, NULL); 400 init_timer(&poll_timer); 401 poll_timer.expires = jiffies + poll_interval; 402 add_timer(&poll_timer); 403} 404 405/*====================================================================*/ 406 407static int _pcc_get_status(u_short sock, u_int *value) 408{ 409 u_int status; 410 411 debug(3, "m32r_cfc: _pcc_get_status:\n"); 412 status = pcc_get(sock, (unsigned int)PLD_CFSTS); 413 *value = (status) ? SS_DETECT : 0; 414 debug(3, "m32r_cfc: _pcc_get_status: status=0x%08x\n", status); 415 416#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || \ 417 defined(CONFIG_PLAT_OPSPUT) 418 if ( status ) { 419 /* enable CF power */ 420 status = inw((unsigned int)PLD_CPCR); 421 if (!(status & PLD_CPCR_CF)) { 422 debug(3, "m32r_cfc: _pcc_get_status: " 423 "power on (CPCR=0x%08x)\n", status); 424 status |= PLD_CPCR_CF; 425 outw(status, (unsigned int)PLD_CPCR); 426 udelay(100); 427 } 428 *value |= SS_POWERON; 429 430 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */ 431 udelay(100); 432 433 *value |= SS_READY; /* always ready */ 434 *value |= SS_3VCARD; 435 } else { 436 /* disable CF power */ 437 status = inw((unsigned int)PLD_CPCR); 438 status &= ~PLD_CPCR_CF; 439 outw(status, (unsigned int)PLD_CPCR); 440 udelay(100); 441 debug(3, "m32r_cfc: _pcc_get_status: " 442 "power off (CPCR=0x%08x)\n", status); 443 } 444#elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) 445 if ( status ) { 446 status = pcc_get(sock, (unsigned int)PLD_CPCR); 447 if (status == 0) { /* power off */ 448 pcc_set(sock, (unsigned int)PLD_CPCR, 1); 449 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */ 450 udelay(50); 451 } 452 *value |= SS_POWERON; 453 454 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); 455 udelay(50); 456 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101); 457 udelay(25); /* for IDE reset */ 458 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100); 459 mdelay(2); /* for IDE reset */ 460 461 *value |= SS_READY; 462 *value |= SS_3VCARD; 463 } else { 464 /* disable CF power */ 465 pcc_set(sock, (unsigned int)PLD_CPCR, 0); 466 udelay(100); 467 debug(3, "m32r_cfc: _pcc_get_status: " 468 "power off (CPCR=0x%08x)\n", status); 469 } 470#else 471#error no platform configuration 472#endif 473 debug(3, "m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n", 474 sock, *value); 475 return 0; 476} /* _get_status */ 477 478/*====================================================================*/ 479 480static int _pcc_set_socket(u_short sock, socket_state_t *state) 481{ 482 debug(3, "m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " 483 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags, 484 state->Vcc, state->Vpp, state->io_irq, state->csc_mask); 485 486#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || \ 487 defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || \ 488 defined(CONFIG_PLAT_MAPPI3) 489 if (state->Vcc) { 490 if ((state->Vcc != 50) && (state->Vcc != 33)) 491 return -EINVAL; 492 /* accept 5V and 3.3V */ 493 } 494#endif 495 if (state->flags & SS_RESET) { 496 debug(3, ":RESET\n"); 497 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101); 498 }else{ 499 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100); 500 } 501 if (state->flags & SS_OUTPUT_ENA){ 502 debug(3, ":OUTPUT_ENA\n"); 503 /* bit clear */ 504 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0); 505 } else { 506 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1); 507 } 508 509#ifdef DEBUG 510 if(state->flags & SS_IOCARD){ 511 debug(3, ":IOCARD"); 512 } 513 if (state->flags & SS_PWR_AUTO) { 514 debug(3, ":PWR_AUTO"); 515 } 516 if (state->csc_mask & SS_DETECT) 517 debug(3, ":csc-SS_DETECT"); 518 if (state->flags & SS_IOCARD) { 519 if (state->csc_mask & SS_STSCHG) 520 debug(3, ":STSCHG"); 521 } else { 522 if (state->csc_mask & SS_BATDEAD) 523 debug(3, ":BATDEAD"); 524 if (state->csc_mask & SS_BATWARN) 525 debug(3, ":BATWARN"); 526 if (state->csc_mask & SS_READY) 527 debug(3, ":READY"); 528 } 529 debug(3, "\n"); 530#endif 531 return 0; 532} /* _set_socket */ 533 534/*====================================================================*/ 535 536static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io) 537{ 538 u_char map; 539 540 debug(3, "m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, " 541 "%#lx-%#lx)\n", sock, io->map, io->flags, 542 io->speed, io->start, io->stop); 543 map = io->map; 544 545 return 0; 546} /* _set_io_map */ 547 548/*====================================================================*/ 549 550static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem) 551{ 552 553 u_char map = mem->map; 554 u_long addr; 555 pcc_socket_t *t = &socket[sock]; 556 557 debug(3, "m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, " 558 "%#lx, %#x)\n", sock, map, mem->flags, 559 mem->speed, mem->static_start, mem->card_start); 560 561 /* 562 * sanity check 563 */ 564 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){ 565 return -EINVAL; 566 } 567 568 /* 569 * de-activate 570 */ 571 if ((mem->flags & MAP_ACTIVE) == 0) { 572 t->current_space = as_none; 573 return 0; 574 } 575 576 /* 577 * Set mode 578 */ 579 if (mem->flags & MAP_ATTRIB) { 580 t->current_space = as_attr; 581 } else { 582 t->current_space = as_comm; 583 } 584 585 /* 586 * Set address 587 */ 588 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK); 589 mem->static_start = addr + mem->card_start; 590 591 return 0; 592 593} /* _set_mem_map */ 594 595 596/*====================================================================*/ 597 598/* this is horribly ugly... proper locking needs to be done here at 599 * some time... */ 600#define LOCKED(x) do { \ 601 int retval; \ 602 unsigned long flags; \ 603 spin_lock_irqsave(&pcc_lock, flags); \ 604 retval = x; \ 605 spin_unlock_irqrestore(&pcc_lock, flags); \ 606 return retval; \ 607} while (0) 608 609 610static int pcc_get_status(struct pcmcia_socket *s, u_int *value) 611{ 612 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 613 614 if (socket[sock].flags & IS_ALIVE) { 615 debug(3, "m32r_cfc: pcc_get_status: sock(%d) -EINVAL\n", sock); 616 *value = 0; 617 return -EINVAL; 618 } 619 debug(3, "m32r_cfc: pcc_get_status: sock(%d)\n", sock); 620 LOCKED(_pcc_get_status(sock, value)); 621} 622 623static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state) 624{ 625 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 626 627 if (socket[sock].flags & IS_ALIVE) { 628 debug(3, "m32r_cfc: pcc_set_socket: sock(%d) -EINVAL\n", sock); 629 return -EINVAL; 630 } 631 debug(3, "m32r_cfc: pcc_set_socket: sock(%d)\n", sock); 632 LOCKED(_pcc_set_socket(sock, state)); 633} 634 635static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) 636{ 637 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 638 639 if (socket[sock].flags & IS_ALIVE) { 640 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d) -EINVAL\n", sock); 641 return -EINVAL; 642 } 643 debug(3, "m32r_cfc: pcc_set_io_map: sock(%d)\n", sock); 644 LOCKED(_pcc_set_io_map(sock, io)); 645} 646 647static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem) 648{ 649 unsigned int sock = container_of(s, struct pcc_socket, socket)->number; 650 651 if (socket[sock].flags & IS_ALIVE) { 652 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d) -EINVAL\n", sock); 653 return -EINVAL; 654 } 655 debug(3, "m32r_cfc: pcc_set_mem_map: sock(%d)\n", sock); 656 LOCKED(_pcc_set_mem_map(sock, mem)); 657} 658 659static int pcc_init(struct pcmcia_socket *s) 660{ 661 debug(3, "m32r_cfc: pcc_init()\n"); 662 return 0; 663} 664 665static struct pccard_operations pcc_operations = { 666 .init = pcc_init, 667 .get_status = pcc_get_status, 668 .set_socket = pcc_set_socket, 669 .set_io_map = pcc_set_io_map, 670 .set_mem_map = pcc_set_mem_map, 671}; 672 673/*====================================================================*/ 674 675static struct device_driver pcc_driver = { 676 .name = "cfc", 677 .bus = &platform_bus_type, 678 .suspend = pcmcia_socket_dev_suspend, 679 .resume = pcmcia_socket_dev_resume, 680}; 681 682static struct platform_device pcc_device = { 683 .name = "cfc", 684 .id = 0, 685}; 686 687/*====================================================================*/ 688 689static int __init init_m32r_pcc(void) 690{ 691 int i, ret; 692 693 ret = driver_register(&pcc_driver); 694 if (ret) 695 return ret; 696 697 ret = platform_device_register(&pcc_device); 698 if (ret){ 699 driver_unregister(&pcc_driver); 700 return ret; 701 } 702 703#if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3) 704 pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f); 705 pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200); 706#endif 707 708 pcc_sockets = 0; 709 710#if !defined(CONFIG_PLAT_USRV) 711 add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE, 712 CFC_IOPORT_BASE); 713#else /* CONFIG_PLAT_USRV */ 714 { 715 ulong base, mapaddr; 716 kio_addr_t ioaddr; 717 718 for (i = 0 ; i < M32R_MAX_PCC ; i++) { 719 base = (ulong)PLD_CFRSTCR; 720 base = base | (i << 8); 721 ioaddr = (i + 1) << 12; 722 mapaddr = CFC_ATTR_MAPBASE | (i << 20); 723 add_pcc_socket(base, 0, mapaddr, ioaddr); 724 } 725 } 726#endif /* CONFIG_PLAT_USRV */ 727 728 if (pcc_sockets == 0) { 729 printk("socket is not found.\n"); 730 platform_device_unregister(&pcc_device); 731 driver_unregister(&pcc_driver); 732 return -ENODEV; 733 } 734 735 /* Set up interrupt handler(s) */ 736 737 for (i = 0 ; i < pcc_sockets ; i++) { 738 socket[i].socket.dev.parent = &pcc_device.dev; 739 socket[i].socket.ops = &pcc_operations; 740 socket[i].socket.resource_ops = &pccard_nonstatic_ops; 741 socket[i].socket.owner = THIS_MODULE; 742 socket[i].number = i; 743 ret = pcmcia_register_socket(&socket[i].socket); 744 if (!ret) 745 socket[i].flags |= IS_REGISTERED; 746 747 } 748 749 /* Finally, schedule a polling interrupt */ 750 if (poll_interval != 0) { 751 poll_timer.function = pcc_interrupt_wrapper; 752 poll_timer.data = 0; 753 init_timer(&poll_timer); 754 poll_timer.expires = jiffies + poll_interval; 755 add_timer(&poll_timer); 756 } 757 758 return 0; 759} /* init_m32r_pcc */ 760 761static void __exit exit_m32r_pcc(void) 762{ 763 int i; 764 765 for (i = 0; i < pcc_sockets; i++) 766 if (socket[i].flags & IS_REGISTERED) 767 pcmcia_unregister_socket(&socket[i].socket); 768 769 platform_device_unregister(&pcc_device); 770 if (poll_interval != 0) 771 del_timer_sync(&poll_timer); 772 773 driver_unregister(&pcc_driver); 774} /* exit_m32r_pcc */ 775 776module_init(init_m32r_pcc); 777module_exit(exit_m32r_pcc); 778MODULE_LICENSE("Dual MPL/GPL"); 779/*====================================================================*/ 780