1/* 2** DINO manager 3** 4** (c) Copyright 1999 Red Hat Software 5** (c) Copyright 1999 SuSE GmbH 6** (c) Copyright 1999,2000 Hewlett-Packard Company 7** (c) Copyright 2000 Grant Grundler 8** (c) Copyright 2006 Helge Deller 9** 10** This program is free software; you can redistribute it and/or modify 11** it under the terms of the GNU General Public License as published by 12** the Free Software Foundation; either version 2 of the License, or 13** (at your option) any later version. 14** 15** This module provides access to Dino PCI bus (config/IOport spaces) 16** and helps manage Dino IRQ lines. 17** 18** Dino interrupt handling is a bit complicated. 19** Dino always writes to the broadcast EIR via irr0 for now. 20** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) 21** Only one processor interrupt is used for the 11 IRQ line 22** inputs to dino. 23** 24** The different between Built-in Dino and Card-Mode 25** dino is in chip initialization and pci device initialization. 26** 27** Linux drivers can only use Card-Mode Dino if pci devices I/O port 28** BARs are configured and used by the driver. Programming MMIO address 29** requires substantial knowledge of available Host I/O address ranges 30** is currently not supported. Port/Config accessor functions are the 31** same. "BIOS" differences are handled within the existing routines. 32*/ 33 34/* Changes : 35** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) 36** - added support for the integrated RS232. 37*/ 38 39/* 40** TODO: create a virtual address for each Dino HPA. 41** GSC code might be able to do this since IODC data tells us 42** how many pages are used. PCI subsystem could (must?) do this 43** for PCI drivers devices which implement/use MMIO registers. 44*/ 45 46#include <linux/delay.h> 47#include <linux/types.h> 48#include <linux/kernel.h> 49#include <linux/pci.h> 50#include <linux/init.h> 51#include <linux/ioport.h> 52#include <linux/slab.h> 53#include <linux/interrupt.h> /* for struct irqaction */ 54#include <linux/spinlock.h> /* for spinlock_t and prototypes */ 55 56#include <asm/pdc.h> 57#include <asm/page.h> 58#include <asm/system.h> 59#include <asm/io.h> 60#include <asm/hardware.h> 61 62#include "gsc.h" 63 64#undef DINO_DEBUG 65 66#ifdef DINO_DEBUG 67#define DBG(x...) printk(x) 68#else 69#define DBG(x...) 70#endif 71 72/* 73** Config accessor functions only pass in the 8-bit bus number 74** and not the 8-bit "PCI Segment" number. Each Dino will be 75** assigned a PCI bus number based on "when" it's discovered. 76** 77** The "secondary" bus number is set to this before calling 78** pci_scan_bus(). If any PPB's are present, the scan will 79** discover them and update the "secondary" and "subordinate" 80** fields in Dino's pci_bus structure. 81** 82** Changes in the configuration *will* result in a different 83** bus number for each dino. 84*/ 85 86#define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) 87#define is_cujo(id) ((id)->hversion == 0x682) 88 89#define DINO_IAR0 0x004 90#define DINO_IODC_ADDR 0x008 91#define DINO_IODC_DATA_0 0x008 92#define DINO_IODC_DATA_1 0x008 93#define DINO_IRR0 0x00C 94#define DINO_IAR1 0x010 95#define DINO_IRR1 0x014 96#define DINO_IMR 0x018 97#define DINO_IPR 0x01C 98#define DINO_TOC_ADDR 0x020 99#define DINO_ICR 0x024 100#define DINO_ILR 0x028 101#define DINO_IO_COMMAND 0x030 102#define DINO_IO_STATUS 0x034 103#define DINO_IO_CONTROL 0x038 104#define DINO_IO_GSC_ERR_RESP 0x040 105#define DINO_IO_ERR_INFO 0x044 106#define DINO_IO_PCI_ERR_RESP 0x048 107#define DINO_IO_FBB_EN 0x05c 108#define DINO_IO_ADDR_EN 0x060 109#define DINO_PCI_ADDR 0x064 110#define DINO_CONFIG_DATA 0x068 111#define DINO_IO_DATA 0x06c 112#define DINO_MEM_DATA 0x070 /* Dino 3.x only */ 113#define DINO_GSC2X_CONFIG 0x7b4 114#define DINO_GMASK 0x800 115#define DINO_PAMR 0x804 116#define DINO_PAPR 0x808 117#define DINO_DAMODE 0x80c 118#define DINO_PCICMD 0x810 119#define DINO_PCISTS 0x814 120#define DINO_MLTIM 0x81c 121#define DINO_BRDG_FEAT 0x820 122#define DINO_PCIROR 0x824 123#define DINO_PCIWOR 0x828 124#define DINO_TLTIM 0x830 125 126#define DINO_IRQS 11 /* bits 0-10 are architected */ 127#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 128#define DINO_LOCAL_IRQS (DINO_IRQS+1) 129 130#define DINO_MASK_IRQ(x) (1<<(x)) 131 132#define PCIINTA 0x001 133#define PCIINTB 0x002 134#define PCIINTC 0x004 135#define PCIINTD 0x008 136#define PCIINTE 0x010 137#define PCIINTF 0x020 138#define GSCEXTINT 0x040 139#define RS232INT 0x400 140 141struct dino_device 142{ 143 struct pci_hba_data hba; /* 'C' inheritance - must be first */ 144 spinlock_t dinosaur_pen; 145 unsigned long txn_addr; /* EIR addr to generate interrupt */ 146 u32 txn_data; /* EIR data assign to each dino */ 147 u32 imr; /* IRQ's which are enabled */ 148 int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */ 149#ifdef DINO_DEBUG 150 unsigned int dino_irr0; /* save most recent IRQ line stat */ 151#endif 152}; 153 154/* Looks nice and keeps the compiler happy */ 155#define DINO_DEV(d) ((struct dino_device *) d) 156 157 158/* 159 * Dino Configuration Space Accessor Functions 160 */ 161 162#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) 163 164/* 165 * keep the current highest bus count to assist in allocating busses. This 166 * tries to keep a global bus count total so that when we discover an 167 * entirely new bus, it can be given a unique bus number. 168 */ 169static int dino_current_bus = 0; 170 171static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, 172 int size, u32 *val) 173{ 174 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 175 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 176 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 177 void __iomem *base_addr = d->hba.base_addr; 178 unsigned long flags; 179 180 DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where, 181 size); 182 spin_lock_irqsave(&d->dinosaur_pen, flags); 183 184 /* tell HW which CFG address */ 185 __raw_writel(v, base_addr + DINO_PCI_ADDR); 186 187 /* generate cfg read cycle */ 188 if (size == 1) { 189 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); 190 } else if (size == 2) { 191 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); 192 } else if (size == 4) { 193 *val = readl(base_addr + DINO_CONFIG_DATA); 194 } 195 196 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 197 return 0; 198} 199 200/* 201 * Dino address stepping "feature": 202 * When address stepping, Dino attempts to drive the bus one cycle too soon 203 * even though the type of cycle (config vs. MMIO) might be different. 204 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. 205 */ 206static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, 207 int size, u32 val) 208{ 209 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 210 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 211 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 212 void __iomem *base_addr = d->hba.base_addr; 213 unsigned long flags; 214 215 DBG("%s: %p, %d, %d, %d\n", __FUNCTION__, base_addr, devfn, where, 216 size); 217 spin_lock_irqsave(&d->dinosaur_pen, flags); 218 219 /* avoid address stepping feature */ 220 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); 221 __raw_readl(base_addr + DINO_CONFIG_DATA); 222 223 /* tell HW which CFG address */ 224 __raw_writel(v, base_addr + DINO_PCI_ADDR); 225 /* generate cfg read cycle */ 226 if (size == 1) { 227 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); 228 } else if (size == 2) { 229 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); 230 } else if (size == 4) { 231 writel(val, base_addr + DINO_CONFIG_DATA); 232 } 233 234 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 235 return 0; 236} 237 238static struct pci_ops dino_cfg_ops = { 239 .read = dino_cfg_read, 240 .write = dino_cfg_write, 241}; 242 243 244/* 245 * Dino "I/O Port" Space Accessor Functions 246 * 247 * Many PCI devices don't require use of I/O port space (eg Tulip, 248 * NCR720) since they export the same registers to both MMIO and 249 * I/O port space. Performance is going to stink if drivers use 250 * I/O port instead of MMIO. 251 */ 252 253#define DINO_PORT_IN(type, size, mask) \ 254static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ 255{ \ 256 u##size v; \ 257 unsigned long flags; \ 258 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 259 /* tell HW which IO Port address */ \ 260 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 261 /* generate I/O PORT read cycle */ \ 262 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ 263 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 264 return v; \ 265} 266 267DINO_PORT_IN(b, 8, 3) 268DINO_PORT_IN(w, 16, 2) 269DINO_PORT_IN(l, 32, 0) 270 271#define DINO_PORT_OUT(type, size, mask) \ 272static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 273{ \ 274 unsigned long flags; \ 275 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 276 /* tell HW which IO port address */ \ 277 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 278 /* generate cfg write cycle */ \ 279 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ 280 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 281} 282 283DINO_PORT_OUT(b, 8, 3) 284DINO_PORT_OUT(w, 16, 2) 285DINO_PORT_OUT(l, 32, 0) 286 287struct pci_port_ops dino_port_ops = { 288 .inb = dino_in8, 289 .inw = dino_in16, 290 .inl = dino_in32, 291 .outb = dino_out8, 292 .outw = dino_out16, 293 .outl = dino_out32 294}; 295 296static void dino_disable_irq(unsigned int irq) 297{ 298 struct dino_device *dino_dev = irq_desc[irq].chip_data; 299 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 300 301 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq); 302 303 /* Clear the matching bit in the IMR register */ 304 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); 305 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 306} 307 308static void dino_enable_irq(unsigned int irq) 309{ 310 struct dino_device *dino_dev = irq_desc[irq].chip_data; 311 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, DINO_LOCAL_IRQS); 312 u32 tmp; 313 314 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, dino_dev, irq); 315 316 /* 317 ** clear pending IRQ bits 318 ** 319 ** This does NOT change ILR state! 320 ** See comment below for ILR usage. 321 */ 322 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); 323 324 /* set the matching bit in the IMR register */ 325 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ 326 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 327 328 /* Emulate "Level Triggered" Interrupt 329 ** Basically, a driver is blowing it if the IRQ line is asserted 330 ** while the IRQ is disabled. But tulip.c seems to do that.... 331 ** Give 'em a kluge award and a nice round of applause! 332 ** 333 ** The gsc_write will generate an interrupt which invokes dino_isr(). 334 ** dino_isr() will read IPR and find nothing. But then catch this 335 ** when it also checks ILR. 336 */ 337 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); 338 if (tmp & DINO_MASK_IRQ(local_irq)) { 339 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", 340 __FUNCTION__, tmp); 341 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); 342 } 343} 344 345static unsigned int dino_startup_irq(unsigned int irq) 346{ 347 dino_enable_irq(irq); 348 return 0; 349} 350 351static struct hw_interrupt_type dino_interrupt_type = { 352 .typename = "GSC-PCI", 353 .startup = dino_startup_irq, 354 .shutdown = dino_disable_irq, 355 .enable = dino_enable_irq, 356 .disable = dino_disable_irq, 357 .ack = no_ack_irq, 358 .end = no_end_irq, 359}; 360 361 362/* 363 * Handle a Processor interrupt generated by Dino. 364 * 365 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from 366 * wedging the CPU. Could be removed or made optional at some point. 367 */ 368static irqreturn_t dino_isr(int irq, void *intr_dev) 369{ 370 struct dino_device *dino_dev = intr_dev; 371 u32 mask; 372 int ilr_loop = 100; 373 374 /* read and acknowledge pending interrupts */ 375#ifdef DINO_DEBUG 376 dino_dev->dino_irr0 = 377#endif 378 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; 379 380 if (mask == 0) 381 return IRQ_NONE; 382 383ilr_again: 384 do { 385 int local_irq = __ffs(mask); 386 int irq = dino_dev->global_irq[local_irq]; 387 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", 388 __FUNCTION__, irq, intr_dev, mask); 389 __do_IRQ(irq); 390 mask &= ~(1 << local_irq); 391 } while (mask); 392 393 /* Support for level triggered IRQ lines. 394 ** 395 ** Dropping this support would make this routine *much* faster. 396 ** But since PCI requires level triggered IRQ line to share lines... 397 ** device drivers may assume lines are level triggered (and not 398 ** edge triggered like EISA/ISA can be). 399 */ 400 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; 401 if (mask) { 402 if (--ilr_loop > 0) 403 goto ilr_again; 404 printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 405 dino_dev->hba.base_addr, mask); 406 return IRQ_NONE; 407 } 408 return IRQ_HANDLED; 409} 410 411static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) 412{ 413 int irq = gsc_assign_irq(&dino_interrupt_type, dino); 414 if (irq == NO_IRQ) 415 return; 416 417 *irqp = irq; 418 dino->global_irq[local_irq] = irq; 419} 420 421static void dino_choose_irq(struct parisc_device *dev, void *ctrl) 422{ 423 int irq; 424 struct dino_device *dino = ctrl; 425 426 switch (dev->id.sversion) { 427 case 0x00084: irq = 8; break; /* PS/2 */ 428 case 0x0008c: irq = 10; break; /* RS232 */ 429 case 0x00096: irq = 8; break; /* PS/2 */ 430 default: return; /* Unknown */ 431 } 432 433 dino_assign_irq(dino, irq, &dev->irq); 434} 435 436 437/* 438 * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de) 439 * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...) 440 */ 441static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev) 442{ 443 u8 new_irq = dev->irq - 1; 444 printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n", 445 pci_name(dev), dev->irq, new_irq); 446 dev->irq = new_irq; 447} 448DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus ); 449 450 451static void __init 452dino_bios_init(void) 453{ 454 DBG("dino_bios_init\n"); 455} 456 457/* 458 * dino_card_setup - Set up the memory space for a Dino in card mode. 459 * @bus: the bus under this dino 460 * 461 * Claim an 8MB chunk of unused IO space and call the generic PCI routines 462 * to set up the addresses of the devices on this bus. 463 */ 464#define _8MB 0x00800000UL 465static void __init 466dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) 467{ 468 int i; 469 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 470 struct resource *res; 471 char name[128]; 472 int size; 473 474 res = &dino_dev->hba.lmmio_space; 475 res->flags = IORESOURCE_MEM; 476 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 477 bus->bridge->bus_id); 478 res->name = kmalloc(size+1, GFP_KERNEL); 479 if(res->name) 480 strcpy((char *)res->name, name); 481 else 482 res->name = dino_dev->hba.lmmio_space.name; 483 484 485 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, 486 F_EXTEND(0xf0000000UL) | _8MB, 487 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { 488 struct list_head *ln, *tmp_ln; 489 490 printk(KERN_ERR "Dino: cannot attach bus %s\n", 491 bus->bridge->bus_id); 492 /* kill the bus, we can't do anything with it */ 493 list_for_each_safe(ln, tmp_ln, &bus->devices) { 494 struct pci_dev *dev = pci_dev_b(ln); 495 496 list_del(&dev->global_list); 497 list_del(&dev->bus_list); 498 } 499 500 return; 501 } 502 bus->resource[1] = res; 503 bus->resource[0] = &(dino_dev->hba.io_space); 504 505 /* Now tell dino what range it has */ 506 for (i = 1; i < 31; i++) { 507 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) 508 break; 509 } 510 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n", 511 i, res->start, base_addr + DINO_IO_ADDR_EN); 512 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); 513} 514 515static void __init 516dino_card_fixup(struct pci_dev *dev) 517{ 518 u32 irq_pin; 519 520 /* 521 ** REVISIT: card-mode PCI-PCI expansion chassis do exist. 522 ** Not sure they were ever productized. 523 ** Die here since we'll die later in dino_inb() anyway. 524 */ 525 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 526 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); 527 } 528 529 /* 530 ** Set Latency Timer to 0xff (not a shared bus) 531 ** Set CACHELINE_SIZE. 532 */ 533 dino_cfg_write(dev->bus, dev->devfn, 534 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 535 536 /* 537 ** Program INT_LINE for card-mode devices. 538 ** The cards are hardwired according to this algorithm. 539 ** And it doesn't matter if PPB's are present or not since 540 ** the IRQ lines bypass the PPB. 541 ** 542 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. 543 ** The additional "-1" adjusts for skewing the IRQ<->slot. 544 */ 545 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 546 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 547 548 /* Shouldn't really need to do this but it's in case someone tries 549 ** to bypass PCI services and look at the card themselves. 550 */ 551 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 552} 553 554/* The alignment contraints for PCI bridges under dino */ 555#define DINO_BRIDGE_ALIGN 0x100000 556 557 558static void __init 559dino_fixup_bus(struct pci_bus *bus) 560{ 561 struct list_head *ln; 562 struct pci_dev *dev; 563 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 564 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num); 565 566 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n", 567 __FUNCTION__, bus, bus->secondary, 568 bus->bridge->platform_data); 569 570 /* Firmware doesn't set up card-mode dino, so we have to */ 571 if (is_card_dino(&dino_dev->hba.dev->id)) { 572 dino_card_setup(bus, dino_dev->hba.base_addr); 573 } else if(bus->parent == NULL) { 574 /* must have a dino above it, reparent the resources 575 * into the dino window */ 576 int i; 577 struct resource *res = &dino_dev->hba.lmmio_space; 578 579 bus->resource[0] = &(dino_dev->hba.io_space); 580 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 581 if(res[i].flags == 0) 582 break; 583 bus->resource[i+1] = &res[i]; 584 } 585 586 } else if(bus->self) { 587 int i; 588 589 pci_read_bridge_bases(bus); 590 591 592 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 593 if((bus->self->resource[i].flags & 594 (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 595 continue; 596 597 if(bus->self->resource[i].flags & IORESOURCE_MEM) { 598 /* There's a quirk to alignment of 599 * bridge memory resources: the start 600 * is the alignment and start-end is 601 * the size. However, firmware will 602 * have assigned start and end, so we 603 * need to take this into account */ 604 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; 605 bus->self->resource[i].start = DINO_BRIDGE_ALIGN; 606 607 } 608 609 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", 610 bus->self->dev.bus_id, i, 611 bus->self->resource[i].start, 612 bus->self->resource[i].end); 613 pci_assign_resource(bus->self, i); 614 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", 615 bus->self->dev.bus_id, i, 616 bus->self->resource[i].start, 617 bus->self->resource[i].end); 618 } 619 } 620 621 622 list_for_each(ln, &bus->devices) { 623 int i; 624 625 dev = pci_dev_b(ln); 626 if (is_card_dino(&dino_dev->hba.dev->id)) 627 dino_card_fixup(dev); 628 629 /* 630 ** P2PB's only have 2 BARs, no IRQs. 631 ** I'd like to just ignore them for now. 632 */ 633 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 634 continue; 635 636 /* Adjust the I/O Port space addresses */ 637 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 638 struct resource *res = &dev->resource[i]; 639 if (res->flags & IORESOURCE_IO) { 640 res->start |= port_base; 641 res->end |= port_base; 642 } 643#ifdef __LP64__ 644 /* Sign Extend MMIO addresses */ 645 else if (res->flags & IORESOURCE_MEM) { 646 res->start |= F_EXTEND(0UL); 647 res->end |= F_EXTEND(0UL); 648 } 649#endif 650 } 651 /* null out the ROM resource if there is one (we don't 652 * care about an expansion rom on parisc, since it 653 * usually contains (x86) bios code) */ 654 dev->resource[PCI_ROM_RESOURCE].flags = 0; 655 656 if(dev->irq == 255) { 657 658#define DINO_FIX_UNASSIGNED_INTERRUPTS 659#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS 660 661 /* This code tries to assign an unassigned 662 * interrupt. Leave it disabled unless you 663 * *really* know what you're doing since the 664 * pin<->interrupt line mapping varies by bus 665 * and machine */ 666 667 u32 irq_pin; 668 669 dino_cfg_read(dev->bus, dev->devfn, 670 PCI_INTERRUPT_PIN, 1, &irq_pin); 671 irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 672 printk(KERN_WARNING "Device %s has undefined IRQ, " 673 "setting to %d\n", pci_name(dev), irq_pin); 674 dino_cfg_write(dev->bus, dev->devfn, 675 PCI_INTERRUPT_LINE, 1, irq_pin); 676 dino_assign_irq(dino_dev, irq_pin, &dev->irq); 677#else 678 dev->irq = 65535; 679 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); 680#endif 681 } else { 682 /* Adjust INT_LINE for that busses region */ 683 dino_assign_irq(dino_dev, dev->irq, &dev->irq); 684 } 685 } 686} 687 688 689struct pci_bios_ops dino_bios_ops = { 690 .init = dino_bios_init, 691 .fixup_bus = dino_fixup_bus 692}; 693 694 695/* 696 * Initialise a DINO controller chip 697 */ 698static void __init 699dino_card_init(struct dino_device *dino_dev) 700{ 701 u32 brdg_feat = 0x00784e05; 702 unsigned long status; 703 704 status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS); 705 if (status & 0x0000ff80) { 706 __raw_writel(0x00000005, 707 dino_dev->hba.base_addr+DINO_IO_COMMAND); 708 udelay(1); 709 } 710 711 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); 712 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); 713 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); 714 715/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ 716 /* 717 ** PCX-L processors don't support XQL like Dino wants it. 718 ** PCX-L2 ignore XQL signal and it doesn't matter. 719 */ 720 brdg_feat &= ~0x4; /* UXQL */ 721 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); 722 723 /* 724 ** Don't enable address decoding until we know which I/O range 725 ** currently is available from the host. Only affects MMIO 726 ** and not I/O port space. 727 */ 728 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); 729 730 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); 731 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); 732 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); 733 734 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); 735 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); 736 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); 737 738 /* Disable PAMR before writing PAPR */ 739 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); 740 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); 741 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); 742 743 /* 744 ** Dino ERS encourages enabling FBB (0x6f). 745 ** We can't until we know *all* devices below us can support it. 746 ** (Something in device configuration header tells us). 747 */ 748 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); 749 750 /* Somewhere, the PCI spec says give devices 1 second 751 ** to recover from the #RESET being de-asserted. 752 ** Experience shows most devices only need 10ms. 753 ** This short-cut speeds up booting significantly. 754 */ 755 mdelay(pci_post_reset_delay); 756} 757 758static int __init 759dino_bridge_init(struct dino_device *dino_dev, const char *name) 760{ 761 unsigned long io_addr; 762 int result, i, count=0; 763 struct resource *res, *prevres = NULL; 764 /* 765 * Decoding IO_ADDR_EN only works for Built-in Dino 766 * since PDC has already initialized this. 767 */ 768 769 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); 770 if (io_addr == 0) { 771 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); 772 return -ENODEV; 773 } 774 775 res = &dino_dev->hba.lmmio_space; 776 for (i = 0; i < 32; i++) { 777 unsigned long start, end; 778 779 if((io_addr & (1 << i)) == 0) 780 continue; 781 782 start = F_EXTEND(0xf0000000UL) | (i << 23); 783 end = start + 8 * 1024 * 1024 - 1; 784 785 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, 786 start, end); 787 788 if(prevres && prevres->end + 1 == start) { 789 prevres->end = end; 790 } else { 791 if(count >= DINO_MAX_LMMIO_RESOURCES) { 792 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); 793 break; 794 } 795 prevres = res; 796 res->start = start; 797 res->end = end; 798 res->flags = IORESOURCE_MEM; 799 res->name = kmalloc(64, GFP_KERNEL); 800 if(res->name) 801 snprintf((char *)res->name, 64, "%s LMMIO %d", 802 name, count); 803 res++; 804 count++; 805 } 806 } 807 808 res = &dino_dev->hba.lmmio_space; 809 810 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 811 if(res[i].flags == 0) 812 break; 813 814 result = ccio_request_resource(dino_dev->hba.dev, &res[i]); 815 if (result < 0) { 816 printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end); 817 return result; 818 } 819 } 820 return 0; 821} 822 823static int __init dino_common_init(struct parisc_device *dev, 824 struct dino_device *dino_dev, const char *name) 825{ 826 int status; 827 u32 eim; 828 struct gsc_irq gsc_irq; 829 struct resource *res; 830 831 pcibios_register_hba(&dino_dev->hba); 832 833 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ 834 pci_port = &dino_port_ops; 835 836 /* 837 ** Note: SMP systems can make use of IRR1/IAR1 registers 838 ** But it won't buy much performance except in very 839 ** specific applications/configurations. Note Dino 840 ** still only has 11 IRQ input lines - just map some of them 841 ** to a different processor. 842 */ 843 dev->irq = gsc_alloc_irq(&gsc_irq); 844 dino_dev->txn_addr = gsc_irq.txn_addr; 845 dino_dev->txn_data = gsc_irq.txn_data; 846 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; 847 848 /* 849 ** Dino needs a PA "IRQ" to get a processor's attention. 850 ** arch/parisc/kernel/irq.c returns an EIRR bit. 851 */ 852 if (dev->irq < 0) { 853 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); 854 return 1; 855 } 856 857 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); 858 if (status) { 859 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 860 name, status); 861 return 1; 862 } 863 864 /* Support the serial port which is sometimes attached on built-in 865 * Dino / Cujo chips. 866 */ 867 868 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); 869 870 /* 871 ** This enables DINO to generate interrupts when it sees 872 ** any of its inputs *change*. Just asserting an IRQ 873 ** before it's enabled (ie unmasked) isn't good enough. 874 */ 875 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); 876 877 /* 878 ** Some platforms don't clear Dino's IRR0 register at boot time. 879 ** Reading will clear it now. 880 */ 881 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); 882 883 /* allocate I/O Port resource region */ 884 res = &dino_dev->hba.io_space; 885 if (!is_cujo(&dev->id)) { 886 res->name = "Dino I/O Port"; 887 } else { 888 res->name = "Cujo I/O Port"; 889 } 890 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); 891 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); 892 res->flags = IORESOURCE_IO; /* do not mark it busy ! */ 893 if (request_resource(&ioport_resource, res) < 0) { 894 printk(KERN_ERR "%s: request I/O Port region failed " 895 "0x%lx/%lx (hpa 0x%p)\n", 896 name, res->start, res->end, dino_dev->hba.base_addr); 897 return 1; 898 } 899 900 return 0; 901} 902 903#define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) 904#define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) 905#define CUJO_RAVEN_BADPAGE 0x01003000UL 906#define CUJO_FIREHAWK_BADPAGE 0x01607000UL 907 908static const char *dino_vers[] = { 909 "2.0", 910 "2.1", 911 "3.0", 912 "3.1" 913}; 914 915static const char *cujo_vers[] = { 916 "1.0", 917 "2.0" 918}; 919 920void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); 921 922/* 923** Determine if dino should claim this chip (return 0) or not (return 1). 924** If so, initialize the chip appropriately (card-mode vs bridge mode). 925** Much of the initialization is common though. 926*/ 927static int __init dino_probe(struct parisc_device *dev) 928{ 929 struct dino_device *dino_dev; // Dino specific control struct 930 const char *version = "unknown"; 931 char *name; 932 int is_cujo = 0; 933 struct pci_bus *bus; 934 unsigned long hpa = dev->hpa.start; 935 936 name = "Dino"; 937 if (is_card_dino(&dev->id)) { 938 version = "3.x (card mode)"; 939 } else { 940 if (!is_cujo(&dev->id)) { 941 if (dev->id.hversion_rev < 4) { 942 version = dino_vers[dev->id.hversion_rev]; 943 } 944 } else { 945 name = "Cujo"; 946 is_cujo = 1; 947 if (dev->id.hversion_rev < 2) { 948 version = cujo_vers[dev->id.hversion_rev]; 949 } 950 } 951 } 952 953 printk("%s version %s found at 0x%lx\n", name, version, hpa); 954 955 if (!request_mem_region(hpa, PAGE_SIZE, name)) { 956 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n", 957 hpa); 958 return 1; 959 } 960 961 /* Check for bugs */ 962 if (is_cujo && dev->id.hversion_rev == 1) { 963#ifdef CONFIG_IOMMU_CCIO 964 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); 965 if (hpa == (unsigned long)CUJO_RAVEN_ADDR) { 966 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); 967 } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { 968 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); 969 } else { 970 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa); 971 } 972#endif 973 } else if (!is_cujo && !is_card_dino(&dev->id) && 974 dev->id.hversion_rev < 3) { 975 printk(KERN_WARNING 976"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" 977"data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" 978"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" 979"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", 980 dev->id.hversion_rev); 981/* REVISIT: why are C200/C240 listed in the README table but not 982** "Models affected"? Could be an omission in the original literature. 983*/ 984 } 985 986 dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL); 987 if (!dino_dev) { 988 printk("dino_init_chip - couldn't alloc dino_device\n"); 989 return 1; 990 } 991 992 dino_dev->hba.dev = dev; 993 dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096); 994 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */ 995 spin_lock_init(&dino_dev->dinosaur_pen); 996 dino_dev->hba.iommu = ccio_get_iommu(dev); 997 998 if (is_card_dino(&dev->id)) { 999 dino_card_init(dino_dev); 1000 } else { 1001 dino_bridge_init(dino_dev, name); 1002 } 1003 1004 if (dino_common_init(dev, dino_dev, name)) 1005 return 1; 1006 1007 dev->dev.platform_data = dino_dev; 1008 1009 /* 1010 ** It's not used to avoid chicken/egg problems 1011 ** with configuration accessor functions. 1012 */ 1013 bus = pci_scan_bus_parented(&dev->dev, dino_current_bus, 1014 &dino_cfg_ops, NULL); 1015 if(bus) { 1016 pci_bus_add_devices(bus); 1017 /* This code *depends* on scanning being single threaded 1018 * if it isn't, this global bus number count will fail 1019 */ 1020 dino_current_bus = bus->subordinate + 1; 1021 pci_bus_assign_resources(bus); 1022 } else { 1023 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus); 1024 /* increment the bus number in case of duplicates */ 1025 dino_current_bus++; 1026 } 1027 dino_dev->hba.hba_bus = bus; 1028 return 0; 1029} 1030 1031/* 1032 * Normally, we would just test sversion. But the Elroy PCI adapter has 1033 * the same sversion as Dino, so we have to check hversion as well. 1034 * Unfortunately, the J2240 PDC reports the wrong hversion for the first 1035 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. 1036 * For card-mode Dino, most machines report an sversion of 9D. But 715 1037 * and 725 firmware misreport it as 0x08080 for no adequately explained 1038 * reason. 1039 */ 1040static struct parisc_device_id dino_tbl[] = { 1041 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ 1042 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, 1043 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ 1044 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ 1045 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ 1046 { 0, } 1047}; 1048 1049static struct parisc_driver dino_driver = { 1050 .name = "dino", 1051 .id_table = dino_tbl, 1052 .probe = dino_probe, 1053}; 1054 1055/* 1056 * One time initialization to let the world know Dino is here. 1057 * This is the only routine which is NOT static. 1058 * Must be called exactly once before pci_init(). 1059 */ 1060int __init dino_init(void) 1061{ 1062 register_parisc_driver(&dino_driver); 1063 return 0; 1064} 1065