1/* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */ 2/* 3 Written 1998-2000 by Donald Becker. 4 5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please 6 send all bug reports to me, and not to Donald Becker, as this code 7 has been heavily modified from Donald's original version. 8 9 This software may be used and distributed according to the terms of 10 the GNU General Public License (GPL), incorporated herein by reference. 11 Drivers based on or derived from this code fall under the GPL and must 12 retain the authorship, copyright and license notice. This file is not 13 a complete program and may only be used when the entire operating 14 system is licensed under the GPL. 15 16 The information below comes from Donald Becker's original driver: 17 18 The author may be reached as becker@scyld.com, or C/O 19 Scyld Computing Corporation 20 410 Severn Ave., Suite 210 21 Annapolis MD 21403 22 23 Support and updates available at 24 http://www.scyld.com/network/starfire.html 25 [link no longer provides useful info -jgarzik] 26 27*/ 28 29#define DRV_NAME "starfire" 30#define DRV_VERSION "2.0" 31#define DRV_RELDATE "June 27, 2006" 32 33#include <linux/module.h> 34#include <linux/kernel.h> 35#include <linux/pci.h> 36#include <linux/netdevice.h> 37#include <linux/etherdevice.h> 38#include <linux/init.h> 39#include <linux/delay.h> 40#include <linux/crc32.h> 41#include <linux/ethtool.h> 42#include <linux/mii.h> 43#include <linux/if_vlan.h> 44#include <linux/mm.h> 45#include <asm/processor.h> /* Processor type for cache alignment. */ 46#include <asm/uaccess.h> 47#include <asm/io.h> 48 49#include "starfire_firmware.h" 50/* 51 * The current frame processor firmware fails to checksum a fragment 52 * of length 1. If and when this is fixed, the #define below can be removed. 53 */ 54#define HAS_BROKEN_FIRMWARE 55 56/* 57 * If using the broken firmware, data must be padded to the next 32-bit boundary. 58 */ 59#ifdef HAS_BROKEN_FIRMWARE 60#define PADDING_MASK 3 61#endif 62 63/* 64 * Define this if using the driver with the zero-copy patch 65 */ 66#define ZEROCOPY 67 68#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 69#define VLAN_SUPPORT 70#endif 71 72#ifndef CONFIG_ADAPTEC_STARFIRE_NAPI 73#undef HAVE_NETDEV_POLL 74#endif 75 76/* The user-configurable values. 77 These may be modified when a driver module is loaded.*/ 78 79/* Used for tuning interrupt latency vs. overhead. */ 80static int intr_latency; 81static int small_frames; 82 83static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ 84static int max_interrupt_work = 20; 85static int mtu; 86/* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 87 The Starfire has a 512 element hash table based on the Ethernet CRC. */ 88static const int multicast_filter_limit = 512; 89/* Whether to do TCP/UDP checksums in hardware */ 90static int enable_hw_cksum = 1; 91 92#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 93/* 94 * Set the copy breakpoint for the copy-only-tiny-frames scheme. 95 * Setting to > 1518 effectively disables this feature. 96 * 97 * NOTE: 98 * The ia64 doesn't allow for unaligned loads even of integers being 99 * misaligned on a 2 byte boundary. Thus always force copying of 100 * packets as the starfire doesn't allow for misaligned DMAs ;-( 101 * 23/10/2000 - Jes 102 * 103 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64, 104 * at least, having unaligned frames leads to a rather serious performance 105 * penalty. -Ion 106 */ 107#if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) 108static int rx_copybreak = PKT_BUF_SZ; 109#else 110static int rx_copybreak /* = 0 */; 111#endif 112 113/* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */ 114#ifdef __sparc__ 115#define DMA_BURST_SIZE 64 116#else 117#define DMA_BURST_SIZE 128 118#endif 119 120/* Used to pass the media type, etc. 121 Both 'options[]' and 'full_duplex[]' exist for driver interoperability. 122 The media type is usually passed in 'options[]'. 123 These variables are deprecated, use ethtool instead. -Ion 124*/ 125#define MAX_UNITS 8 /* More are supported, limit only on options */ 126static int options[MAX_UNITS] = {0, }; 127static int full_duplex[MAX_UNITS] = {0, }; 128 129/* Operational parameters that are set at compile time. */ 130 131/* The "native" ring sizes are either 256 or 2048. 132 However in some modes a descriptor may be marked to wrap the ring earlier. 133*/ 134#define RX_RING_SIZE 256 135#define TX_RING_SIZE 32 136/* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */ 137#define DONE_Q_SIZE 1024 138/* All queues must be aligned on a 256-byte boundary */ 139#define QUEUE_ALIGN 256 140 141#if RX_RING_SIZE > 256 142#define RX_Q_ENTRIES Rx2048QEntries 143#else 144#define RX_Q_ENTRIES Rx256QEntries 145#endif 146 147/* Operational parameters that usually are not changed. */ 148/* Time in jiffies before concluding the transmitter is hung. */ 149#define TX_TIMEOUT (2 * HZ) 150 151/* 152 * This SUCKS. 153 * We need a much better method to determine if dma_addr_t is 64-bit. 154 */ 155#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || \ 156 defined(__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && \ 157 defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) 158/* 64-bit dma_addr_t */ 159#define ADDR_64BITS /* This chip uses 64 bit addresses. */ 160#define netdrv_addr_t u64 161#define cpu_to_dma(x) cpu_to_le64(x) 162#define dma_to_cpu(x) le64_to_cpu(x) 163#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit 164#define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit 165#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit 166#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit 167#define RX_DESC_ADDR_SIZE RxDescAddr64bit 168#else /* 32-bit dma_addr_t */ 169#define netdrv_addr_t u32 170#define cpu_to_dma(x) cpu_to_le32(x) 171#define dma_to_cpu(x) le32_to_cpu(x) 172#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit 173#define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit 174#define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit 175#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit 176#define RX_DESC_ADDR_SIZE RxDescAddr32bit 177#endif 178 179#define skb_first_frag_len(skb) skb_headlen(skb) 180#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1) 181 182#ifdef HAVE_NETDEV_POLL 183#define init_poll(dev) \ 184do { \ 185 dev->poll = &netdev_poll; \ 186 dev->weight = max_interrupt_work; \ 187} while (0) 188#define netdev_rx(dev, ioaddr) \ 189do { \ 190 u32 intr_enable; \ 191 if (netif_rx_schedule_prep(dev)) { \ 192 __netif_rx_schedule(dev); \ 193 intr_enable = readl(ioaddr + IntrEnable); \ 194 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \ 195 writel(intr_enable, ioaddr + IntrEnable); \ 196 readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \ 197 } else { \ 198 /* Paranoia check */ \ 199 intr_enable = readl(ioaddr + IntrEnable); \ 200 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \ 201 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \ 202 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \ 203 writel(intr_enable, ioaddr + IntrEnable); \ 204 } \ 205 } \ 206} while (0) 207#define netdev_receive_skb(skb) netif_receive_skb(skb) 208#define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid) 209static int netdev_poll(struct net_device *dev, int *budget); 210#else /* not HAVE_NETDEV_POLL */ 211#define init_poll(dev) 212#define netdev_receive_skb(skb) netif_rx(skb) 213#define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid) 214#define netdev_rx(dev, ioaddr) \ 215do { \ 216 int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \ 217 __netdev_rx(dev, "a);\ 218} while (0) 219#endif /* not HAVE_NETDEV_POLL */ 220/* end of compatibility code */ 221 222 223/* These identify the driver base version and may not be removed. */ 224static const char version[] __devinitdata = 225KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" 226KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; 227 228MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 229MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver"); 230MODULE_LICENSE("GPL"); 231MODULE_VERSION(DRV_VERSION); 232 233module_param(max_interrupt_work, int, 0); 234module_param(mtu, int, 0); 235module_param(debug, int, 0); 236module_param(rx_copybreak, int, 0); 237module_param(intr_latency, int, 0); 238module_param(small_frames, int, 0); 239module_param_array(options, int, NULL, 0); 240module_param_array(full_duplex, int, NULL, 0); 241module_param(enable_hw_cksum, int, 0); 242MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt"); 243MODULE_PARM_DESC(mtu, "MTU (all boards)"); 244MODULE_PARM_DESC(debug, "Debug level (0-6)"); 245MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); 246MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds"); 247MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)"); 248MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex"); 249MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)"); 250MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)"); 251 252/* 253 Theory of Operation 254 255I. Board Compatibility 256 257This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter. 258 259II. Board-specific settings 260 261III. Driver operation 262 263IIIa. Ring buffers 264 265The Starfire hardware uses multiple fixed-size descriptor queues/rings. The 266ring sizes are set fixed by the hardware, but may optionally be wrapped 267earlier by the END bit in the descriptor. 268This driver uses that hardware queue size for the Rx ring, where a large 269number of entries has no ill effect beyond increases the potential backlog. 270The Tx ring is wrapped with the END bit, since a large hardware Tx queue 271disables the queue layer priority ordering and we have no mechanism to 272utilize the hardware two-level priority queue. When modifying the 273RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning 274levels. 275 276IIIb/c. Transmit/Receive Structure 277 278See the Adaptec manual for the many possible structures, and options for 279each structure. There are far too many to document all of them here. 280 281For transmit this driver uses type 0/1 transmit descriptors (depending 282on the 32/64 bitness of the architecture), and relies on automatic 283minimum-length padding. It does not use the completion queue 284consumer index, but instead checks for non-zero status entries. 285 286For receive this driver uses type 2/3 receive descriptors. The driver 287allocates full frame size skbuffs for the Rx ring buffers, so all frames 288should fit in a single descriptor. The driver does not use the completion 289queue consumer index, but instead checks for non-zero status entries. 290 291When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff 292is allocated and the frame is copied to the new skbuff. When the incoming 293frame is larger, the skbuff is passed directly up the protocol stack. 294Buffers consumed this way are replaced by newly allocated skbuffs in a later 295phase of receive. 296 297A notable aspect of operation is that unaligned buffers are not permitted by 298the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame 299isn't longword aligned, which may cause problems on some machine 300e.g. Alphas and IA64. For these architectures, the driver is forced to copy 301the frame into a new skbuff unconditionally. Copied frames are put into the 302skbuff at an offset of "+2", thus 16-byte aligning the IP header. 303 304IIId. Synchronization 305 306The driver runs as two independent, single-threaded flows of control. One 307is the send-packet routine, which enforces single-threaded use by the 308dev->tbusy flag. The other thread is the interrupt handler, which is single 309threaded by the hardware and interrupt handling software. 310 311The send packet thread has partial control over the Tx ring and the netif_queue 312status. If the number of free Tx slots in the ring falls below a certain number 313(currently hardcoded to 4), it signals the upper layer to stop the queue. 314 315The interrupt handler has exclusive control over the Rx ring and records stats 316from the Tx ring. After reaping the stats, it marks the Tx queue entry as 317empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the 318number of free Tx slow is above the threshold, it signals the upper layer to 319restart the queue. 320 321IV. Notes 322 323IVb. References 324 325The Adaptec Starfire manuals, available only from Adaptec. 326http://www.scyld.com/expert/100mbps.html 327http://www.scyld.com/expert/NWay.html 328 329IVc. Errata 330 331- StopOnPerr is broken, don't enable 332- Hardware ethernet padding exposes random data, perform software padding 333 instead (unverified -- works correctly for all the hardware I have) 334 335*/ 336 337 338 339enum chip_capability_flags {CanHaveMII=1, }; 340 341enum chipset { 342 CH_6915 = 0, 343}; 344 345static struct pci_device_id starfire_pci_tbl[] = { 346 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 }, 347 { 0, } 348}; 349MODULE_DEVICE_TABLE(pci, starfire_pci_tbl); 350 351/* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */ 352static const struct chip_info { 353 const char *name; 354 int drv_flags; 355} netdrv_tbl[] __devinitdata = { 356 { "Adaptec Starfire 6915", CanHaveMII }, 357}; 358 359 360/* Offsets to the device registers. 361 Unlike software-only systems, device drivers interact with complex hardware. 362 It's not useful to define symbolic names for every register bit in the 363 device. The name can only partially document the semantics and make 364 the driver longer and more difficult to read. 365 In general, only the important configuration values or bits changed 366 multiple times should be defined symbolically. 367*/ 368enum register_offsets { 369 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074, 370 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088, 371 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000, 372 GPIOCtrl=0x5008C, TxDescCtrl=0x50090, 373 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */ 374 TxRingHiAddr=0x5009C, /* 64 bit address extension. */ 375 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4, 376 TxThreshold=0x500B0, 377 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8, 378 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0, 379 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0, 380 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0, 381 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4, 382 TxMode=0x55000, VlanType=0x55064, 383 PerfFilterTable=0x56000, HashTable=0x56100, 384 TxGfpMem=0x58000, RxGfpMem=0x5a000, 385}; 386 387/* 388 * Bits in the interrupt status/mask registers. 389 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register 390 * enables all the interrupt sources that are or'ed into those status bits. 391 */ 392enum intr_status_bits { 393 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000, 394 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000, 395 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000, 396 IntrTxComplQLow=0x200000, IntrPCI=0x100000, 397 IntrDMAErr=0x080000, IntrTxDataLow=0x040000, 398 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000, 399 IntrNormalSummary=0x8000, IntrTxDone=0x4000, 400 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000, 401 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400, 402 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100, 403 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40, 404 IntrNoTxCsum=0x20, IntrTxBadID=0x10, 405 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04, 406 IntrTxGfp=0x02, IntrPCIPad=0x01, 407 /* not quite bits */ 408 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done, 409 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low, 410 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe, 411}; 412 413/* Bits in the RxFilterMode register. */ 414enum rx_mode_bits { 415 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01, 416 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30, 417 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200, 418 WakeupOnGFP=0x0800, 419}; 420 421/* Bits in the TxMode register */ 422enum tx_mode_bits { 423 MiiSoftReset=0x8000, MIILoopback=0x4000, 424 TxFlowEnable=0x0800, RxFlowEnable=0x0400, 425 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01, 426}; 427 428/* Bits in the TxDescCtrl register. */ 429enum tx_ctrl_bits { 430 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20, 431 TxDescSpace128=0x30, TxDescSpace256=0x40, 432 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02, 433 TxDescType3=0x03, TxDescType4=0x04, 434 TxNoDMACompletion=0x08, 435 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0, 436 TxHiPriFIFOThreshShift=24, TxPadLenShift=16, 437 TxDMABurstSizeShift=8, 438}; 439 440/* Bits in the RxDescQCtrl register. */ 441enum rx_ctrl_bits { 442 RxBufferLenShift=16, RxMinDescrThreshShift=0, 443 RxPrefetchMode=0x8000, RxVariableQ=0x2000, 444 Rx2048QEntries=0x4000, Rx256QEntries=0, 445 RxDescAddr64bit=0x1000, RxDescAddr32bit=0, 446 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0, 447 RxDescSpace4=0x000, RxDescSpace8=0x100, 448 RxDescSpace16=0x200, RxDescSpace32=0x300, 449 RxDescSpace64=0x400, RxDescSpace128=0x500, 450 RxConsumerWrEn=0x80, 451}; 452 453/* Bits in the RxDMACtrl register. */ 454enum rx_dmactrl_bits { 455 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000, 456 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000, 457 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000, 458 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000, 459 RxChecksumRejectTCPOnly=0x01000000, 460 RxCompletionQ2Enable=0x800000, 461 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000, 462 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000, 463 RxDMAQ2NonIP=0x400000, 464 RxUseBackupQueue=0x080000, RxDMACRC=0x040000, 465 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8, 466 RxBurstSizeShift=0, 467}; 468 469/* Bits in the RxCompletionAddr register */ 470enum rx_compl_bits { 471 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0, 472 RxComplProducerWrEn=0x40, 473 RxComplType0=0x00, RxComplType1=0x10, 474 RxComplType2=0x20, RxComplType3=0x30, 475 RxComplThreshShift=0, 476}; 477 478/* Bits in the TxCompletionAddr register */ 479enum tx_compl_bits { 480 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0, 481 TxComplProducerWrEn=0x40, 482 TxComplIntrStatus=0x20, 483 CommonQueueMode=0x10, 484 TxComplThreshShift=0, 485}; 486 487/* Bits in the GenCtrl register */ 488enum gen_ctrl_bits { 489 RxEnable=0x05, TxEnable=0x0a, 490 RxGFPEnable=0x10, TxGFPEnable=0x20, 491}; 492 493/* Bits in the IntrTimerCtrl register */ 494enum intr_ctrl_bits { 495 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100, 496 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600, 497 IntrLatencyMask=0x1f, 498}; 499 500/* The Rx and Tx buffer descriptors. */ 501struct starfire_rx_desc { 502 dma_addr_t rxaddr; 503}; 504enum rx_desc_bits { 505 RxDescValid=1, RxDescEndRing=2, 506}; 507 508/* Completion queue entry. */ 509struct short_rx_done_desc { 510 u32 status; /* Low 16 bits is length. */ 511}; 512struct basic_rx_done_desc { 513 u32 status; /* Low 16 bits is length. */ 514 u16 vlanid; 515 u16 status2; 516}; 517struct csum_rx_done_desc { 518 u32 status; /* Low 16 bits is length. */ 519 u16 csum; /* Partial checksum */ 520 u16 status2; 521}; 522struct full_rx_done_desc { 523 u32 status; /* Low 16 bits is length. */ 524 u16 status3; 525 u16 status2; 526 u16 vlanid; 527 u16 csum; /* partial checksum */ 528 u32 timestamp; 529}; 530#ifdef VLAN_SUPPORT 531typedef struct full_rx_done_desc rx_done_desc; 532#define RxComplType RxComplType3 533#else /* not VLAN_SUPPORT */ 534typedef struct csum_rx_done_desc rx_done_desc; 535#define RxComplType RxComplType2 536#endif /* not VLAN_SUPPORT */ 537 538enum rx_done_bits { 539 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000, 540}; 541 542/* Type 1 Tx descriptor. */ 543struct starfire_tx_desc_1 { 544 u32 status; /* Upper bits are status, lower 16 length. */ 545 u32 addr; 546}; 547 548/* Type 2 Tx descriptor. */ 549struct starfire_tx_desc_2 { 550 u32 status; /* Upper bits are status, lower 16 length. */ 551 u32 reserved; 552 u64 addr; 553}; 554 555#ifdef ADDR_64BITS 556typedef struct starfire_tx_desc_2 starfire_tx_desc; 557#define TX_DESC_TYPE TxDescType2 558#else /* not ADDR_64BITS */ 559typedef struct starfire_tx_desc_1 starfire_tx_desc; 560#define TX_DESC_TYPE TxDescType1 561#endif /* not ADDR_64BITS */ 562#define TX_DESC_SPACING TxDescSpaceUnlim 563 564enum tx_desc_bits { 565 TxDescID=0xB0000000, 566 TxCRCEn=0x01000000, TxDescIntr=0x08000000, 567 TxRingWrap=0x04000000, TxCalTCP=0x02000000, 568}; 569struct tx_done_desc { 570 u32 status; /* timestamp, index. */ 571}; 572 573struct rx_ring_info { 574 struct sk_buff *skb; 575 dma_addr_t mapping; 576}; 577struct tx_ring_info { 578 struct sk_buff *skb; 579 dma_addr_t mapping; 580 unsigned int used_slots; 581}; 582 583#define PHY_CNT 2 584struct netdev_private { 585 /* Descriptor rings first for alignment. */ 586 struct starfire_rx_desc *rx_ring; 587 starfire_tx_desc *tx_ring; 588 dma_addr_t rx_ring_dma; 589 dma_addr_t tx_ring_dma; 590 /* The addresses of rx/tx-in-place skbuffs. */ 591 struct rx_ring_info rx_info[RX_RING_SIZE]; 592 struct tx_ring_info tx_info[TX_RING_SIZE]; 593 /* Pointers to completion queues (full pages). */ 594 rx_done_desc *rx_done_q; 595 dma_addr_t rx_done_q_dma; 596 unsigned int rx_done; 597 struct tx_done_desc *tx_done_q; 598 dma_addr_t tx_done_q_dma; 599 unsigned int tx_done; 600 struct net_device_stats stats; 601 struct pci_dev *pci_dev; 602#ifdef VLAN_SUPPORT 603 struct vlan_group *vlgrp; 604#endif 605 void *queue_mem; 606 dma_addr_t queue_mem_dma; 607 size_t queue_mem_size; 608 609 /* Frequently used values: keep some adjacent for cache effect. */ 610 spinlock_t lock; 611 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ 612 unsigned int cur_tx, dirty_tx, reap_tx; 613 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 614 /* These values keep track of the transceiver/media in use. */ 615 int speed100; /* Set if speed == 100MBit. */ 616 u32 tx_mode; 617 u32 intr_timer_ctrl; 618 u8 tx_threshold; 619 /* MII transceiver section. */ 620 struct mii_if_info mii_if; /* MII lib hooks/info */ 621 int phy_cnt; /* MII device addresses. */ 622 unsigned char phys[PHY_CNT]; /* MII device addresses. */ 623 void __iomem *base; 624}; 625 626 627static int mdio_read(struct net_device *dev, int phy_id, int location); 628static void mdio_write(struct net_device *dev, int phy_id, int location, int value); 629static int netdev_open(struct net_device *dev); 630static void check_duplex(struct net_device *dev); 631static void tx_timeout(struct net_device *dev); 632static void init_ring(struct net_device *dev); 633static int start_tx(struct sk_buff *skb, struct net_device *dev); 634static irqreturn_t intr_handler(int irq, void *dev_instance); 635static void netdev_error(struct net_device *dev, int intr_status); 636static int __netdev_rx(struct net_device *dev, int *quota); 637static void refill_rx_ring(struct net_device *dev); 638static void netdev_error(struct net_device *dev, int intr_status); 639static void set_rx_mode(struct net_device *dev); 640static struct net_device_stats *get_stats(struct net_device *dev); 641static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 642static int netdev_close(struct net_device *dev); 643static void netdev_media_change(struct net_device *dev); 644static const struct ethtool_ops ethtool_ops; 645 646 647#ifdef VLAN_SUPPORT 648static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) 649{ 650 struct netdev_private *np = netdev_priv(dev); 651 652 spin_lock(&np->lock); 653 if (debug > 2) 654 printk("%s: Setting vlgrp to %p\n", dev->name, grp); 655 np->vlgrp = grp; 656 set_rx_mode(dev); 657 spin_unlock(&np->lock); 658} 659 660static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) 661{ 662 struct netdev_private *np = netdev_priv(dev); 663 664 spin_lock(&np->lock); 665 if (debug > 1) 666 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid); 667 set_rx_mode(dev); 668 spin_unlock(&np->lock); 669} 670 671static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) 672{ 673 struct netdev_private *np = netdev_priv(dev); 674 675 spin_lock(&np->lock); 676 if (debug > 1) 677 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid); 678 vlan_group_set_device(np->vlgrp, vid, NULL); 679 set_rx_mode(dev); 680 spin_unlock(&np->lock); 681} 682#endif /* VLAN_SUPPORT */ 683 684 685static int __devinit starfire_init_one(struct pci_dev *pdev, 686 const struct pci_device_id *ent) 687{ 688 struct netdev_private *np; 689 int i, irq, option, chip_idx = ent->driver_data; 690 struct net_device *dev; 691 static int card_idx = -1; 692 long ioaddr; 693 void __iomem *base; 694 int drv_flags, io_size; 695 int boguscnt; 696 697/* when built into the kernel, we only print version if device is found */ 698#ifndef MODULE 699 static int printed_version; 700 if (!printed_version++) 701 printk(version); 702#endif 703 704 card_idx++; 705 706 if (pci_enable_device (pdev)) 707 return -EIO; 708 709 ioaddr = pci_resource_start(pdev, 0); 710 io_size = pci_resource_len(pdev, 0); 711 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) { 712 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx); 713 return -ENODEV; 714 } 715 716 dev = alloc_etherdev(sizeof(*np)); 717 if (!dev) { 718 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx); 719 return -ENOMEM; 720 } 721 SET_MODULE_OWNER(dev); 722 SET_NETDEV_DEV(dev, &pdev->dev); 723 724 irq = pdev->irq; 725 726 if (pci_request_regions (pdev, DRV_NAME)) { 727 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx); 728 goto err_out_free_netdev; 729 } 730 731 base = ioremap(ioaddr, io_size); 732 if (!base) { 733 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n", 734 card_idx, io_size, ioaddr); 735 goto err_out_free_res; 736 } 737 738 pci_set_master(pdev); 739 740 /* enable MWI -- it vastly improves Rx performance on sparc64 */ 741 pci_set_mwi(pdev); 742 743#ifdef ZEROCOPY 744 /* Starfire can do TCP/UDP checksumming */ 745 if (enable_hw_cksum) 746 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 747#endif /* ZEROCOPY */ 748#ifdef VLAN_SUPPORT 749 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; 750 dev->vlan_rx_register = netdev_vlan_rx_register; 751 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid; 752 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid; 753#endif /* VLAN_RX_KILL_VID */ 754#ifdef ADDR_64BITS 755 dev->features |= NETIF_F_HIGHDMA; 756#endif /* ADDR_64BITS */ 757 758 /* Serial EEPROM reads are hidden by the hardware. */ 759 for (i = 0; i < 6; i++) 760 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i); 761 762#if !defined(final_version) /* Dump the EEPROM contents during development. */ 763 if (debug > 4) 764 for (i = 0; i < 0x20; i++) 765 printk("%2.2x%s", 766 (unsigned int)readb(base + EEPROMCtrl + i), 767 i % 16 != 15 ? " " : "\n"); 768#endif 769 770 /* Issue soft reset */ 771 writel(MiiSoftReset, base + TxMode); 772 udelay(1000); 773 writel(0, base + TxMode); 774 775 /* Reset the chip to erase previous misconfiguration. */ 776 writel(1, base + PCIDeviceConfig); 777 boguscnt = 1000; 778 while (--boguscnt > 0) { 779 udelay(10); 780 if ((readl(base + PCIDeviceConfig) & 1) == 0) 781 break; 782 } 783 if (boguscnt == 0) 784 printk("%s: chipset reset never completed!\n", dev->name); 785 /* wait a little longer */ 786 udelay(1000); 787 788 dev->base_addr = (unsigned long)base; 789 dev->irq = irq; 790 791 np = netdev_priv(dev); 792 np->base = base; 793 spin_lock_init(&np->lock); 794 pci_set_drvdata(pdev, dev); 795 796 np->pci_dev = pdev; 797 798 np->mii_if.dev = dev; 799 np->mii_if.mdio_read = mdio_read; 800 np->mii_if.mdio_write = mdio_write; 801 np->mii_if.phy_id_mask = 0x1f; 802 np->mii_if.reg_num_mask = 0x1f; 803 804 drv_flags = netdrv_tbl[chip_idx].drv_flags; 805 806 option = card_idx < MAX_UNITS ? options[card_idx] : 0; 807 if (dev->mem_start) 808 option = dev->mem_start; 809 810 /* The lower four bits are the media type. */ 811 if (option & 0x200) 812 np->mii_if.full_duplex = 1; 813 814 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) 815 np->mii_if.full_duplex = 1; 816 817 if (np->mii_if.full_duplex) 818 np->mii_if.force_media = 1; 819 else 820 np->mii_if.force_media = 0; 821 np->speed100 = 1; 822 823 /* timer resolution is 128 * 0.8us */ 824 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) | 825 Timer10X | EnableIntrMasking; 826 827 if (small_frames > 0) { 828 np->intr_timer_ctrl |= SmallFrameBypass; 829 switch (small_frames) { 830 case 1 ... 64: 831 np->intr_timer_ctrl |= SmallFrame64; 832 break; 833 case 65 ... 128: 834 np->intr_timer_ctrl |= SmallFrame128; 835 break; 836 case 129 ... 256: 837 np->intr_timer_ctrl |= SmallFrame256; 838 break; 839 default: 840 np->intr_timer_ctrl |= SmallFrame512; 841 if (small_frames > 512) 842 printk("Adjusting small_frames down to 512\n"); 843 break; 844 } 845 } 846 847 /* The chip-specific entries in the device structure. */ 848 dev->open = &netdev_open; 849 dev->hard_start_xmit = &start_tx; 850 dev->tx_timeout = tx_timeout; 851 dev->watchdog_timeo = TX_TIMEOUT; 852 init_poll(dev); 853 dev->stop = &netdev_close; 854 dev->get_stats = &get_stats; 855 dev->set_multicast_list = &set_rx_mode; 856 dev->do_ioctl = &netdev_ioctl; 857 SET_ETHTOOL_OPS(dev, ðtool_ops); 858 859 if (mtu) 860 dev->mtu = mtu; 861 862 if (register_netdev(dev)) 863 goto err_out_cleardev; 864 865 printk(KERN_INFO "%s: %s at %p, ", 866 dev->name, netdrv_tbl[chip_idx].name, base); 867 for (i = 0; i < 5; i++) 868 printk("%2.2x:", dev->dev_addr[i]); 869 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq); 870 871 if (drv_flags & CanHaveMII) { 872 int phy, phy_idx = 0; 873 int mii_status; 874 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) { 875 mdio_write(dev, phy, MII_BMCR, BMCR_RESET); 876 mdelay(100); 877 boguscnt = 1000; 878 while (--boguscnt > 0) 879 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0) 880 break; 881 if (boguscnt == 0) { 882 printk("%s: PHY#%d reset never completed!\n", dev->name, phy); 883 continue; 884 } 885 mii_status = mdio_read(dev, phy, MII_BMSR); 886 if (mii_status != 0) { 887 np->phys[phy_idx++] = phy; 888 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE); 889 printk(KERN_INFO "%s: MII PHY found at address %d, status " 890 "%#4.4x advertising %#4.4x.\n", 891 dev->name, phy, mii_status, np->mii_if.advertising); 892 /* there can be only one PHY on-board */ 893 break; 894 } 895 } 896 np->phy_cnt = phy_idx; 897 if (np->phy_cnt > 0) 898 np->mii_if.phy_id = np->phys[0]; 899 else 900 memset(&np->mii_if, 0, sizeof(np->mii_if)); 901 } 902 903 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n", 904 dev->name, enable_hw_cksum ? "enabled" : "disabled"); 905 return 0; 906 907err_out_cleardev: 908 pci_set_drvdata(pdev, NULL); 909 iounmap(base); 910err_out_free_res: 911 pci_release_regions (pdev); 912err_out_free_netdev: 913 free_netdev(dev); 914 return -ENODEV; 915} 916 917 918/* Read the MII Management Data I/O (MDIO) interfaces. */ 919static int mdio_read(struct net_device *dev, int phy_id, int location) 920{ 921 struct netdev_private *np = netdev_priv(dev); 922 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); 923 int result, boguscnt=1000; 924 /* ??? Should we add a busy-wait here? */ 925 do 926 result = readl(mdio_addr); 927 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0); 928 if (boguscnt == 0) 929 return 0; 930 if ((result & 0xffff) == 0xffff) 931 return 0; 932 return result & 0xffff; 933} 934 935 936static void mdio_write(struct net_device *dev, int phy_id, int location, int value) 937{ 938 struct netdev_private *np = netdev_priv(dev); 939 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); 940 writel(value, mdio_addr); 941 /* The busy-wait will occur before a read. */ 942} 943 944 945static int netdev_open(struct net_device *dev) 946{ 947 struct netdev_private *np = netdev_priv(dev); 948 void __iomem *ioaddr = np->base; 949 int i, retval; 950 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size; 951 952 /* Do we ever need to reset the chip??? */ 953 954 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev); 955 if (retval) 956 return retval; 957 958 /* Disable the Rx and Tx, and reset the chip. */ 959 writel(0, ioaddr + GenCtrl); 960 writel(1, ioaddr + PCIDeviceConfig); 961 if (debug > 1) 962 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", 963 dev->name, dev->irq); 964 965 /* Allocate the various queues. */ 966 if (np->queue_mem == 0) { 967 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; 968 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; 969 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; 970 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE; 971 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size; 972 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma); 973 if (np->queue_mem == NULL) { 974 free_irq(dev->irq, dev); 975 return -ENOMEM; 976 } 977 978 np->tx_done_q = np->queue_mem; 979 np->tx_done_q_dma = np->queue_mem_dma; 980 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size; 981 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size; 982 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size; 983 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size; 984 np->rx_ring = (void *) np->tx_ring + tx_ring_size; 985 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size; 986 } 987 988 /* Start with no carrier, it gets adjusted later */ 989 netif_carrier_off(dev); 990 init_ring(dev); 991 /* Set the size of the Rx buffers. */ 992 writel((np->rx_buf_sz << RxBufferLenShift) | 993 (0 << RxMinDescrThreshShift) | 994 RxPrefetchMode | RxVariableQ | 995 RX_Q_ENTRIES | 996 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE | 997 RxDescSpace4, 998 ioaddr + RxDescQCtrl); 999 1000 /* Set up the Rx DMA controller. */ 1001 writel(RxChecksumIgnore | 1002 (0 << RxEarlyIntThreshShift) | 1003 (6 << RxHighPrioThreshShift) | 1004 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift), 1005 ioaddr + RxDMACtrl); 1006 1007 /* Set Tx descriptor */ 1008 writel((2 << TxHiPriFIFOThreshShift) | 1009 (0 << TxPadLenShift) | 1010 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) | 1011 TX_DESC_Q_ADDR_SIZE | 1012 TX_DESC_SPACING | TX_DESC_TYPE, 1013 ioaddr + TxDescCtrl); 1014 1015 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr); 1016 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr); 1017 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr); 1018 writel(np->rx_ring_dma, ioaddr + RxDescQAddr); 1019 writel(np->tx_ring_dma, ioaddr + TxRingPtr); 1020 1021 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr); 1022 writel(np->rx_done_q_dma | 1023 RxComplType | 1024 (0 << RxComplThreshShift), 1025 ioaddr + RxCompletionAddr); 1026 1027 if (debug > 1) 1028 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name); 1029 1030 /* Fill both the Tx SA register and the Rx perfect filter. */ 1031 for (i = 0; i < 6; i++) 1032 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i); 1033 /* The first entry is special because it bypasses the VLAN filter. 1034 Don't use it. */ 1035 writew(0, ioaddr + PerfFilterTable); 1036 writew(0, ioaddr + PerfFilterTable + 4); 1037 writew(0, ioaddr + PerfFilterTable + 8); 1038 for (i = 1; i < 16; i++) { 1039 u16 *eaddrs = (u16 *)dev->dev_addr; 1040 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16; 1041 writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4; 1042 writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4; 1043 writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8; 1044 } 1045 1046 /* Initialize other registers. */ 1047 /* Configure the PCI bus bursts and FIFO thresholds. */ 1048 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */ 1049 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode); 1050 udelay(1000); 1051 writel(np->tx_mode, ioaddr + TxMode); 1052 np->tx_threshold = 4; 1053 writel(np->tx_threshold, ioaddr + TxThreshold); 1054 1055 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl); 1056 1057 netif_start_queue(dev); 1058 1059 if (debug > 1) 1060 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name); 1061 set_rx_mode(dev); 1062 1063 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE); 1064 check_duplex(dev); 1065 1066 /* Enable GPIO interrupts on link change */ 1067 writel(0x0f00ff00, ioaddr + GPIOCtrl); 1068 1069 /* Set the interrupt mask */ 1070 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr | 1071 IntrTxDMADone | IntrStatsMax | IntrLinkChange | 1072 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID, 1073 ioaddr + IntrEnable); 1074 /* Enable PCI interrupts. */ 1075 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig), 1076 ioaddr + PCIDeviceConfig); 1077 1078#ifdef VLAN_SUPPORT 1079 /* Set VLAN type to 802.1q */ 1080 writel(ETH_P_8021Q, ioaddr + VlanType); 1081#endif /* VLAN_SUPPORT */ 1082 1083 /* Load Rx/Tx firmware into the frame processors */ 1084 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++) 1085 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4); 1086 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++) 1087 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4); 1088 if (enable_hw_cksum) 1089 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */ 1090 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl); 1091 else 1092 /* Enable the Rx and Tx units only. */ 1093 writel(TxEnable|RxEnable, ioaddr + GenCtrl); 1094 1095 if (debug > 1) 1096 printk(KERN_DEBUG "%s: Done netdev_open().\n", 1097 dev->name); 1098 1099 return 0; 1100} 1101 1102 1103static void check_duplex(struct net_device *dev) 1104{ 1105 struct netdev_private *np = netdev_priv(dev); 1106 u16 reg0; 1107 int silly_count = 1000; 1108 1109 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising); 1110 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET); 1111 udelay(500); 1112 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET) 1113 /* do nothing */; 1114 if (!silly_count) { 1115 printk("%s: MII reset failed!\n", dev->name); 1116 return; 1117 } 1118 1119 reg0 = mdio_read(dev, np->phys[0], MII_BMCR); 1120 1121 if (!np->mii_if.force_media) { 1122 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART; 1123 } else { 1124 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART); 1125 if (np->speed100) 1126 reg0 |= BMCR_SPEED100; 1127 if (np->mii_if.full_duplex) 1128 reg0 |= BMCR_FULLDPLX; 1129 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n", 1130 dev->name, 1131 np->speed100 ? "100" : "10", 1132 np->mii_if.full_duplex ? "full" : "half"); 1133 } 1134 mdio_write(dev, np->phys[0], MII_BMCR, reg0); 1135} 1136 1137 1138static void tx_timeout(struct net_device *dev) 1139{ 1140 struct netdev_private *np = netdev_priv(dev); 1141 void __iomem *ioaddr = np->base; 1142 int old_debug; 1143 1144 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, " 1145 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus)); 1146 1147 /* Perhaps we should reinitialize the hardware here. */ 1148 1149 /* 1150 * Stop and restart the interface. 1151 * Cheat and increase the debug level temporarily. 1152 */ 1153 old_debug = debug; 1154 debug = 2; 1155 netdev_close(dev); 1156 netdev_open(dev); 1157 debug = old_debug; 1158 1159 /* Trigger an immediate transmit demand. */ 1160 1161 dev->trans_start = jiffies; 1162 np->stats.tx_errors++; 1163 netif_wake_queue(dev); 1164} 1165 1166 1167/* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1168static void init_ring(struct net_device *dev) 1169{ 1170 struct netdev_private *np = netdev_priv(dev); 1171 int i; 1172 1173 np->cur_rx = np->cur_tx = np->reap_tx = 0; 1174 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0; 1175 1176 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); 1177 1178 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1179 for (i = 0; i < RX_RING_SIZE; i++) { 1180 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz); 1181 np->rx_info[i].skb = skb; 1182 if (skb == NULL) 1183 break; 1184 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1185 skb->dev = dev; /* Mark as being used by this device. */ 1186 /* Grrr, we cannot offset to correctly align the IP header. */ 1187 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid); 1188 } 1189 writew(i - 1, np->base + RxDescQIdx); 1190 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); 1191 1192 /* Clear the remainder of the Rx buffer ring. */ 1193 for ( ; i < RX_RING_SIZE; i++) { 1194 np->rx_ring[i].rxaddr = 0; 1195 np->rx_info[i].skb = NULL; 1196 np->rx_info[i].mapping = 0; 1197 } 1198 /* Mark the last entry as wrapping the ring. */ 1199 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing); 1200 1201 /* Clear the completion rings. */ 1202 for (i = 0; i < DONE_Q_SIZE; i++) { 1203 np->rx_done_q[i].status = 0; 1204 np->tx_done_q[i].status = 0; 1205 } 1206 1207 for (i = 0; i < TX_RING_SIZE; i++) 1208 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i])); 1209 1210 return; 1211} 1212 1213 1214static int start_tx(struct sk_buff *skb, struct net_device *dev) 1215{ 1216 struct netdev_private *np = netdev_priv(dev); 1217 unsigned int entry; 1218 u32 status; 1219 int i; 1220 1221 /* 1222 * be cautious here, wrapping the queue has weird semantics 1223 * and we may not have enough slots even when it seems we do. 1224 */ 1225 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) { 1226 netif_stop_queue(dev); 1227 return 1; 1228 } 1229 1230#if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE) 1231 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1232 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK)) 1233 return NETDEV_TX_OK; 1234 } 1235#endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */ 1236 1237 entry = np->cur_tx % TX_RING_SIZE; 1238 for (i = 0; i < skb_num_frags(skb); i++) { 1239 int wrap_ring = 0; 1240 status = TxDescID; 1241 1242 if (i == 0) { 1243 np->tx_info[entry].skb = skb; 1244 status |= TxCRCEn; 1245 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) { 1246 status |= TxRingWrap; 1247 wrap_ring = 1; 1248 } 1249 if (np->reap_tx) { 1250 status |= TxDescIntr; 1251 np->reap_tx = 0; 1252 } 1253 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1254 status |= TxCalTCP; 1255 np->stats.tx_compressed++; 1256 } 1257 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16); 1258 1259 np->tx_info[entry].mapping = 1260 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE); 1261 } else { 1262 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1]; 1263 status |= this_frag->size; 1264 np->tx_info[entry].mapping = 1265 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE); 1266 } 1267 1268 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping); 1269 np->tx_ring[entry].status = cpu_to_le32(status); 1270 if (debug > 3) 1271 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n", 1272 dev->name, np->cur_tx, np->dirty_tx, 1273 entry, status); 1274 if (wrap_ring) { 1275 np->tx_info[entry].used_slots = TX_RING_SIZE - entry; 1276 np->cur_tx += np->tx_info[entry].used_slots; 1277 entry = 0; 1278 } else { 1279 np->tx_info[entry].used_slots = 1; 1280 np->cur_tx += np->tx_info[entry].used_slots; 1281 entry++; 1282 } 1283 /* scavenge the tx descriptors twice per TX_RING_SIZE */ 1284 if (np->cur_tx % (TX_RING_SIZE / 2) == 0) 1285 np->reap_tx = 1; 1286 } 1287 1288 /* Non-x86: explicitly flush descriptor cache lines here. */ 1289 /* Ensure all descriptors are written back before the transmit is 1290 initiated. - Jes */ 1291 wmb(); 1292 1293 /* Update the producer index. */ 1294 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx); 1295 1296 /* 4 is arbitrary, but should be ok */ 1297 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE) 1298 netif_stop_queue(dev); 1299 1300 dev->trans_start = jiffies; 1301 1302 return 0; 1303} 1304 1305 1306/* The interrupt handler does all of the Rx thread work and cleans up 1307 after the Tx thread. */ 1308static irqreturn_t intr_handler(int irq, void *dev_instance) 1309{ 1310 struct net_device *dev = dev_instance; 1311 struct netdev_private *np = netdev_priv(dev); 1312 void __iomem *ioaddr = np->base; 1313 int boguscnt = max_interrupt_work; 1314 int consumer; 1315 int tx_status; 1316 int handled = 0; 1317 1318 do { 1319 u32 intr_status = readl(ioaddr + IntrClear); 1320 1321 if (debug > 4) 1322 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n", 1323 dev->name, intr_status); 1324 1325 if (intr_status == 0 || intr_status == (u32) -1) 1326 break; 1327 1328 handled = 1; 1329 1330 if (intr_status & (IntrRxDone | IntrRxEmpty)) 1331 netdev_rx(dev, ioaddr); 1332 1333 /* Scavenge the skbuff list based on the Tx-done queue. 1334 There are redundant checks here that may be cleaned up 1335 after the driver has proven to be reliable. */ 1336 consumer = readl(ioaddr + TxConsumerIdx); 1337 if (debug > 3) 1338 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n", 1339 dev->name, consumer); 1340 1341 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) { 1342 if (debug > 3) 1343 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n", 1344 dev->name, np->dirty_tx, np->tx_done, tx_status); 1345 if ((tx_status & 0xe0000000) == 0xa0000000) { 1346 np->stats.tx_packets++; 1347 } else if ((tx_status & 0xe0000000) == 0x80000000) { 1348 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc); 1349 struct sk_buff *skb = np->tx_info[entry].skb; 1350 np->tx_info[entry].skb = NULL; 1351 pci_unmap_single(np->pci_dev, 1352 np->tx_info[entry].mapping, 1353 skb_first_frag_len(skb), 1354 PCI_DMA_TODEVICE); 1355 np->tx_info[entry].mapping = 0; 1356 np->dirty_tx += np->tx_info[entry].used_slots; 1357 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE; 1358 { 1359 int i; 1360 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1361 pci_unmap_single(np->pci_dev, 1362 np->tx_info[entry].mapping, 1363 skb_shinfo(skb)->frags[i].size, 1364 PCI_DMA_TODEVICE); 1365 np->dirty_tx++; 1366 entry++; 1367 } 1368 } 1369 1370 dev_kfree_skb_irq(skb); 1371 } 1372 np->tx_done_q[np->tx_done].status = 0; 1373 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE; 1374 } 1375 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2); 1376 1377 if (netif_queue_stopped(dev) && 1378 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) { 1379 /* The ring is no longer full, wake the queue. */ 1380 netif_wake_queue(dev); 1381 } 1382 1383 /* Stats overflow */ 1384 if (intr_status & IntrStatsMax) 1385 get_stats(dev); 1386 1387 /* Media change interrupt. */ 1388 if (intr_status & IntrLinkChange) 1389 netdev_media_change(dev); 1390 1391 /* Abnormal error summary/uncommon events handlers. */ 1392 if (intr_status & IntrAbnormalSummary) 1393 netdev_error(dev, intr_status); 1394 1395 if (--boguscnt < 0) { 1396 if (debug > 1) 1397 printk(KERN_WARNING "%s: Too much work at interrupt, " 1398 "status=%#8.8x.\n", 1399 dev->name, intr_status); 1400 break; 1401 } 1402 } while (1); 1403 1404 if (debug > 4) 1405 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n", 1406 dev->name, (int) readl(ioaddr + IntrStatus)); 1407 return IRQ_RETVAL(handled); 1408} 1409 1410 1411/* This routine is logically part of the interrupt/poll handler, but separated 1412 for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */ 1413static int __netdev_rx(struct net_device *dev, int *quota) 1414{ 1415 struct netdev_private *np = netdev_priv(dev); 1416 u32 desc_status; 1417 int retcode = 0; 1418 1419 /* If EOP is set on the next entry, it's a new packet. Send it up. */ 1420 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) { 1421 struct sk_buff *skb; 1422 u16 pkt_len; 1423 int entry; 1424 rx_done_desc *desc = &np->rx_done_q[np->rx_done]; 1425 1426 if (debug > 4) 1427 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status); 1428 if (!(desc_status & RxOK)) { 1429 /* There was an error. */ 1430 if (debug > 2) 1431 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status); 1432 np->stats.rx_errors++; 1433 if (desc_status & RxFIFOErr) 1434 np->stats.rx_fifo_errors++; 1435 goto next_rx; 1436 } 1437 1438 if (*quota <= 0) { /* out of rx quota */ 1439 retcode = 1; 1440 goto out; 1441 } 1442 (*quota)--; 1443 1444 pkt_len = desc_status; /* Implicitly Truncate */ 1445 entry = (desc_status >> 16) & 0x7ff; 1446 1447 if (debug > 4) 1448 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota); 1449 /* Check if the packet is long enough to accept without copying 1450 to a minimally-sized skbuff. */ 1451 if (pkt_len < rx_copybreak 1452 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { 1453 skb_reserve(skb, 2); /* 16 byte align the IP header */ 1454 pci_dma_sync_single_for_cpu(np->pci_dev, 1455 np->rx_info[entry].mapping, 1456 pkt_len, PCI_DMA_FROMDEVICE); 1457 eth_copy_and_sum(skb, np->rx_info[entry].skb->data, pkt_len, 0); 1458 pci_dma_sync_single_for_device(np->pci_dev, 1459 np->rx_info[entry].mapping, 1460 pkt_len, PCI_DMA_FROMDEVICE); 1461 skb_put(skb, pkt_len); 1462 } else { 1463 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1464 skb = np->rx_info[entry].skb; 1465 skb_put(skb, pkt_len); 1466 np->rx_info[entry].skb = NULL; 1467 np->rx_info[entry].mapping = 0; 1468 } 1469#ifndef final_version /* Remove after testing. */ 1470 /* You will want this info for the initial debug. */ 1471 if (debug > 5) 1472 printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:" 1473 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x.\n", 1474 skb->data[0], skb->data[1], skb->data[2], skb->data[3], 1475 skb->data[4], skb->data[5], skb->data[6], skb->data[7], 1476 skb->data[8], skb->data[9], skb->data[10], 1477 skb->data[11], skb->data[12], skb->data[13]); 1478#endif 1479 1480 skb->protocol = eth_type_trans(skb, dev); 1481#ifdef VLAN_SUPPORT 1482 if (debug > 4) 1483 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2)); 1484#endif 1485 if (le16_to_cpu(desc->status2) & 0x0100) { 1486 skb->ip_summed = CHECKSUM_UNNECESSARY; 1487 np->stats.rx_compressed++; 1488 } 1489 /* 1490 * This feature doesn't seem to be working, at least 1491 * with the two firmware versions I have. If the GFP sees 1492 * an IP fragment, it either ignores it completely, or reports 1493 * "bad checksum" on it. 1494 * 1495 * Maybe I missed something -- corrections are welcome. 1496 * Until then, the printk stays. :-) -Ion 1497 */ 1498 else if (le16_to_cpu(desc->status2) & 0x0040) { 1499 skb->ip_summed = CHECKSUM_COMPLETE; 1500 skb->csum = le16_to_cpu(desc->csum); 1501 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2)); 1502 } 1503#ifdef VLAN_SUPPORT 1504 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) { 1505 if (debug > 4) 1506 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", le16_to_cpu(desc->vlanid)); 1507 /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */ 1508 vlan_netdev_receive_skb(skb, np->vlgrp, le16_to_cpu(desc->vlanid) & VLAN_VID_MASK); 1509 } else 1510#endif /* VLAN_SUPPORT */ 1511 netdev_receive_skb(skb); 1512 dev->last_rx = jiffies; 1513 np->stats.rx_packets++; 1514 1515 next_rx: 1516 np->cur_rx++; 1517 desc->status = 0; 1518 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE; 1519 } 1520 writew(np->rx_done, np->base + CompletionQConsumerIdx); 1521 1522 out: 1523 refill_rx_ring(dev); 1524 if (debug > 5) 1525 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n", 1526 retcode, np->rx_done, desc_status); 1527 return retcode; 1528} 1529 1530 1531#ifdef HAVE_NETDEV_POLL 1532static int netdev_poll(struct net_device *dev, int *budget) 1533{ 1534 u32 intr_status; 1535 struct netdev_private *np = netdev_priv(dev); 1536 void __iomem *ioaddr = np->base; 1537 int retcode = 0, quota = dev->quota; 1538 1539 do { 1540 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear); 1541 1542 retcode = __netdev_rx(dev, "a); 1543 *budget -= (dev->quota - quota); 1544 dev->quota = quota; 1545 if (retcode) 1546 goto out; 1547 1548 intr_status = readl(ioaddr + IntrStatus); 1549 } while (intr_status & (IntrRxDone | IntrRxEmpty)); 1550 1551 netif_rx_complete(dev); 1552 intr_status = readl(ioaddr + IntrEnable); 1553 intr_status |= IntrRxDone | IntrRxEmpty; 1554 writel(intr_status, ioaddr + IntrEnable); 1555 1556 out: 1557 if (debug > 5) 1558 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n", retcode); 1559 1560 /* Restart Rx engine if stopped. */ 1561 return retcode; 1562} 1563#endif /* HAVE_NETDEV_POLL */ 1564 1565 1566static void refill_rx_ring(struct net_device *dev) 1567{ 1568 struct netdev_private *np = netdev_priv(dev); 1569 struct sk_buff *skb; 1570 int entry = -1; 1571 1572 /* Refill the Rx ring buffers. */ 1573 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { 1574 entry = np->dirty_rx % RX_RING_SIZE; 1575 if (np->rx_info[entry].skb == NULL) { 1576 skb = dev_alloc_skb(np->rx_buf_sz); 1577 np->rx_info[entry].skb = skb; 1578 if (skb == NULL) 1579 break; /* Better luck next round. */ 1580 np->rx_info[entry].mapping = 1581 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1582 skb->dev = dev; /* Mark as being used by this device. */ 1583 np->rx_ring[entry].rxaddr = 1584 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid); 1585 } 1586 if (entry == RX_RING_SIZE - 1) 1587 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing); 1588 } 1589 if (entry >= 0) 1590 writew(entry, np->base + RxDescQIdx); 1591} 1592 1593 1594static void netdev_media_change(struct net_device *dev) 1595{ 1596 struct netdev_private *np = netdev_priv(dev); 1597 void __iomem *ioaddr = np->base; 1598 u16 reg0, reg1, reg4, reg5; 1599 u32 new_tx_mode; 1600 u32 new_intr_timer_ctrl; 1601 1602 /* reset status first */ 1603 mdio_read(dev, np->phys[0], MII_BMCR); 1604 mdio_read(dev, np->phys[0], MII_BMSR); 1605 1606 reg0 = mdio_read(dev, np->phys[0], MII_BMCR); 1607 reg1 = mdio_read(dev, np->phys[0], MII_BMSR); 1608 1609 if (reg1 & BMSR_LSTATUS) { 1610 /* link is up */ 1611 if (reg0 & BMCR_ANENABLE) { 1612 /* autonegotiation is enabled */ 1613 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE); 1614 reg5 = mdio_read(dev, np->phys[0], MII_LPA); 1615 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) { 1616 np->speed100 = 1; 1617 np->mii_if.full_duplex = 1; 1618 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) { 1619 np->speed100 = 1; 1620 np->mii_if.full_duplex = 0; 1621 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) { 1622 np->speed100 = 0; 1623 np->mii_if.full_duplex = 1; 1624 } else { 1625 np->speed100 = 0; 1626 np->mii_if.full_duplex = 0; 1627 } 1628 } else { 1629 /* autonegotiation is disabled */ 1630 if (reg0 & BMCR_SPEED100) 1631 np->speed100 = 1; 1632 else 1633 np->speed100 = 0; 1634 if (reg0 & BMCR_FULLDPLX) 1635 np->mii_if.full_duplex = 1; 1636 else 1637 np->mii_if.full_duplex = 0; 1638 } 1639 netif_carrier_on(dev); 1640 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n", 1641 dev->name, 1642 np->speed100 ? "100" : "10", 1643 np->mii_if.full_duplex ? "full" : "half"); 1644 1645 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */ 1646 if (np->mii_if.full_duplex) 1647 new_tx_mode |= FullDuplex; 1648 if (np->tx_mode != new_tx_mode) { 1649 np->tx_mode = new_tx_mode; 1650 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode); 1651 udelay(1000); 1652 writel(np->tx_mode, ioaddr + TxMode); 1653 } 1654 1655 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X; 1656 if (np->speed100) 1657 new_intr_timer_ctrl |= Timer10X; 1658 if (np->intr_timer_ctrl != new_intr_timer_ctrl) { 1659 np->intr_timer_ctrl = new_intr_timer_ctrl; 1660 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl); 1661 } 1662 } else { 1663 netif_carrier_off(dev); 1664 printk(KERN_DEBUG "%s: Link is down\n", dev->name); 1665 } 1666} 1667 1668 1669static void netdev_error(struct net_device *dev, int intr_status) 1670{ 1671 struct netdev_private *np = netdev_priv(dev); 1672 1673 /* Came close to underrunning the Tx FIFO, increase threshold. */ 1674 if (intr_status & IntrTxDataLow) { 1675 if (np->tx_threshold <= PKT_BUF_SZ / 16) { 1676 writel(++np->tx_threshold, np->base + TxThreshold); 1677 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n", 1678 dev->name, np->tx_threshold * 16); 1679 } else 1680 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name); 1681 } 1682 if (intr_status & IntrRxGFPDead) { 1683 np->stats.rx_fifo_errors++; 1684 np->stats.rx_errors++; 1685 } 1686 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) { 1687 np->stats.tx_fifo_errors++; 1688 np->stats.tx_errors++; 1689 } 1690 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug) 1691 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n", 1692 dev->name, intr_status); 1693} 1694 1695 1696static struct net_device_stats *get_stats(struct net_device *dev) 1697{ 1698 struct netdev_private *np = netdev_priv(dev); 1699 void __iomem *ioaddr = np->base; 1700 1701 /* This adapter architecture needs no SMP locks. */ 1702 np->stats.tx_bytes = readl(ioaddr + 0x57010); 1703 np->stats.rx_bytes = readl(ioaddr + 0x57044); 1704 np->stats.tx_packets = readl(ioaddr + 0x57000); 1705 np->stats.tx_aborted_errors = 1706 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028); 1707 np->stats.tx_window_errors = readl(ioaddr + 0x57018); 1708 np->stats.collisions = 1709 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008); 1710 1711 /* The chip only need report frame silently dropped. */ 1712 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus); 1713 writew(0, ioaddr + RxDMAStatus); 1714 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C); 1715 np->stats.rx_frame_errors = readl(ioaddr + 0x57040); 1716 np->stats.rx_length_errors = readl(ioaddr + 0x57058); 1717 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C); 1718 1719 return &np->stats; 1720} 1721 1722 1723static void set_rx_mode(struct net_device *dev) 1724{ 1725 struct netdev_private *np = netdev_priv(dev); 1726 void __iomem *ioaddr = np->base; 1727 u32 rx_mode = MinVLANPrio; 1728 struct dev_mc_list *mclist; 1729 int i; 1730#ifdef VLAN_SUPPORT 1731 1732 rx_mode |= VlanMode; 1733 if (np->vlgrp) { 1734 int vlan_count = 0; 1735 void __iomem *filter_addr = ioaddr + HashTable + 8; 1736 for (i = 0; i < VLAN_VID_MASK; i++) { 1737 if (vlan_group_get_device(np->vlgrp, i)) { 1738 if (vlan_count >= 32) 1739 break; 1740 writew(cpu_to_be16(i), filter_addr); 1741 filter_addr += 16; 1742 vlan_count++; 1743 } 1744 } 1745 if (i == VLAN_VID_MASK) { 1746 rx_mode |= PerfectFilterVlan; 1747 while (vlan_count < 32) { 1748 writew(0, filter_addr); 1749 filter_addr += 16; 1750 vlan_count++; 1751 } 1752 } 1753 } 1754#endif /* VLAN_SUPPORT */ 1755 1756 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1757 rx_mode |= AcceptAll; 1758 } else if ((dev->mc_count > multicast_filter_limit) 1759 || (dev->flags & IFF_ALLMULTI)) { 1760 /* Too many to match, or accept all multicasts. */ 1761 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter; 1762 } else if (dev->mc_count <= 14) { 1763 /* Use the 16 element perfect filter, skip first two entries. */ 1764 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16; 1765 u16 *eaddrs; 1766 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2; 1767 i++, mclist = mclist->next) { 1768 eaddrs = (u16 *)mclist->dmi_addr; 1769 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 4; 1770 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; 1771 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 8; 1772 } 1773 eaddrs = (u16 *)dev->dev_addr; 1774 while (i++ < 16) { 1775 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; 1776 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; 1777 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; 1778 } 1779 rx_mode |= AcceptBroadcast|PerfectFilter; 1780 } else { 1781 /* Must use a multicast hash table. */ 1782 void __iomem *filter_addr; 1783 u16 *eaddrs; 1784 u16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */ 1785 1786 memset(mc_filter, 0, sizeof(mc_filter)); 1787 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; 1788 i++, mclist = mclist->next) { 1789 /* The chip uses the upper 9 CRC bits 1790 as index into the hash table */ 1791 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23; 1792 __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1]; 1793 1794 *fptr |= cpu_to_le32(1 << (bit_nr & 31)); 1795 } 1796 /* Clear the perfect filter list, skip first two entries. */ 1797 filter_addr = ioaddr + PerfFilterTable + 2 * 16; 1798 eaddrs = (u16 *)dev->dev_addr; 1799 for (i = 2; i < 16; i++) { 1800 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; 1801 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; 1802 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; 1803 } 1804 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) 1805 writew(mc_filter[i], filter_addr); 1806 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter; 1807 } 1808 writel(rx_mode, ioaddr + RxFilterMode); 1809} 1810 1811static int check_if_running(struct net_device *dev) 1812{ 1813 if (!netif_running(dev)) 1814 return -EINVAL; 1815 return 0; 1816} 1817 1818static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1819{ 1820 struct netdev_private *np = netdev_priv(dev); 1821 strcpy(info->driver, DRV_NAME); 1822 strcpy(info->version, DRV_VERSION); 1823 strcpy(info->bus_info, pci_name(np->pci_dev)); 1824} 1825 1826static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1827{ 1828 struct netdev_private *np = netdev_priv(dev); 1829 spin_lock_irq(&np->lock); 1830 mii_ethtool_gset(&np->mii_if, ecmd); 1831 spin_unlock_irq(&np->lock); 1832 return 0; 1833} 1834 1835static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1836{ 1837 struct netdev_private *np = netdev_priv(dev); 1838 int res; 1839 spin_lock_irq(&np->lock); 1840 res = mii_ethtool_sset(&np->mii_if, ecmd); 1841 spin_unlock_irq(&np->lock); 1842 check_duplex(dev); 1843 return res; 1844} 1845 1846static int nway_reset(struct net_device *dev) 1847{ 1848 struct netdev_private *np = netdev_priv(dev); 1849 return mii_nway_restart(&np->mii_if); 1850} 1851 1852static u32 get_link(struct net_device *dev) 1853{ 1854 struct netdev_private *np = netdev_priv(dev); 1855 return mii_link_ok(&np->mii_if); 1856} 1857 1858static u32 get_msglevel(struct net_device *dev) 1859{ 1860 return debug; 1861} 1862 1863static void set_msglevel(struct net_device *dev, u32 val) 1864{ 1865 debug = val; 1866} 1867 1868static const struct ethtool_ops ethtool_ops = { 1869 .begin = check_if_running, 1870 .get_drvinfo = get_drvinfo, 1871 .get_settings = get_settings, 1872 .set_settings = set_settings, 1873 .nway_reset = nway_reset, 1874 .get_link = get_link, 1875 .get_msglevel = get_msglevel, 1876 .set_msglevel = set_msglevel, 1877}; 1878 1879static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1880{ 1881 struct netdev_private *np = netdev_priv(dev); 1882 struct mii_ioctl_data *data = if_mii(rq); 1883 int rc; 1884 1885 if (!netif_running(dev)) 1886 return -EINVAL; 1887 1888 spin_lock_irq(&np->lock); 1889 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL); 1890 spin_unlock_irq(&np->lock); 1891 1892 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0])) 1893 check_duplex(dev); 1894 1895 return rc; 1896} 1897 1898static int netdev_close(struct net_device *dev) 1899{ 1900 struct netdev_private *np = netdev_priv(dev); 1901 void __iomem *ioaddr = np->base; 1902 int i; 1903 1904 netif_stop_queue(dev); 1905 1906 if (debug > 1) { 1907 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n", 1908 dev->name, (int) readl(ioaddr + IntrStatus)); 1909 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", 1910 dev->name, np->cur_tx, np->dirty_tx, 1911 np->cur_rx, np->dirty_rx); 1912 } 1913 1914 /* Disable interrupts by clearing the interrupt mask. */ 1915 writel(0, ioaddr + IntrEnable); 1916 1917 /* Stop the chip's Tx and Rx processes. */ 1918 writel(0, ioaddr + GenCtrl); 1919 readl(ioaddr + GenCtrl); 1920 1921 if (debug > 5) { 1922 printk(KERN_DEBUG" Tx ring at %#llx:\n", 1923 (long long) np->tx_ring_dma); 1924 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++) 1925 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n", 1926 i, le32_to_cpu(np->tx_ring[i].status), 1927 (long long) dma_to_cpu(np->tx_ring[i].addr), 1928 le32_to_cpu(np->tx_done_q[i].status)); 1929 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n", 1930 (long long) np->rx_ring_dma, np->rx_done_q); 1931 if (np->rx_done_q) 1932 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) { 1933 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n", 1934 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status)); 1935 } 1936 } 1937 1938 free_irq(dev->irq, dev); 1939 1940 /* Free all the skbuffs in the Rx queue. */ 1941 for (i = 0; i < RX_RING_SIZE; i++) { 1942 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */ 1943 if (np->rx_info[i].skb != NULL) { 1944 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); 1945 dev_kfree_skb(np->rx_info[i].skb); 1946 } 1947 np->rx_info[i].skb = NULL; 1948 np->rx_info[i].mapping = 0; 1949 } 1950 for (i = 0; i < TX_RING_SIZE; i++) { 1951 struct sk_buff *skb = np->tx_info[i].skb; 1952 if (skb == NULL) 1953 continue; 1954 pci_unmap_single(np->pci_dev, 1955 np->tx_info[i].mapping, 1956 skb_first_frag_len(skb), PCI_DMA_TODEVICE); 1957 np->tx_info[i].mapping = 0; 1958 dev_kfree_skb(skb); 1959 np->tx_info[i].skb = NULL; 1960 } 1961 1962 return 0; 1963} 1964 1965#ifdef CONFIG_PM 1966static int starfire_suspend(struct pci_dev *pdev, pm_message_t state) 1967{ 1968 struct net_device *dev = pci_get_drvdata(pdev); 1969 1970 if (netif_running(dev)) { 1971 netif_device_detach(dev); 1972 netdev_close(dev); 1973 } 1974 1975 pci_save_state(pdev); 1976 pci_set_power_state(pdev, pci_choose_state(pdev,state)); 1977 1978 return 0; 1979} 1980 1981static int starfire_resume(struct pci_dev *pdev) 1982{ 1983 struct net_device *dev = pci_get_drvdata(pdev); 1984 1985 pci_set_power_state(pdev, PCI_D0); 1986 pci_restore_state(pdev); 1987 1988 if (netif_running(dev)) { 1989 netdev_open(dev); 1990 netif_device_attach(dev); 1991 } 1992 1993 return 0; 1994} 1995#endif /* CONFIG_PM */ 1996 1997 1998static void __devexit starfire_remove_one (struct pci_dev *pdev) 1999{ 2000 struct net_device *dev = pci_get_drvdata(pdev); 2001 struct netdev_private *np = netdev_priv(dev); 2002 2003 BUG_ON(!dev); 2004 2005 unregister_netdev(dev); 2006 2007 if (np->queue_mem) 2008 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma); 2009 2010 2011 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */ 2012 pci_disable_device(pdev); 2013 2014 iounmap(np->base); 2015 pci_release_regions(pdev); 2016 2017 pci_set_drvdata(pdev, NULL); 2018 free_netdev(dev); /* Will also free np!! */ 2019} 2020 2021 2022static struct pci_driver starfire_driver = { 2023 .name = DRV_NAME, 2024 .probe = starfire_init_one, 2025 .remove = __devexit_p(starfire_remove_one), 2026#ifdef CONFIG_PM 2027 .suspend = starfire_suspend, 2028 .resume = starfire_resume, 2029#endif /* CONFIG_PM */ 2030 .id_table = starfire_pci_tbl, 2031}; 2032 2033 2034static int __init starfire_init (void) 2035{ 2036/* when a module, this is printed whether or not devices are found in probe */ 2037#ifdef MODULE 2038 printk(version); 2039#ifdef HAVE_NETDEV_POLL 2040 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n"); 2041#else 2042 printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n"); 2043#endif 2044#endif 2045 2046 /* we can do this test only at run-time... sigh */ 2047 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) { 2048 printk("This driver has dma_addr_t issues, please send email to maintainer\n"); 2049 return -ENODEV; 2050 } 2051 2052 return pci_register_driver(&starfire_driver); 2053} 2054 2055 2056static void __exit starfire_cleanup (void) 2057{ 2058 pci_unregister_driver (&starfire_driver); 2059} 2060 2061 2062module_init(starfire_init); 2063module_exit(starfire_cleanup); 2064 2065 2066/* 2067 * Local variables: 2068 * c-basic-offset: 8 2069 * tab-width: 8 2070 * End: 2071 */ 2072