1/* 2========================================================================= 3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x. 4 -------------------------------------------------------------------- 5 6 History: 7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>. 8 May 20 2002 - Add link status force-mode and TBI mode support. 9 2004 - Massive updates. See kernel SCM system for details. 10========================================================================= 11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes. 12 Command: 'insmod r8169 media = SET_MEDIA' 13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex. 14 15 SET_MEDIA can be: 16 _10_Half = 0x01 17 _10_Full = 0x02 18 _100_Half = 0x04 19 _100_Full = 0x08 20 _1000_Full = 0x10 21 22 2. Support TBI mode. 23========================================================================= 24VERSION 1.1 <2002/10/4> 25 26 The bit4:0 of MII register 4 is called "selector field", and have to be 27 00001b to indicate support of IEEE std 802.3 during NWay process of 28 exchanging Link Code Word (FLP). 29 30VERSION 1.2 <2002/11/30> 31 32 - Large style cleanup 33 - Use ether_crc in stock kernel (linux/crc32.h) 34 - Copy mc_filter setup code from 8139cp 35 (includes an optimization, and avoids set_bit use) 36 37VERSION 1.6LK <2004/04/14> 38 39 - Merge of Realtek's version 1.6 40 - Conversion to DMA API 41 - Suspend/resume 42 - Endianness 43 - Misc Rx/Tx bugs 44 45VERSION 2.2LK <2005/01/25> 46 47 - RX csum, TX csum/SG, TSO 48 - VLAN 49 - baby (< 7200) Jumbo frames support 50 - Merge of Realtek's version 2.2 (new phy) 51 */ 52 53#include <linux/module.h> 54#include <linux/moduleparam.h> 55#include <linux/pci.h> 56#include <linux/netdevice.h> 57#include <linux/etherdevice.h> 58#include <linux/delay.h> 59#include <linux/ethtool.h> 60#include <linux/mii.h> 61#include <linux/if_vlan.h> 62#include <linux/crc32.h> 63#include <linux/in.h> 64#include <linux/ip.h> 65#include <linux/tcp.h> 66#include <linux/init.h> 67#include <linux/dma-mapping.h> 68 69#include <asm/system.h> 70#include <asm/io.h> 71#include <asm/irq.h> 72 73#ifdef CONFIG_R8169_NAPI 74#define NAPI_SUFFIX "-NAPI" 75#else 76#define NAPI_SUFFIX "" 77#endif 78 79#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX 80#define MODULENAME "r8169" 81#define PFX MODULENAME ": " 82 83#ifdef RTL8169_DEBUG 84#define assert(expr) \ 85 if (!(expr)) { \ 86 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ 87 #expr,__FILE__,__FUNCTION__,__LINE__); \ 88 } 89#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) 90#else 91#define assert(expr) do {} while (0) 92#define dprintk(fmt, args...) do {} while (0) 93#endif /* RTL8169_DEBUG */ 94 95#define R8169_MSG_DEFAULT \ 96 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 97 98#define TX_BUFFS_AVAIL(tp) \ 99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) 100 101#ifdef CONFIG_R8169_NAPI 102#define rtl8169_rx_skb netif_receive_skb 103#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb 104#define rtl8169_rx_quota(count, quota) min(count, quota) 105#else 106#define rtl8169_rx_skb netif_rx 107#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx 108#define rtl8169_rx_quota(count, quota) count 109#endif 110 111/* media options */ 112#define MAX_UNITS 8 113static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 114static int num_media = 0; 115 116/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ 117static const int max_interrupt_work = 20; 118 119/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 120 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 121static const int multicast_filter_limit = 32; 122 123/* MAC address length */ 124#define MAC_ADDR_LEN 6 125 126#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 127#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 128#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 129#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 130#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ 131#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ 132#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 133 134#define R8169_REGS_SIZE 256 135#define R8169_NAPI_WEIGHT 64 136#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 137#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 138#define RX_BUF_SIZE 1536 /* Rx Buffer size */ 139#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 140#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 141 142#define RTL8169_TX_TIMEOUT (6*HZ) 143#define RTL8169_PHY_TIMEOUT (10*HZ) 144 145/* write/read MMIO register */ 146#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 147#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 148#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 149#define RTL_R8(reg) readb (ioaddr + (reg)) 150#define RTL_R16(reg) readw (ioaddr + (reg)) 151#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 152 153enum mac_version { 154 RTL_GIGA_MAC_VER_01 = 0x00, 155 RTL_GIGA_MAC_VER_02 = 0x01, 156 RTL_GIGA_MAC_VER_03 = 0x02, 157 RTL_GIGA_MAC_VER_04 = 0x03, 158 RTL_GIGA_MAC_VER_05 = 0x04, 159 RTL_GIGA_MAC_VER_11 = 0x0b, 160 RTL_GIGA_MAC_VER_12 = 0x0c, 161 RTL_GIGA_MAC_VER_13 = 0x0d, 162 RTL_GIGA_MAC_VER_14 = 0x0e, 163 RTL_GIGA_MAC_VER_15 = 0x0f 164}; 165 166enum phy_version { 167 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */ 168 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */ 169 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */ 170 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */ 171 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */ 172 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ 173}; 174 175#define _R(NAME,MAC,MASK) \ 176 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } 177 178static const struct { 179 const char *name; 180 u8 mac_version; 181 u32 RxConfigMask; /* Clears the bits supported by this chip */ 182} rtl_chip_info[] = { 183 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), 184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880), 185 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), 186 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), 187 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), 188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E 189 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E 190 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 191 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 192 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139 193}; 194#undef _R 195 196enum cfg_version { 197 RTL_CFG_0 = 0x00, 198 RTL_CFG_1, 199 RTL_CFG_2 200}; 201 202static const struct { 203 unsigned int region; 204 unsigned int align; 205} rtl_cfg_info[] = { 206 [RTL_CFG_0] = { 1, NET_IP_ALIGN }, 207 [RTL_CFG_1] = { 2, NET_IP_ALIGN }, 208 [RTL_CFG_2] = { 2, 8 } 209}; 210 211static struct pci_device_id rtl8169_pci_tbl[] = { 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, 214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, 215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 }, 216 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, 217 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, 218 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 }, 219 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, 220 { PCI_VENDOR_ID_LINKSYS, 0x1032, 221 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, 222 {0,}, 223}; 224 225MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 226 227static int rx_copybreak = 200; 228static int use_dac; 229static struct { 230 u32 msg_enable; 231} debug = { -1 }; 232 233enum RTL8169_registers { 234 MAC0 = 0, /* Ethernet hardware address. */ 235 MAR0 = 8, /* Multicast filter. */ 236 CounterAddrLow = 0x10, 237 CounterAddrHigh = 0x14, 238 TxDescStartAddrLow = 0x20, 239 TxDescStartAddrHigh = 0x24, 240 TxHDescStartAddrLow = 0x28, 241 TxHDescStartAddrHigh = 0x2c, 242 FLASH = 0x30, 243 ERSR = 0x36, 244 ChipCmd = 0x37, 245 TxPoll = 0x38, 246 IntrMask = 0x3C, 247 IntrStatus = 0x3E, 248 TxConfig = 0x40, 249 RxConfig = 0x44, 250 RxMissed = 0x4C, 251 Cfg9346 = 0x50, 252 Config0 = 0x51, 253 Config1 = 0x52, 254 Config2 = 0x53, 255 Config3 = 0x54, 256 Config4 = 0x55, 257 Config5 = 0x56, 258 MultiIntr = 0x5C, 259 PHYAR = 0x60, 260 TBICSR = 0x64, 261 TBI_ANAR = 0x68, 262 TBI_LPAR = 0x6A, 263 PHYstatus = 0x6C, 264 RxMaxSize = 0xDA, 265 CPlusCmd = 0xE0, 266 IntrMitigate = 0xE2, 267 RxDescAddrLow = 0xE4, 268 RxDescAddrHigh = 0xE8, 269 EarlyTxThres = 0xEC, 270 FuncEvent = 0xF0, 271 FuncEventMask = 0xF4, 272 FuncPresetState = 0xF8, 273 FuncForceEvent = 0xFC, 274}; 275 276enum RTL8169_register_content { 277 /* InterruptStatusBits */ 278 SYSErr = 0x8000, 279 PCSTimeout = 0x4000, 280 SWInt = 0x0100, 281 TxDescUnavail = 0x80, 282 RxFIFOOver = 0x40, 283 LinkChg = 0x20, 284 RxOverflow = 0x10, 285 TxErr = 0x08, 286 TxOK = 0x04, 287 RxErr = 0x02, 288 RxOK = 0x01, 289 290 /* RxStatusDesc */ 291 RxFOVF = (1 << 23), 292 RxRWT = (1 << 22), 293 RxRES = (1 << 21), 294 RxRUNT = (1 << 20), 295 RxCRC = (1 << 19), 296 297 /* ChipCmdBits */ 298 CmdReset = 0x10, 299 CmdRxEnb = 0x08, 300 CmdTxEnb = 0x04, 301 RxBufEmpty = 0x01, 302 303 /* Cfg9346Bits */ 304 Cfg9346_Lock = 0x00, 305 Cfg9346_Unlock = 0xC0, 306 307 /* rx_mode_bits */ 308 AcceptErr = 0x20, 309 AcceptRunt = 0x10, 310 AcceptBroadcast = 0x08, 311 AcceptMulticast = 0x04, 312 AcceptMyPhys = 0x02, 313 AcceptAllPhys = 0x01, 314 315 /* RxConfigBits */ 316 RxCfgFIFOShift = 13, 317 RxCfgDMAShift = 8, 318 319 /* TxConfigBits */ 320 TxInterFrameGapShift = 24, 321 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 322 323 /* Config1 register p.24 */ 324 PMEnable = (1 << 0), /* Power Management Enable */ 325 326 /* Config3 register p.25 */ 327 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 328 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 329 330 /* Config5 register p.27 */ 331 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 332 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 333 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 334 LanWake = (1 << 1), /* LanWake enable/disable */ 335 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 336 337 /* TBICSR p.28 */ 338 TBIReset = 0x80000000, 339 TBILoopback = 0x40000000, 340 TBINwEnable = 0x20000000, 341 TBINwRestart = 0x10000000, 342 TBILinkOk = 0x02000000, 343 TBINwComplete = 0x01000000, 344 345 /* CPlusCmd p.31 */ 346 RxVlan = (1 << 6), 347 RxChkSum = (1 << 5), 348 PCIDAC = (1 << 4), 349 PCIMulRW = (1 << 3), 350 351 /* rtl8169_PHYstatus */ 352 TBI_Enable = 0x80, 353 TxFlowCtrl = 0x40, 354 RxFlowCtrl = 0x20, 355 _1000bpsF = 0x10, 356 _100bps = 0x08, 357 _10bps = 0x04, 358 LinkStatus = 0x02, 359 FullDup = 0x01, 360 361 /* _MediaType */ 362 _10_Half = 0x01, 363 _10_Full = 0x02, 364 _100_Half = 0x04, 365 _100_Full = 0x08, 366 _1000_Full = 0x10, 367 368 /* _TBICSRBit */ 369 TBILinkOK = 0x02000000, 370 371 /* DumpCounterCommand */ 372 CounterDump = 0x8, 373}; 374 375enum _DescStatusBit { 376 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 377 RingEnd = (1 << 30), /* End of descriptor ring */ 378 FirstFrag = (1 << 29), /* First segment of a packet */ 379 LastFrag = (1 << 28), /* Final segment of a packet */ 380 381 /* Tx private */ 382 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ 383 MSSShift = 16, /* MSS value position */ 384 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ 385 IPCS = (1 << 18), /* Calculate IP checksum */ 386 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ 387 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ 388 TxVlanTag = (1 << 17), /* Add VLAN tag */ 389 390 /* Rx private */ 391 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 392 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ 393 394#define RxProtoUDP (PID1) 395#define RxProtoTCP (PID0) 396#define RxProtoIP (PID1 | PID0) 397#define RxProtoMask RxProtoIP 398 399 IPFail = (1 << 16), /* IP checksum failed */ 400 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 401 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 402 RxVlanTag = (1 << 16), /* VLAN tag available */ 403}; 404 405#define RsvdMask 0x3fffc000 406 407struct TxDesc { 408 u32 opts1; 409 u32 opts2; 410 u64 addr; 411}; 412 413struct RxDesc { 414 u32 opts1; 415 u32 opts2; 416 u64 addr; 417}; 418 419struct ring_info { 420 struct sk_buff *skb; 421 u32 len; 422 u8 __pad[sizeof(void *) - sizeof(u32)]; 423}; 424 425struct rtl8169_private { 426 void __iomem *mmio_addr; /* memory map physical address */ 427 struct pci_dev *pci_dev; /* Index of PCI device */ 428 struct net_device *dev; 429 struct net_device_stats stats; /* statistics of net device */ 430 spinlock_t lock; /* spin lock flag */ 431 u32 msg_enable; 432 int chipset; 433 int mac_version; 434 int phy_version; 435 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 436 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 437 u32 dirty_rx; 438 u32 dirty_tx; 439 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 440 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 441 dma_addr_t TxPhyAddr; 442 dma_addr_t RxPhyAddr; 443 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ 444 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 445 unsigned align; 446 unsigned rx_buf_sz; 447 struct timer_list timer; 448 u16 cp_cmd; 449 u16 intr_mask; 450 int phy_auto_nego_reg; 451 int phy_1000_ctrl_reg; 452#ifdef CONFIG_R8169_VLAN 453 struct vlan_group *vlgrp; 454#endif 455 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); 456 void (*get_settings)(struct net_device *, struct ethtool_cmd *); 457 void (*phy_reset_enable)(void __iomem *); 458 unsigned int (*phy_reset_pending)(void __iomem *); 459 unsigned int (*link_ok)(void __iomem *); 460 struct delayed_work task; 461 unsigned wol_enabled : 1; 462}; 463 464MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 465MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 466module_param_array(media, int, &num_media, 0); 467MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8)."); 468module_param(rx_copybreak, int, 0); 469MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); 470module_param(use_dac, int, 0); 471MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); 472module_param_named(debug, debug.msg_enable, int, 0); 473MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 474MODULE_LICENSE("GPL"); 475MODULE_VERSION(RTL8169_VERSION); 476 477static int rtl8169_open(struct net_device *dev); 478static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); 479static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); 480static int rtl8169_init_ring(struct net_device *dev); 481static void rtl8169_hw_start(struct net_device *dev); 482static int rtl8169_close(struct net_device *dev); 483static void rtl8169_set_rx_mode(struct net_device *dev); 484static void rtl8169_tx_timeout(struct net_device *dev); 485static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); 486static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, 487 void __iomem *); 488static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); 489static void rtl8169_down(struct net_device *dev); 490static void rtl8169_rx_clear(struct rtl8169_private *tp); 491 492#ifdef CONFIG_R8169_NAPI 493static int rtl8169_poll(struct net_device *dev, int *budget); 494#endif 495 496static const u16 rtl8169_intr_mask = 497 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK; 498static const u16 rtl8169_napi_event = 499 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr; 500static const unsigned int rtl8169_rx_config = 501 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 502 503static void mdio_write(void __iomem *ioaddr, int RegAddr, int value) 504{ 505 int i; 506 507 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 508 509 for (i = 20; i > 0; i--) { 510 /* Check if the RTL8169 has completed writing to the specified MII register */ 511 if (!(RTL_R32(PHYAR) & 0x80000000)) 512 break; 513 udelay(25); 514 } 515} 516 517static int mdio_read(void __iomem *ioaddr, int RegAddr) 518{ 519 int i, value = -1; 520 521 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 522 523 for (i = 20; i > 0; i--) { 524 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 525 if (RTL_R32(PHYAR) & 0x80000000) { 526 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 527 break; 528 } 529 udelay(25); 530 } 531 return value; 532} 533 534static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) 535{ 536 RTL_W16(IntrMask, 0x0000); 537 538 RTL_W16(IntrStatus, 0xffff); 539} 540 541static void rtl8169_asic_down(void __iomem *ioaddr) 542{ 543 RTL_W8(ChipCmd, 0x00); 544 rtl8169_irq_mask_and_ack(ioaddr); 545 RTL_R16(CPlusCmd); 546} 547 548static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) 549{ 550 return RTL_R32(TBICSR) & TBIReset; 551} 552 553static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) 554{ 555 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; 556} 557 558static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) 559{ 560 return RTL_R32(TBICSR) & TBILinkOk; 561} 562 563static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) 564{ 565 return RTL_R8(PHYstatus) & LinkStatus; 566} 567 568static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) 569{ 570 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); 571} 572 573static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) 574{ 575 unsigned int val; 576 577 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; 578 mdio_write(ioaddr, MII_BMCR, val & 0xffff); 579} 580 581static void rtl8169_check_link_status(struct net_device *dev, 582 struct rtl8169_private *tp, void __iomem *ioaddr) 583{ 584 unsigned long flags; 585 586 spin_lock_irqsave(&tp->lock, flags); 587 if (tp->link_ok(ioaddr)) { 588 netif_carrier_on(dev); 589 if (netif_msg_ifup(tp)) 590 printk(KERN_INFO PFX "%s: link up\n", dev->name); 591 } else { 592 if (netif_msg_ifdown(tp)) 593 printk(KERN_INFO PFX "%s: link down\n", dev->name); 594 netif_carrier_off(dev); 595 } 596 spin_unlock_irqrestore(&tp->lock, flags); 597} 598 599static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex) 600{ 601 struct { 602 u16 speed; 603 u8 duplex; 604 u8 autoneg; 605 u8 media; 606 } link_settings[] = { 607 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half }, 608 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full }, 609 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half }, 610 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full }, 611 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full }, 612 /* Make TBI happy */ 613 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff } 614 }, *p; 615 unsigned char option; 616 617 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff; 618 619 if ((option != 0xff) && !idx && netif_msg_drv(&debug)) 620 printk(KERN_WARNING PFX "media option is deprecated.\n"); 621 622 for (p = link_settings; p->media != 0xff; p++) { 623 if (p->media == option) 624 break; 625 } 626 *autoneg = p->autoneg; 627 *speed = p->speed; 628 *duplex = p->duplex; 629} 630 631static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 632{ 633 struct rtl8169_private *tp = netdev_priv(dev); 634 void __iomem *ioaddr = tp->mmio_addr; 635 u8 options; 636 637 wol->wolopts = 0; 638 639#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 640 wol->supported = WAKE_ANY; 641 642 spin_lock_irq(&tp->lock); 643 644 options = RTL_R8(Config1); 645 if (!(options & PMEnable)) 646 goto out_unlock; 647 648 options = RTL_R8(Config3); 649 if (options & LinkUp) 650 wol->wolopts |= WAKE_PHY; 651 if (options & MagicPacket) 652 wol->wolopts |= WAKE_MAGIC; 653 654 options = RTL_R8(Config5); 655 if (options & UWF) 656 wol->wolopts |= WAKE_UCAST; 657 if (options & BWF) 658 wol->wolopts |= WAKE_BCAST; 659 if (options & MWF) 660 wol->wolopts |= WAKE_MCAST; 661 662out_unlock: 663 spin_unlock_irq(&tp->lock); 664} 665 666static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 667{ 668 struct rtl8169_private *tp = netdev_priv(dev); 669 void __iomem *ioaddr = tp->mmio_addr; 670 int i; 671 static struct { 672 u32 opt; 673 u16 reg; 674 u8 mask; 675 } cfg[] = { 676 { WAKE_ANY, Config1, PMEnable }, 677 { WAKE_PHY, Config3, LinkUp }, 678 { WAKE_MAGIC, Config3, MagicPacket }, 679 { WAKE_UCAST, Config5, UWF }, 680 { WAKE_BCAST, Config5, BWF }, 681 { WAKE_MCAST, Config5, MWF }, 682 { WAKE_ANY, Config5, LanWake } 683 }; 684 685 spin_lock_irq(&tp->lock); 686 687 RTL_W8(Cfg9346, Cfg9346_Unlock); 688 689 for (i = 0; i < ARRAY_SIZE(cfg); i++) { 690 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; 691 if (wol->wolopts & cfg[i].opt) 692 options |= cfg[i].mask; 693 RTL_W8(cfg[i].reg, options); 694 } 695 696 RTL_W8(Cfg9346, Cfg9346_Lock); 697 698 tp->wol_enabled = (wol->wolopts) ? 1 : 0; 699 700 spin_unlock_irq(&tp->lock); 701 702 return 0; 703} 704 705static void rtl8169_get_drvinfo(struct net_device *dev, 706 struct ethtool_drvinfo *info) 707{ 708 struct rtl8169_private *tp = netdev_priv(dev); 709 710 strcpy(info->driver, MODULENAME); 711 strcpy(info->version, RTL8169_VERSION); 712 strcpy(info->bus_info, pci_name(tp->pci_dev)); 713} 714 715static int rtl8169_get_regs_len(struct net_device *dev) 716{ 717 return R8169_REGS_SIZE; 718} 719 720static int rtl8169_set_speed_tbi(struct net_device *dev, 721 u8 autoneg, u16 speed, u8 duplex) 722{ 723 struct rtl8169_private *tp = netdev_priv(dev); 724 void __iomem *ioaddr = tp->mmio_addr; 725 int ret = 0; 726 u32 reg; 727 728 reg = RTL_R32(TBICSR); 729 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && 730 (duplex == DUPLEX_FULL)) { 731 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); 732 } else if (autoneg == AUTONEG_ENABLE) 733 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); 734 else { 735 if (netif_msg_link(tp)) { 736 printk(KERN_WARNING "%s: " 737 "incorrect speed setting refused in TBI mode\n", 738 dev->name); 739 } 740 ret = -EOPNOTSUPP; 741 } 742 743 return ret; 744} 745 746static int rtl8169_set_speed_xmii(struct net_device *dev, 747 u8 autoneg, u16 speed, u8 duplex) 748{ 749 struct rtl8169_private *tp = netdev_priv(dev); 750 void __iomem *ioaddr = tp->mmio_addr; 751 int auto_nego, giga_ctrl; 752 753 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); 754 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 755 ADVERTISE_100HALF | ADVERTISE_100FULL); 756 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); 757 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 758 759 if (autoneg == AUTONEG_ENABLE) { 760 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | 761 ADVERTISE_100HALF | ADVERTISE_100FULL); 762 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 763 } else { 764 if (speed == SPEED_10) 765 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; 766 else if (speed == SPEED_100) 767 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; 768 else if (speed == SPEED_1000) 769 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 770 771 if (duplex == DUPLEX_HALF) 772 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); 773 774 if (duplex == DUPLEX_FULL) 775 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); 776 777 /* This tweak comes straight from Realtek's driver. */ 778 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && 779 (tp->mac_version == RTL_GIGA_MAC_VER_13)) { 780 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; 781 } 782 } 783 784 /* The 8100e/8101e do Fast Ethernet only. */ 785 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || 786 (tp->mac_version == RTL_GIGA_MAC_VER_14) || 787 (tp->mac_version == RTL_GIGA_MAC_VER_15)) { 788 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && 789 netif_msg_link(tp)) { 790 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", 791 dev->name); 792 } 793 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 794 } 795 796 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 797 798 tp->phy_auto_nego_reg = auto_nego; 799 tp->phy_1000_ctrl_reg = giga_ctrl; 800 801 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); 802 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); 803 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 804 return 0; 805} 806 807static int rtl8169_set_speed(struct net_device *dev, 808 u8 autoneg, u16 speed, u8 duplex) 809{ 810 struct rtl8169_private *tp = netdev_priv(dev); 811 int ret; 812 813 ret = tp->set_speed(dev, autoneg, speed, duplex); 814 815 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) 816 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); 817 818 return ret; 819} 820 821static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 822{ 823 struct rtl8169_private *tp = netdev_priv(dev); 824 unsigned long flags; 825 int ret; 826 827 spin_lock_irqsave(&tp->lock, flags); 828 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); 829 spin_unlock_irqrestore(&tp->lock, flags); 830 831 return ret; 832} 833 834static u32 rtl8169_get_rx_csum(struct net_device *dev) 835{ 836 struct rtl8169_private *tp = netdev_priv(dev); 837 838 return tp->cp_cmd & RxChkSum; 839} 840 841static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) 842{ 843 struct rtl8169_private *tp = netdev_priv(dev); 844 void __iomem *ioaddr = tp->mmio_addr; 845 unsigned long flags; 846 847 spin_lock_irqsave(&tp->lock, flags); 848 849 if (data) 850 tp->cp_cmd |= RxChkSum; 851 else 852 tp->cp_cmd &= ~RxChkSum; 853 854 RTL_W16(CPlusCmd, tp->cp_cmd); 855 RTL_R16(CPlusCmd); 856 857 spin_unlock_irqrestore(&tp->lock, flags); 858 859 return 0; 860} 861 862#ifdef CONFIG_R8169_VLAN 863 864static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, 865 struct sk_buff *skb) 866{ 867 return (tp->vlgrp && vlan_tx_tag_present(skb)) ? 868 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; 869} 870 871static void rtl8169_vlan_rx_register(struct net_device *dev, 872 struct vlan_group *grp) 873{ 874 struct rtl8169_private *tp = netdev_priv(dev); 875 void __iomem *ioaddr = tp->mmio_addr; 876 unsigned long flags; 877 878 spin_lock_irqsave(&tp->lock, flags); 879 tp->vlgrp = grp; 880 if (tp->vlgrp) 881 tp->cp_cmd |= RxVlan; 882 else 883 tp->cp_cmd &= ~RxVlan; 884 RTL_W16(CPlusCmd, tp->cp_cmd); 885 RTL_R16(CPlusCmd); 886 spin_unlock_irqrestore(&tp->lock, flags); 887} 888 889static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, 890 struct sk_buff *skb) 891{ 892 u32 opts2 = le32_to_cpu(desc->opts2); 893 int ret; 894 895 if (tp->vlgrp && (opts2 & RxVlanTag)) { 896 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, 897 swab16(opts2 & 0xffff)); 898 ret = 0; 899 } else 900 ret = -1; 901 desc->opts2 = 0; 902 return ret; 903} 904 905#else /* !CONFIG_R8169_VLAN */ 906 907static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, 908 struct sk_buff *skb) 909{ 910 return 0; 911} 912 913static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, 914 struct sk_buff *skb) 915{ 916 return -1; 917} 918 919#endif 920 921static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) 922{ 923 struct rtl8169_private *tp = netdev_priv(dev); 924 void __iomem *ioaddr = tp->mmio_addr; 925 u32 status; 926 927 cmd->supported = 928 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; 929 cmd->port = PORT_FIBRE; 930 cmd->transceiver = XCVR_INTERNAL; 931 932 status = RTL_R32(TBICSR); 933 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; 934 cmd->autoneg = !!(status & TBINwEnable); 935 936 cmd->speed = SPEED_1000; 937 cmd->duplex = DUPLEX_FULL; /* Always set */ 938} 939 940static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) 941{ 942 struct rtl8169_private *tp = netdev_priv(dev); 943 void __iomem *ioaddr = tp->mmio_addr; 944 u8 status; 945 946 cmd->supported = SUPPORTED_10baseT_Half | 947 SUPPORTED_10baseT_Full | 948 SUPPORTED_100baseT_Half | 949 SUPPORTED_100baseT_Full | 950 SUPPORTED_1000baseT_Full | 951 SUPPORTED_Autoneg | 952 SUPPORTED_TP; 953 954 cmd->autoneg = 1; 955 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg; 956 957 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) 958 cmd->advertising |= ADVERTISED_10baseT_Half; 959 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) 960 cmd->advertising |= ADVERTISED_10baseT_Full; 961 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF) 962 cmd->advertising |= ADVERTISED_100baseT_Half; 963 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL) 964 cmd->advertising |= ADVERTISED_100baseT_Full; 965 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) 966 cmd->advertising |= ADVERTISED_1000baseT_Full; 967 968 status = RTL_R8(PHYstatus); 969 970 if (status & _1000bpsF) 971 cmd->speed = SPEED_1000; 972 else if (status & _100bps) 973 cmd->speed = SPEED_100; 974 else if (status & _10bps) 975 cmd->speed = SPEED_10; 976 977 if (status & TxFlowCtrl) 978 cmd->advertising |= ADVERTISED_Asym_Pause; 979 if (status & RxFlowCtrl) 980 cmd->advertising |= ADVERTISED_Pause; 981 982 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ? 983 DUPLEX_FULL : DUPLEX_HALF; 984} 985 986static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 987{ 988 struct rtl8169_private *tp = netdev_priv(dev); 989 unsigned long flags; 990 991 spin_lock_irqsave(&tp->lock, flags); 992 993 tp->get_settings(dev, cmd); 994 995 spin_unlock_irqrestore(&tp->lock, flags); 996 return 0; 997} 998 999static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1000 void *p) 1001{ 1002 struct rtl8169_private *tp = netdev_priv(dev); 1003 unsigned long flags; 1004 1005 if (regs->len > R8169_REGS_SIZE) 1006 regs->len = R8169_REGS_SIZE; 1007 1008 spin_lock_irqsave(&tp->lock, flags); 1009 memcpy_fromio(p, tp->mmio_addr, regs->len); 1010 spin_unlock_irqrestore(&tp->lock, flags); 1011} 1012 1013static u32 rtl8169_get_msglevel(struct net_device *dev) 1014{ 1015 struct rtl8169_private *tp = netdev_priv(dev); 1016 1017 return tp->msg_enable; 1018} 1019 1020static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1021{ 1022 struct rtl8169_private *tp = netdev_priv(dev); 1023 1024 tp->msg_enable = value; 1025} 1026 1027static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1028 "tx_packets", 1029 "rx_packets", 1030 "tx_errors", 1031 "rx_errors", 1032 "rx_missed", 1033 "align_errors", 1034 "tx_single_collisions", 1035 "tx_multi_collisions", 1036 "unicast", 1037 "broadcast", 1038 "multicast", 1039 "tx_aborted", 1040 "tx_underrun", 1041}; 1042 1043struct rtl8169_counters { 1044 u64 tx_packets; 1045 u64 rx_packets; 1046 u64 tx_errors; 1047 u32 rx_errors; 1048 u16 rx_missed; 1049 u16 align_errors; 1050 u32 tx_one_collision; 1051 u32 tx_multi_collision; 1052 u64 rx_unicast; 1053 u64 rx_broadcast; 1054 u32 rx_multicast; 1055 u16 tx_aborted; 1056 u16 tx_underun; 1057}; 1058 1059static int rtl8169_get_stats_count(struct net_device *dev) 1060{ 1061 return ARRAY_SIZE(rtl8169_gstrings); 1062} 1063 1064static void rtl8169_get_ethtool_stats(struct net_device *dev, 1065 struct ethtool_stats *stats, u64 *data) 1066{ 1067 struct rtl8169_private *tp = netdev_priv(dev); 1068 void __iomem *ioaddr = tp->mmio_addr; 1069 struct rtl8169_counters *counters; 1070 dma_addr_t paddr; 1071 u32 cmd; 1072 1073 ASSERT_RTNL(); 1074 1075 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); 1076 if (!counters) 1077 return; 1078 1079 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); 1080 cmd = (u64)paddr & DMA_32BIT_MASK; 1081 RTL_W32(CounterAddrLow, cmd); 1082 RTL_W32(CounterAddrLow, cmd | CounterDump); 1083 1084 while (RTL_R32(CounterAddrLow) & CounterDump) { 1085 if (msleep_interruptible(1)) 1086 break; 1087 } 1088 1089 RTL_W32(CounterAddrLow, 0); 1090 RTL_W32(CounterAddrHigh, 0); 1091 1092 data[0] = le64_to_cpu(counters->tx_packets); 1093 data[1] = le64_to_cpu(counters->rx_packets); 1094 data[2] = le64_to_cpu(counters->tx_errors); 1095 data[3] = le32_to_cpu(counters->rx_errors); 1096 data[4] = le16_to_cpu(counters->rx_missed); 1097 data[5] = le16_to_cpu(counters->align_errors); 1098 data[6] = le32_to_cpu(counters->tx_one_collision); 1099 data[7] = le32_to_cpu(counters->tx_multi_collision); 1100 data[8] = le64_to_cpu(counters->rx_unicast); 1101 data[9] = le64_to_cpu(counters->rx_broadcast); 1102 data[10] = le32_to_cpu(counters->rx_multicast); 1103 data[11] = le16_to_cpu(counters->tx_aborted); 1104 data[12] = le16_to_cpu(counters->tx_underun); 1105 1106 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); 1107} 1108 1109static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1110{ 1111 switch(stringset) { 1112 case ETH_SS_STATS: 1113 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1114 break; 1115 } 1116} 1117 1118 1119static const struct ethtool_ops rtl8169_ethtool_ops = { 1120 .get_drvinfo = rtl8169_get_drvinfo, 1121 .get_regs_len = rtl8169_get_regs_len, 1122 .get_link = ethtool_op_get_link, 1123 .get_settings = rtl8169_get_settings, 1124 .set_settings = rtl8169_set_settings, 1125 .get_msglevel = rtl8169_get_msglevel, 1126 .set_msglevel = rtl8169_set_msglevel, 1127 .get_rx_csum = rtl8169_get_rx_csum, 1128 .set_rx_csum = rtl8169_set_rx_csum, 1129 .get_tx_csum = ethtool_op_get_tx_csum, 1130 .set_tx_csum = ethtool_op_set_tx_csum, 1131 .get_sg = ethtool_op_get_sg, 1132 .set_sg = ethtool_op_set_sg, 1133 .get_tso = ethtool_op_get_tso, 1134 .set_tso = ethtool_op_set_tso, 1135 .get_regs = rtl8169_get_regs, 1136 .get_wol = rtl8169_get_wol, 1137 .set_wol = rtl8169_set_wol, 1138 .get_strings = rtl8169_get_strings, 1139 .get_stats_count = rtl8169_get_stats_count, 1140 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1141 .get_perm_addr = ethtool_op_get_perm_addr, 1142}; 1143 1144static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum, 1145 int bitval) 1146{ 1147 int val; 1148 1149 val = mdio_read(ioaddr, reg); 1150 val = (bitval == 1) ? 1151 val | (bitval << bitnum) : val & ~(0x0001 << bitnum); 1152 mdio_write(ioaddr, reg, val & 0xffff); 1153} 1154 1155static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr) 1156{ 1157 const struct { 1158 u32 mask; 1159 int mac_version; 1160 } mac_info[] = { 1161 { 0x38800000, RTL_GIGA_MAC_VER_15 }, 1162 { 0x38000000, RTL_GIGA_MAC_VER_12 }, 1163 { 0x34000000, RTL_GIGA_MAC_VER_13 }, 1164 { 0x30800000, RTL_GIGA_MAC_VER_14 }, 1165 { 0x30000000, RTL_GIGA_MAC_VER_11 }, 1166 { 0x18000000, RTL_GIGA_MAC_VER_05 }, 1167 { 0x10000000, RTL_GIGA_MAC_VER_04 }, 1168 { 0x04000000, RTL_GIGA_MAC_VER_03 }, 1169 { 0x00800000, RTL_GIGA_MAC_VER_02 }, 1170 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ 1171 }, *p = mac_info; 1172 u32 reg; 1173 1174 reg = RTL_R32(TxConfig) & 0x7c800000; 1175 while ((reg & p->mask) != p->mask) 1176 p++; 1177 tp->mac_version = p->mac_version; 1178} 1179 1180static void rtl8169_print_mac_version(struct rtl8169_private *tp) 1181{ 1182 dprintk("mac_version = 0x%02x\n", tp->mac_version); 1183} 1184 1185static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr) 1186{ 1187 const struct { 1188 u16 mask; 1189 u16 set; 1190 int phy_version; 1191 } phy_info[] = { 1192 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G }, 1193 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F }, 1194 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E }, 1195 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */ 1196 }, *p = phy_info; 1197 u16 reg; 1198 1199 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff; 1200 while ((reg & p->mask) != p->set) 1201 p++; 1202 tp->phy_version = p->phy_version; 1203} 1204 1205static void rtl8169_print_phy_version(struct rtl8169_private *tp) 1206{ 1207 struct { 1208 int version; 1209 char *msg; 1210 u32 reg; 1211 } phy_print[] = { 1212 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 }, 1213 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 }, 1214 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 }, 1215 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 }, 1216 { 0, NULL, 0x0000 } 1217 }, *p; 1218 1219 for (p = phy_print; p->msg; p++) { 1220 if (tp->phy_version == p->version) { 1221 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg); 1222 return; 1223 } 1224 } 1225 dprintk("phy_version == Unknown\n"); 1226} 1227 1228static void rtl8169_hw_phy_config(struct net_device *dev) 1229{ 1230 struct rtl8169_private *tp = netdev_priv(dev); 1231 void __iomem *ioaddr = tp->mmio_addr; 1232 struct { 1233 u16 regs[5]; /* Beware of bit-sign propagation */ 1234 } phy_magic[5] = { { 1235 { 0x0000, //w 4 15 12 0 1236 0x00a1, //w 3 15 0 00a1 1237 0x0008, //w 2 15 0 0008 1238 0x1020, //w 1 15 0 1020 1239 0x1000 } },{ //w 0 15 0 1000 1240 { 0x7000, //w 4 15 12 7 1241 0xff41, //w 3 15 0 ff41 1242 0xde60, //w 2 15 0 de60 1243 0x0140, //w 1 15 0 0140 1244 0x0077 } },{ //w 0 15 0 0077 1245 { 0xa000, //w 4 15 12 a 1246 0xdf01, //w 3 15 0 df01 1247 0xdf20, //w 2 15 0 df20 1248 0xff95, //w 1 15 0 ff95 1249 0xfa00 } },{ //w 0 15 0 fa00 1250 { 0xb000, //w 4 15 12 b 1251 0xff41, //w 3 15 0 ff41 1252 0xde20, //w 2 15 0 de20 1253 0x0140, //w 1 15 0 0140 1254 0x00bb } },{ //w 0 15 0 00bb 1255 { 0xf000, //w 4 15 12 f 1256 0xdf01, //w 3 15 0 df01 1257 0xdf20, //w 2 15 0 df20 1258 0xff95, //w 1 15 0 ff95 1259 0xbf00 } //w 0 15 0 bf00 1260 } 1261 }, *p = phy_magic; 1262 int i; 1263 1264 rtl8169_print_mac_version(tp); 1265 rtl8169_print_phy_version(tp); 1266 1267 if (tp->mac_version <= RTL_GIGA_MAC_VER_01) 1268 return; 1269 if (tp->phy_version >= RTL_GIGA_PHY_VER_H) 1270 return; 1271 1272 dprintk("MAC version != 0 && PHY version == 0 or 1\n"); 1273 dprintk("Do final_reg2.cfg\n"); 1274 1275 /* Shazam ! */ 1276 1277 if (tp->mac_version == RTL_GIGA_MAC_VER_04) { 1278 mdio_write(ioaddr, 31, 0x0002); 1279 mdio_write(ioaddr, 1, 0x90d0); 1280 mdio_write(ioaddr, 31, 0x0000); 1281 return; 1282 } 1283 1284 /* phy config for RTL8169s mac_version C chip */ 1285 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1 1286 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000 1287 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7 1288 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 1289 1290 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { 1291 int val, pos = 4; 1292 1293 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); 1294 mdio_write(ioaddr, pos, val); 1295 while (--pos >= 0) 1296 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); 1297 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 1298 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 1299 } 1300 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0 1301} 1302 1303static void rtl8169_phy_timer(unsigned long __opaque) 1304{ 1305 struct net_device *dev = (struct net_device *)__opaque; 1306 struct rtl8169_private *tp = netdev_priv(dev); 1307 struct timer_list *timer = &tp->timer; 1308 void __iomem *ioaddr = tp->mmio_addr; 1309 unsigned long timeout = RTL8169_PHY_TIMEOUT; 1310 1311 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); 1312 assert(tp->phy_version < RTL_GIGA_PHY_VER_H); 1313 1314 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) 1315 return; 1316 1317 spin_lock_irq(&tp->lock); 1318 1319 if (tp->phy_reset_pending(ioaddr)) { 1320 /* 1321 * A busy loop could burn quite a few cycles on nowadays CPU. 1322 * Let's delay the execution of the timer for a few ticks. 1323 */ 1324 timeout = HZ/10; 1325 goto out_mod_timer; 1326 } 1327 1328 if (tp->link_ok(ioaddr)) 1329 goto out_unlock; 1330 1331 if (netif_msg_link(tp)) 1332 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); 1333 1334 tp->phy_reset_enable(ioaddr); 1335 1336out_mod_timer: 1337 mod_timer(timer, jiffies + timeout); 1338out_unlock: 1339 spin_unlock_irq(&tp->lock); 1340} 1341 1342static inline void rtl8169_delete_timer(struct net_device *dev) 1343{ 1344 struct rtl8169_private *tp = netdev_priv(dev); 1345 struct timer_list *timer = &tp->timer; 1346 1347 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) || 1348 (tp->phy_version >= RTL_GIGA_PHY_VER_H)) 1349 return; 1350 1351 del_timer_sync(timer); 1352} 1353 1354static inline void rtl8169_request_timer(struct net_device *dev) 1355{ 1356 struct rtl8169_private *tp = netdev_priv(dev); 1357 struct timer_list *timer = &tp->timer; 1358 1359 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) || 1360 (tp->phy_version >= RTL_GIGA_PHY_VER_H)) 1361 return; 1362 1363 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); 1364} 1365 1366#ifdef CONFIG_NET_POLL_CONTROLLER 1367/* 1368 * Polling 'interrupt' - used by things like netconsole to send skbs 1369 * without having to re-enable interrupts. It's not called while 1370 * the interrupt routine is executing. 1371 */ 1372static void rtl8169_netpoll(struct net_device *dev) 1373{ 1374 struct rtl8169_private *tp = netdev_priv(dev); 1375 struct pci_dev *pdev = tp->pci_dev; 1376 1377 disable_irq(pdev->irq); 1378 rtl8169_interrupt(pdev->irq, dev); 1379 enable_irq(pdev->irq); 1380} 1381#endif 1382 1383static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, 1384 void __iomem *ioaddr) 1385{ 1386 iounmap(ioaddr); 1387 pci_release_regions(pdev); 1388 pci_disable_device(pdev); 1389 free_netdev(dev); 1390} 1391 1392static void rtl8169_phy_reset(struct net_device *dev, 1393 struct rtl8169_private *tp) 1394{ 1395 void __iomem *ioaddr = tp->mmio_addr; 1396 int i; 1397 1398 tp->phy_reset_enable(ioaddr); 1399 for (i = 0; i < 100; i++) { 1400 if (!tp->phy_reset_pending(ioaddr)) 1401 return; 1402 msleep(1); 1403 } 1404 if (netif_msg_link(tp)) 1405 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); 1406} 1407 1408static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 1409{ 1410 void __iomem *ioaddr = tp->mmio_addr; 1411 static int board_idx = -1; 1412 u8 autoneg, duplex; 1413 u16 speed; 1414 1415 board_idx++; 1416 1417 rtl8169_hw_phy_config(dev); 1418 1419 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 1420 RTL_W8(0x82, 0x01); 1421 1422 if (tp->mac_version < RTL_GIGA_MAC_VER_03) { 1423 dprintk("Set PCI Latency=0x40\n"); 1424 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 1425 } 1426 1427 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { 1428 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 1429 RTL_W8(0x82, 0x01); 1430 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); 1431 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 1432 } 1433 1434 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex); 1435 1436 rtl8169_phy_reset(dev, tp); 1437 1438 rtl8169_set_speed(dev, autoneg, speed, duplex); 1439 1440 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) 1441 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); 1442} 1443 1444static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1445{ 1446 struct rtl8169_private *tp = netdev_priv(dev); 1447 struct mii_ioctl_data *data = if_mii(ifr); 1448 1449 if (!netif_running(dev)) 1450 return -ENODEV; 1451 1452 switch (cmd) { 1453 case SIOCGMIIPHY: 1454 data->phy_id = 32; /* Internal PHY */ 1455 return 0; 1456 1457 case SIOCGMIIREG: 1458 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); 1459 return 0; 1460 1461 case SIOCSMIIREG: 1462 if (!capable(CAP_NET_ADMIN)) 1463 return -EPERM; 1464 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); 1465 return 0; 1466 } 1467 return -EOPNOTSUPP; 1468} 1469 1470static int __devinit 1471rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1472{ 1473 const unsigned int region = rtl_cfg_info[ent->driver_data].region; 1474 struct rtl8169_private *tp; 1475 struct net_device *dev; 1476 void __iomem *ioaddr; 1477 unsigned int pm_cap; 1478 int i, rc; 1479 1480 if (netif_msg_drv(&debug)) { 1481 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", 1482 MODULENAME, RTL8169_VERSION); 1483 } 1484 1485 dev = alloc_etherdev(sizeof (*tp)); 1486 if (!dev) { 1487 if (netif_msg_drv(&debug)) 1488 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); 1489 rc = -ENOMEM; 1490 goto out; 1491 } 1492 1493 SET_MODULE_OWNER(dev); 1494 SET_NETDEV_DEV(dev, &pdev->dev); 1495 tp = netdev_priv(dev); 1496 tp->dev = dev; 1497 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 1498 1499 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 1500 rc = pci_enable_device(pdev); 1501 if (rc < 0) { 1502 if (netif_msg_probe(tp)) 1503 dev_err(&pdev->dev, "enable failure\n"); 1504 goto err_out_free_dev_1; 1505 } 1506 1507 rc = pci_set_mwi(pdev); 1508 if (rc < 0) 1509 goto err_out_disable_2; 1510 1511 /* save power state before pci_enable_device overwrites it */ 1512 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 1513 if (pm_cap) { 1514 u16 pwr_command, acpi_idle_state; 1515 1516 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command); 1517 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK; 1518 } else { 1519 if (netif_msg_probe(tp)) { 1520 dev_err(&pdev->dev, 1521 "PowerManagement capability not found.\n"); 1522 } 1523 } 1524 1525 /* make sure PCI base addr 1 is MMIO */ 1526 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { 1527 if (netif_msg_probe(tp)) { 1528 dev_err(&pdev->dev, 1529 "region #%d not an MMIO resource, aborting\n", 1530 region); 1531 } 1532 rc = -ENODEV; 1533 goto err_out_mwi_3; 1534 } 1535 1536 /* check for weird/broken PCI region reporting */ 1537 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 1538 if (netif_msg_probe(tp)) { 1539 dev_err(&pdev->dev, 1540 "Invalid PCI region size(s), aborting\n"); 1541 } 1542 rc = -ENODEV; 1543 goto err_out_mwi_3; 1544 } 1545 1546 rc = pci_request_regions(pdev, MODULENAME); 1547 if (rc < 0) { 1548 if (netif_msg_probe(tp)) 1549 dev_err(&pdev->dev, "could not request regions.\n"); 1550 goto err_out_mwi_3; 1551 } 1552 1553 tp->cp_cmd = PCIMulRW | RxChkSum; 1554 1555 if ((sizeof(dma_addr_t) > 4) && 1556 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { 1557 tp->cp_cmd |= PCIDAC; 1558 dev->features |= NETIF_F_HIGHDMA; 1559 } else { 1560 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1561 if (rc < 0) { 1562 if (netif_msg_probe(tp)) { 1563 dev_err(&pdev->dev, 1564 "DMA configuration failed.\n"); 1565 } 1566 goto err_out_free_res_4; 1567 } 1568 } 1569 1570 pci_set_master(pdev); 1571 1572 /* ioremap MMIO region */ 1573 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); 1574 if (!ioaddr) { 1575 if (netif_msg_probe(tp)) 1576 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 1577 rc = -EIO; 1578 goto err_out_free_res_4; 1579 } 1580 1581 /* Unneeded ? Don't mess with Mrs. Murphy. */ 1582 rtl8169_irq_mask_and_ack(ioaddr); 1583 1584 /* Soft reset the chip. */ 1585 RTL_W8(ChipCmd, CmdReset); 1586 1587 /* Check that the chip has finished the reset. */ 1588 for (i = 100; i > 0; i--) { 1589 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 1590 break; 1591 msleep_interruptible(1); 1592 } 1593 1594 /* Identify chip attached to board */ 1595 rtl8169_get_mac_version(tp, ioaddr); 1596 rtl8169_get_phy_version(tp, ioaddr); 1597 1598 rtl8169_print_mac_version(tp); 1599 rtl8169_print_phy_version(tp); 1600 1601 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { 1602 if (tp->mac_version == rtl_chip_info[i].mac_version) 1603 break; 1604 } 1605 if (i < 0) { 1606 /* Unknown chip: assume array element #0, original RTL-8169 */ 1607 if (netif_msg_probe(tp)) { 1608 dev_printk(KERN_DEBUG, &pdev->dev, 1609 "unknown chip version, assuming %s\n", 1610 rtl_chip_info[0].name); 1611 } 1612 i++; 1613 } 1614 tp->chipset = i; 1615 1616 RTL_W8(Cfg9346, Cfg9346_Unlock); 1617 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); 1618 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); 1619 RTL_W8(Cfg9346, Cfg9346_Lock); 1620 1621 if (RTL_R8(PHYstatus) & TBI_Enable) { 1622 tp->set_speed = rtl8169_set_speed_tbi; 1623 tp->get_settings = rtl8169_gset_tbi; 1624 tp->phy_reset_enable = rtl8169_tbi_reset_enable; 1625 tp->phy_reset_pending = rtl8169_tbi_reset_pending; 1626 tp->link_ok = rtl8169_tbi_link_ok; 1627 1628 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ 1629 } else { 1630 tp->set_speed = rtl8169_set_speed_xmii; 1631 tp->get_settings = rtl8169_gset_xmii; 1632 tp->phy_reset_enable = rtl8169_xmii_reset_enable; 1633 tp->phy_reset_pending = rtl8169_xmii_reset_pending; 1634 tp->link_ok = rtl8169_xmii_link_ok; 1635 1636 dev->do_ioctl = rtl8169_ioctl; 1637 } 1638 1639 for (i = 0; i < MAC_ADDR_LEN; i++) 1640 dev->dev_addr[i] = RTL_R8(MAC0 + i); 1641 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); 1642 1643 dev->open = rtl8169_open; 1644 dev->hard_start_xmit = rtl8169_start_xmit; 1645 dev->get_stats = rtl8169_get_stats; 1646 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); 1647 dev->stop = rtl8169_close; 1648 dev->tx_timeout = rtl8169_tx_timeout; 1649 dev->set_multicast_list = rtl8169_set_rx_mode; 1650 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; 1651 dev->irq = pdev->irq; 1652 dev->base_addr = (unsigned long) ioaddr; 1653 dev->change_mtu = rtl8169_change_mtu; 1654 1655#ifdef CONFIG_R8169_NAPI 1656 dev->poll = rtl8169_poll; 1657 dev->weight = R8169_NAPI_WEIGHT; 1658#endif 1659 1660#ifdef CONFIG_R8169_VLAN 1661 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 1662 dev->vlan_rx_register = rtl8169_vlan_rx_register; 1663#endif 1664 1665#ifdef CONFIG_NET_POLL_CONTROLLER 1666 dev->poll_controller = rtl8169_netpoll; 1667#endif 1668 1669 tp->intr_mask = 0xffff; 1670 tp->pci_dev = pdev; 1671 tp->mmio_addr = ioaddr; 1672 tp->align = rtl_cfg_info[ent->driver_data].align; 1673 1674 init_timer(&tp->timer); 1675 tp->timer.data = (unsigned long) dev; 1676 tp->timer.function = rtl8169_phy_timer; 1677 1678 spin_lock_init(&tp->lock); 1679 1680 rc = register_netdev(dev); 1681 if (rc < 0) 1682 goto err_out_unmap_5; 1683 1684 pci_set_drvdata(pdev, dev); 1685 1686 if (netif_msg_probe(tp)) { 1687 printk(KERN_INFO "%s: %s at 0x%lx, " 1688 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " 1689 "IRQ %d\n", 1690 dev->name, 1691 rtl_chip_info[tp->chipset].name, 1692 dev->base_addr, 1693 dev->dev_addr[0], dev->dev_addr[1], 1694 dev->dev_addr[2], dev->dev_addr[3], 1695 dev->dev_addr[4], dev->dev_addr[5], dev->irq); 1696 } 1697 1698 rtl8169_init_phy(dev, tp); 1699 1700out: 1701 return rc; 1702 1703err_out_unmap_5: 1704 iounmap(ioaddr); 1705err_out_free_res_4: 1706 pci_release_regions(pdev); 1707err_out_mwi_3: 1708 pci_clear_mwi(pdev); 1709err_out_disable_2: 1710 pci_disable_device(pdev); 1711err_out_free_dev_1: 1712 free_netdev(dev); 1713 goto out; 1714} 1715 1716static void __devexit 1717rtl8169_remove_one(struct pci_dev *pdev) 1718{ 1719 struct net_device *dev = pci_get_drvdata(pdev); 1720 struct rtl8169_private *tp = netdev_priv(dev); 1721 1722 assert(dev != NULL); 1723 assert(tp != NULL); 1724 1725 flush_scheduled_work(); 1726 1727 unregister_netdev(dev); 1728 rtl8169_release_board(pdev, dev, tp->mmio_addr); 1729 pci_set_drvdata(pdev, NULL); 1730} 1731 1732static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, 1733 struct net_device *dev) 1734{ 1735 unsigned int mtu = dev->mtu; 1736 1737 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; 1738} 1739 1740static int rtl8169_open(struct net_device *dev) 1741{ 1742 struct rtl8169_private *tp = netdev_priv(dev); 1743 struct pci_dev *pdev = tp->pci_dev; 1744 int retval = -ENOMEM; 1745 1746 1747 rtl8169_set_rxbufsize(tp, dev); 1748 1749 /* 1750 * Rx and Tx desscriptors needs 256 bytes alignment. 1751 * pci_alloc_consistent provides more. 1752 */ 1753 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, 1754 &tp->TxPhyAddr); 1755 if (!tp->TxDescArray) 1756 goto out; 1757 1758 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, 1759 &tp->RxPhyAddr); 1760 if (!tp->RxDescArray) 1761 goto err_free_tx_0; 1762 1763 retval = rtl8169_init_ring(dev); 1764 if (retval < 0) 1765 goto err_free_rx_1; 1766 1767 INIT_DELAYED_WORK(&tp->task, NULL); 1768 1769 smp_mb(); 1770 1771 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, 1772 dev->name, dev); 1773 if (retval < 0) 1774 goto err_release_ring_2; 1775 1776 rtl8169_hw_start(dev); 1777 1778 rtl8169_request_timer(dev); 1779 1780 rtl8169_check_link_status(dev, tp, tp->mmio_addr); 1781out: 1782 return retval; 1783 1784err_release_ring_2: 1785 rtl8169_rx_clear(tp); 1786err_free_rx_1: 1787 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, 1788 tp->RxPhyAddr); 1789err_free_tx_0: 1790 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, 1791 tp->TxPhyAddr); 1792 goto out; 1793} 1794 1795static void rtl8169_hw_reset(void __iomem *ioaddr) 1796{ 1797 /* Disable interrupts */ 1798 rtl8169_irq_mask_and_ack(ioaddr); 1799 1800 /* Reset the chipset */ 1801 RTL_W8(ChipCmd, CmdReset); 1802 1803 /* PCI commit */ 1804 RTL_R8(ChipCmd); 1805} 1806 1807static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp) 1808{ 1809 void __iomem *ioaddr = tp->mmio_addr; 1810 u32 cfg = rtl8169_rx_config; 1811 1812 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 1813 RTL_W32(RxConfig, cfg); 1814 1815 /* Set DMA burst size and Interframe Gap Time */ 1816 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 1817 (InterFrameGap << TxInterFrameGapShift)); 1818} 1819 1820static void rtl8169_hw_start(struct net_device *dev) 1821{ 1822 struct rtl8169_private *tp = netdev_priv(dev); 1823 void __iomem *ioaddr = tp->mmio_addr; 1824 struct pci_dev *pdev = tp->pci_dev; 1825 u16 cmd; 1826 u32 i; 1827 1828 /* Soft reset the chip. */ 1829 RTL_W8(ChipCmd, CmdReset); 1830 1831 /* Check that the chip has finished the reset. */ 1832 for (i = 100; i > 0; i--) { 1833 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 1834 break; 1835 msleep_interruptible(1); 1836 } 1837 1838 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { 1839 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); 1840 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); 1841 } 1842 1843 if (tp->mac_version == RTL_GIGA_MAC_VER_13) { 1844 pci_write_config_word(pdev, 0x68, 0x00); 1845 pci_write_config_word(pdev, 0x69, 0x08); 1846 } 1847 1848 /* Undocumented stuff. */ 1849 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { 1850 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */ 1851 if ((RTL_R8(Config2) & 0x07) & 0x01) 1852 RTL_W32(0x7c, 0x0007ffff); 1853 1854 RTL_W32(0x7c, 0x0007ff00); 1855 1856 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1857 cmd = cmd & 0xef; 1858 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1859 } 1860 1861 RTL_W8(Cfg9346, Cfg9346_Unlock); 1862 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || 1863 (tp->mac_version == RTL_GIGA_MAC_VER_02) || 1864 (tp->mac_version == RTL_GIGA_MAC_VER_03) || 1865 (tp->mac_version == RTL_GIGA_MAC_VER_04)) 1866 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 1867 1868 RTL_W8(EarlyTxThres, EarlyTxThld); 1869 1870 /* Low hurts. Let's disable the filtering. */ 1871 RTL_W16(RxMaxSize, 16383); 1872 1873 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || 1874 (tp->mac_version == RTL_GIGA_MAC_VER_02) || 1875 (tp->mac_version == RTL_GIGA_MAC_VER_03) || 1876 (tp->mac_version == RTL_GIGA_MAC_VER_04)) 1877 rtl8169_set_rx_tx_config_registers(tp); 1878 1879 cmd = RTL_R16(CPlusCmd); 1880 RTL_W16(CPlusCmd, cmd); 1881 1882 tp->cp_cmd |= cmd | PCIMulRW; 1883 1884 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || 1885 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { 1886 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. " 1887 "Bit-3 and bit-14 MUST be 1\n"); 1888 tp->cp_cmd |= (1 << 14); 1889 } 1890 1891 RTL_W16(CPlusCmd, tp->cp_cmd); 1892 1893 /* 1894 * Undocumented corner. Supposedly: 1895 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets 1896 */ 1897 RTL_W16(IntrMitigate, 0x0000); 1898 1899 /* 1900 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 1901 * register to be written before TxDescAddrLow to work. 1902 * Switching from MMIO to I/O access fixes the issue as well. 1903 */ 1904 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); 1905 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK)); 1906 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); 1907 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); 1908 1909 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && 1910 (tp->mac_version != RTL_GIGA_MAC_VER_02) && 1911 (tp->mac_version != RTL_GIGA_MAC_VER_03) && 1912 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { 1913 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 1914 rtl8169_set_rx_tx_config_registers(tp); 1915 } 1916 1917 RTL_W8(Cfg9346, Cfg9346_Lock); 1918 1919 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 1920 RTL_R8(IntrMask); 1921 1922 RTL_W32(RxMissed, 0); 1923 1924 rtl8169_set_rx_mode(dev); 1925 1926 /* no early-rx interrupts */ 1927 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 1928 1929 /* Enable all known interrupts by setting the interrupt mask. */ 1930 RTL_W16(IntrMask, rtl8169_intr_mask); 1931 1932 netif_start_queue(dev); 1933} 1934 1935static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 1936{ 1937 struct rtl8169_private *tp = netdev_priv(dev); 1938 int ret = 0; 1939 1940 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) 1941 return -EINVAL; 1942 1943 dev->mtu = new_mtu; 1944 1945 if (!netif_running(dev)) 1946 goto out; 1947 1948 rtl8169_down(dev); 1949 1950 rtl8169_set_rxbufsize(tp, dev); 1951 1952 ret = rtl8169_init_ring(dev); 1953 if (ret < 0) 1954 goto out; 1955 1956 netif_poll_enable(dev); 1957 1958 rtl8169_hw_start(dev); 1959 1960 rtl8169_request_timer(dev); 1961 1962out: 1963 return ret; 1964} 1965 1966static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 1967{ 1968 desc->addr = 0x0badbadbadbadbadull; 1969 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 1970} 1971 1972static void rtl8169_free_rx_skb(struct rtl8169_private *tp, 1973 struct sk_buff **sk_buff, struct RxDesc *desc) 1974{ 1975 struct pci_dev *pdev = tp->pci_dev; 1976 1977 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, 1978 PCI_DMA_FROMDEVICE); 1979 dev_kfree_skb(*sk_buff); 1980 *sk_buff = NULL; 1981 rtl8169_make_unusable_by_asic(desc); 1982} 1983 1984static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) 1985{ 1986 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 1987 1988 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); 1989} 1990 1991static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, 1992 u32 rx_buf_sz) 1993{ 1994 desc->addr = cpu_to_le64(mapping); 1995 wmb(); 1996 rtl8169_mark_to_asic(desc, rx_buf_sz); 1997} 1998 1999static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff, 2000 struct RxDesc *desc, int rx_buf_sz, 2001 unsigned int align) 2002{ 2003 struct sk_buff *skb; 2004 dma_addr_t mapping; 2005 int ret = 0; 2006 2007 skb = dev_alloc_skb(rx_buf_sz + align); 2008 if (!skb) 2009 goto err_out; 2010 2011 skb_reserve(skb, (align - 1) & (unsigned long)skb->data); 2012 *sk_buff = skb; 2013 2014 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, 2015 PCI_DMA_FROMDEVICE); 2016 2017 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); 2018 2019out: 2020 return ret; 2021 2022err_out: 2023 ret = -ENOMEM; 2024 rtl8169_make_unusable_by_asic(desc); 2025 goto out; 2026} 2027 2028static void rtl8169_rx_clear(struct rtl8169_private *tp) 2029{ 2030 int i; 2031 2032 for (i = 0; i < NUM_RX_DESC; i++) { 2033 if (tp->Rx_skbuff[i]) { 2034 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, 2035 tp->RxDescArray + i); 2036 } 2037 } 2038} 2039 2040static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, 2041 u32 start, u32 end) 2042{ 2043 u32 cur; 2044 2045 for (cur = start; end - cur > 0; cur++) { 2046 int ret, i = cur % NUM_RX_DESC; 2047 2048 if (tp->Rx_skbuff[i]) 2049 continue; 2050 2051 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i, 2052 tp->RxDescArray + i, tp->rx_buf_sz, tp->align); 2053 if (ret < 0) 2054 break; 2055 } 2056 return cur - start; 2057} 2058 2059static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 2060{ 2061 desc->opts1 |= cpu_to_le32(RingEnd); 2062} 2063 2064static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2065{ 2066 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; 2067} 2068 2069static int rtl8169_init_ring(struct net_device *dev) 2070{ 2071 struct rtl8169_private *tp = netdev_priv(dev); 2072 2073 rtl8169_init_ring_indexes(tp); 2074 2075 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); 2076 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); 2077 2078 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) 2079 goto err_out; 2080 2081 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 2082 2083 return 0; 2084 2085err_out: 2086 rtl8169_rx_clear(tp); 2087 return -ENOMEM; 2088} 2089 2090static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, 2091 struct TxDesc *desc) 2092{ 2093 unsigned int len = tx_skb->len; 2094 2095 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); 2096 desc->opts1 = 0x00; 2097 desc->opts2 = 0x00; 2098 desc->addr = 0x00; 2099 tx_skb->len = 0; 2100} 2101 2102static void rtl8169_tx_clear(struct rtl8169_private *tp) 2103{ 2104 unsigned int i; 2105 2106 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { 2107 unsigned int entry = i % NUM_TX_DESC; 2108 struct ring_info *tx_skb = tp->tx_skb + entry; 2109 unsigned int len = tx_skb->len; 2110 2111 if (len) { 2112 struct sk_buff *skb = tx_skb->skb; 2113 2114 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, 2115 tp->TxDescArray + entry); 2116 if (skb) { 2117 dev_kfree_skb(skb); 2118 tx_skb->skb = NULL; 2119 } 2120 tp->stats.tx_dropped++; 2121 } 2122 } 2123 tp->cur_tx = tp->dirty_tx = 0; 2124} 2125 2126static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) 2127{ 2128 struct rtl8169_private *tp = netdev_priv(dev); 2129 2130 PREPARE_DELAYED_WORK(&tp->task, task); 2131 schedule_delayed_work(&tp->task, 4); 2132} 2133 2134static void rtl8169_wait_for_quiescence(struct net_device *dev) 2135{ 2136 struct rtl8169_private *tp = netdev_priv(dev); 2137 void __iomem *ioaddr = tp->mmio_addr; 2138 2139 synchronize_irq(dev->irq); 2140 2141 /* Wait for any pending NAPI task to complete */ 2142 netif_poll_disable(dev); 2143 2144 rtl8169_irq_mask_and_ack(ioaddr); 2145 2146 netif_poll_enable(dev); 2147} 2148 2149static void rtl8169_reinit_task(struct work_struct *work) 2150{ 2151 struct rtl8169_private *tp = 2152 container_of(work, struct rtl8169_private, task.work); 2153 struct net_device *dev = tp->dev; 2154 int ret; 2155 2156 rtnl_lock(); 2157 2158 if (!netif_running(dev)) 2159 goto out_unlock; 2160 2161 rtl8169_wait_for_quiescence(dev); 2162 rtl8169_close(dev); 2163 2164 ret = rtl8169_open(dev); 2165 if (unlikely(ret < 0)) { 2166 if (net_ratelimit()) { 2167 struct rtl8169_private *tp = netdev_priv(dev); 2168 2169 if (netif_msg_drv(tp)) { 2170 printk(PFX KERN_ERR 2171 "%s: reinit failure (status = %d)." 2172 " Rescheduling.\n", dev->name, ret); 2173 } 2174 } 2175 rtl8169_schedule_work(dev, rtl8169_reinit_task); 2176 } 2177 2178out_unlock: 2179 rtnl_unlock(); 2180} 2181 2182static void rtl8169_reset_task(struct work_struct *work) 2183{ 2184 struct rtl8169_private *tp = 2185 container_of(work, struct rtl8169_private, task.work); 2186 struct net_device *dev = tp->dev; 2187 2188 rtnl_lock(); 2189 2190 if (!netif_running(dev)) 2191 goto out_unlock; 2192 2193 rtl8169_wait_for_quiescence(dev); 2194 2195 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr); 2196 rtl8169_tx_clear(tp); 2197 2198 if (tp->dirty_rx == tp->cur_rx) { 2199 rtl8169_init_ring_indexes(tp); 2200 rtl8169_hw_start(dev); 2201 netif_wake_queue(dev); 2202 } else { 2203 if (net_ratelimit()) { 2204 struct rtl8169_private *tp = netdev_priv(dev); 2205 2206 if (netif_msg_intr(tp)) { 2207 printk(PFX KERN_EMERG 2208 "%s: Rx buffers shortage\n", dev->name); 2209 } 2210 } 2211 rtl8169_schedule_work(dev, rtl8169_reset_task); 2212 } 2213 2214out_unlock: 2215 rtnl_unlock(); 2216} 2217 2218static void rtl8169_tx_timeout(struct net_device *dev) 2219{ 2220 struct rtl8169_private *tp = netdev_priv(dev); 2221 2222 rtl8169_hw_reset(tp->mmio_addr); 2223 2224 /* Let's wait a bit while any (async) irq lands on */ 2225 rtl8169_schedule_work(dev, rtl8169_reset_task); 2226} 2227 2228static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 2229 u32 opts1) 2230{ 2231 struct skb_shared_info *info = skb_shinfo(skb); 2232 unsigned int cur_frag, entry; 2233 struct TxDesc *txd; 2234 2235 entry = tp->cur_tx; 2236 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 2237 skb_frag_t *frag = info->frags + cur_frag; 2238 dma_addr_t mapping; 2239 u32 status, len; 2240 void *addr; 2241 2242 entry = (entry + 1) % NUM_TX_DESC; 2243 2244 txd = tp->TxDescArray + entry; 2245 len = frag->size; 2246 addr = ((void *) page_address(frag->page)) + frag->page_offset; 2247 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); 2248 2249 /* anti gcc 2.95.3 bugware (sic) */ 2250 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); 2251 2252 txd->opts1 = cpu_to_le32(status); 2253 txd->addr = cpu_to_le64(mapping); 2254 2255 tp->tx_skb[entry].len = len; 2256 } 2257 2258 if (cur_frag) { 2259 tp->tx_skb[entry].skb = skb; 2260 txd->opts1 |= cpu_to_le32(LastFrag); 2261 } 2262 2263 return cur_frag; 2264} 2265 2266static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) 2267{ 2268 if (dev->features & NETIF_F_TSO) { 2269 u32 mss = skb_shinfo(skb)->gso_size; 2270 2271 if (mss) 2272 return LargeSend | ((mss & MSSMask) << MSSShift); 2273 } 2274 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2275 const struct iphdr *ip = ip_hdr(skb); 2276 2277 if (ip->protocol == IPPROTO_TCP) 2278 return IPCS | TCPCS; 2279 else if (ip->protocol == IPPROTO_UDP) 2280 return IPCS | UDPCS; 2281 WARN_ON(1); /* we need a WARN() */ 2282 } 2283 return 0; 2284} 2285 2286static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) 2287{ 2288 struct rtl8169_private *tp = netdev_priv(dev); 2289 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; 2290 struct TxDesc *txd = tp->TxDescArray + entry; 2291 void __iomem *ioaddr = tp->mmio_addr; 2292 dma_addr_t mapping; 2293 u32 status, len; 2294 u32 opts1; 2295 int ret = NETDEV_TX_OK; 2296 2297 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { 2298 if (netif_msg_drv(tp)) { 2299 printk(KERN_ERR 2300 "%s: BUG! Tx Ring full when queue awake!\n", 2301 dev->name); 2302 } 2303 goto err_stop; 2304 } 2305 2306 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 2307 goto err_stop; 2308 2309 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); 2310 2311 frags = rtl8169_xmit_frags(tp, skb, opts1); 2312 if (frags) { 2313 len = skb_headlen(skb); 2314 opts1 |= FirstFrag; 2315 } else { 2316 len = skb->len; 2317 2318 if (unlikely(len < ETH_ZLEN)) { 2319 if (skb_padto(skb, ETH_ZLEN)) 2320 goto err_update_stats; 2321 len = ETH_ZLEN; 2322 } 2323 2324 opts1 |= FirstFrag | LastFrag; 2325 tp->tx_skb[entry].skb = skb; 2326 } 2327 2328 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); 2329 2330 tp->tx_skb[entry].len = len; 2331 txd->addr = cpu_to_le64(mapping); 2332 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); 2333 2334 wmb(); 2335 2336 /* anti gcc 2.95.3 bugware (sic) */ 2337 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); 2338 txd->opts1 = cpu_to_le32(status); 2339 2340 dev->trans_start = jiffies; 2341 2342 tp->cur_tx += frags + 1; 2343 2344 smp_wmb(); 2345 2346 RTL_W8(TxPoll, 0x40); /* set polling bit */ 2347 2348 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { 2349 netif_stop_queue(dev); 2350 smp_rmb(); 2351 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) 2352 netif_wake_queue(dev); 2353 } 2354 2355out: 2356 return ret; 2357 2358err_stop: 2359 netif_stop_queue(dev); 2360 ret = NETDEV_TX_BUSY; 2361err_update_stats: 2362 tp->stats.tx_dropped++; 2363 goto out; 2364} 2365 2366static void rtl8169_pcierr_interrupt(struct net_device *dev) 2367{ 2368 struct rtl8169_private *tp = netdev_priv(dev); 2369 struct pci_dev *pdev = tp->pci_dev; 2370 void __iomem *ioaddr = tp->mmio_addr; 2371 u16 pci_status, pci_cmd; 2372 2373 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 2374 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 2375 2376 if (netif_msg_intr(tp)) { 2377 printk(KERN_ERR 2378 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", 2379 dev->name, pci_cmd, pci_status); 2380 } 2381 2382 /* 2383 * The recovery sequence below admits a very elaborated explanation: 2384 * - it seems to work; 2385 * - I did not see what else could be done; 2386 * - it makes iop3xx happy. 2387 * 2388 * Feel free to adjust to your needs. 2389 */ 2390 if (pdev->broken_parity_status) 2391 pci_cmd &= ~PCI_COMMAND_PARITY; 2392 else 2393 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 2394 2395 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 2396 2397 pci_write_config_word(pdev, PCI_STATUS, 2398 pci_status & (PCI_STATUS_DETECTED_PARITY | 2399 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 2400 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 2401 2402 /* The infamous DAC f*ckup only happens at boot time */ 2403 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { 2404 if (netif_msg_intr(tp)) 2405 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); 2406 tp->cp_cmd &= ~PCIDAC; 2407 RTL_W16(CPlusCmd, tp->cp_cmd); 2408 dev->features &= ~NETIF_F_HIGHDMA; 2409 } 2410 2411 rtl8169_hw_reset(ioaddr); 2412 2413 rtl8169_schedule_work(dev, rtl8169_reinit_task); 2414} 2415 2416static void 2417rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp, 2418 void __iomem *ioaddr) 2419{ 2420 unsigned int dirty_tx, tx_left; 2421 2422 assert(dev != NULL); 2423 assert(tp != NULL); 2424 assert(ioaddr != NULL); 2425 2426 dirty_tx = tp->dirty_tx; 2427 smp_rmb(); 2428 tx_left = tp->cur_tx - dirty_tx; 2429 2430 while (tx_left > 0) { 2431 unsigned int entry = dirty_tx % NUM_TX_DESC; 2432 struct ring_info *tx_skb = tp->tx_skb + entry; 2433 u32 len = tx_skb->len; 2434 u32 status; 2435 2436 rmb(); 2437 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 2438 if (status & DescOwn) 2439 break; 2440 2441 tp->stats.tx_bytes += len; 2442 tp->stats.tx_packets++; 2443 2444 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); 2445 2446 if (status & LastFrag) { 2447 dev_kfree_skb_irq(tx_skb->skb); 2448 tx_skb->skb = NULL; 2449 } 2450 dirty_tx++; 2451 tx_left--; 2452 } 2453 2454 if (tp->dirty_tx != dirty_tx) { 2455 tp->dirty_tx = dirty_tx; 2456 smp_wmb(); 2457 if (netif_queue_stopped(dev) && 2458 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { 2459 netif_wake_queue(dev); 2460 } 2461 } 2462} 2463 2464static inline int rtl8169_fragmented_frame(u32 status) 2465{ 2466 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 2467} 2468 2469static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) 2470{ 2471 u32 opts1 = le32_to_cpu(desc->opts1); 2472 u32 status = opts1 & RxProtoMask; 2473 2474 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 2475 ((status == RxProtoUDP) && !(opts1 & UDPFail)) || 2476 ((status == RxProtoIP) && !(opts1 & IPFail))) 2477 skb->ip_summed = CHECKSUM_UNNECESSARY; 2478 else 2479 skb->ip_summed = CHECKSUM_NONE; 2480} 2481 2482static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size, 2483 struct RxDesc *desc, int rx_buf_sz, 2484 unsigned int align) 2485{ 2486 int ret = -1; 2487 2488 if (pkt_size < rx_copybreak) { 2489 struct sk_buff *skb; 2490 2491 skb = dev_alloc_skb(pkt_size + align); 2492 if (skb) { 2493 skb_reserve(skb, (align - 1) & (unsigned long)skb->data); 2494 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0); 2495 *sk_buff = skb; 2496 rtl8169_mark_to_asic(desc, rx_buf_sz); 2497 ret = 0; 2498 } 2499 } 2500 return ret; 2501} 2502 2503static int 2504rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp, 2505 void __iomem *ioaddr) 2506{ 2507 unsigned int cur_rx, rx_left; 2508 unsigned int delta, count; 2509 2510 assert(dev != NULL); 2511 assert(tp != NULL); 2512 assert(ioaddr != NULL); 2513 2514 cur_rx = tp->cur_rx; 2515 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; 2516 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota); 2517 2518 for (; rx_left > 0; rx_left--, cur_rx++) { 2519 unsigned int entry = cur_rx % NUM_RX_DESC; 2520 struct RxDesc *desc = tp->RxDescArray + entry; 2521 u32 status; 2522 2523 rmb(); 2524 status = le32_to_cpu(desc->opts1); 2525 2526 if (status & DescOwn) 2527 break; 2528 if (unlikely(status & RxRES)) { 2529 if (netif_msg_rx_err(tp)) { 2530 printk(KERN_INFO 2531 "%s: Rx ERROR. status = %08x\n", 2532 dev->name, status); 2533 } 2534 tp->stats.rx_errors++; 2535 if (status & (RxRWT | RxRUNT)) 2536 tp->stats.rx_length_errors++; 2537 if (status & RxCRC) 2538 tp->stats.rx_crc_errors++; 2539 if (status & RxFOVF) { 2540 rtl8169_schedule_work(dev, rtl8169_reset_task); 2541 tp->stats.rx_fifo_errors++; 2542 } 2543 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 2544 } else { 2545 struct sk_buff *skb = tp->Rx_skbuff[entry]; 2546 int pkt_size = (status & 0x00001FFF) - 4; 2547 void (*pci_action)(struct pci_dev *, dma_addr_t, 2548 size_t, int) = pci_dma_sync_single_for_device; 2549 2550 /* 2551 * The driver does not support incoming fragmented 2552 * frames. They are seen as a symptom of over-mtu 2553 * sized frames. 2554 */ 2555 if (unlikely(rtl8169_fragmented_frame(status))) { 2556 tp->stats.rx_dropped++; 2557 tp->stats.rx_length_errors++; 2558 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 2559 continue; 2560 } 2561 2562 rtl8169_rx_csum(skb, desc); 2563 2564 pci_dma_sync_single_for_cpu(tp->pci_dev, 2565 le64_to_cpu(desc->addr), tp->rx_buf_sz, 2566 PCI_DMA_FROMDEVICE); 2567 2568 if (rtl8169_try_rx_copy(&skb, pkt_size, desc, 2569 tp->rx_buf_sz, tp->align)) { 2570 pci_action = pci_unmap_single; 2571 tp->Rx_skbuff[entry] = NULL; 2572 } 2573 2574 pci_action(tp->pci_dev, le64_to_cpu(desc->addr), 2575 tp->rx_buf_sz, PCI_DMA_FROMDEVICE); 2576 2577 skb_put(skb, pkt_size); 2578 skb->protocol = eth_type_trans(skb, dev); 2579 2580 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) 2581 rtl8169_rx_skb(skb); 2582 2583 dev->last_rx = jiffies; 2584 tp->stats.rx_bytes += pkt_size; 2585 tp->stats.rx_packets++; 2586 } 2587 } 2588 2589 count = cur_rx - tp->cur_rx; 2590 tp->cur_rx = cur_rx; 2591 2592 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); 2593 if (!delta && count && netif_msg_intr(tp)) 2594 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); 2595 tp->dirty_rx += delta; 2596 2597 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) 2598 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); 2599 2600 return count; 2601} 2602 2603/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */ 2604static irqreturn_t 2605rtl8169_interrupt(int irq, void *dev_instance) 2606{ 2607 struct net_device *dev = (struct net_device *) dev_instance; 2608 struct rtl8169_private *tp = netdev_priv(dev); 2609 int boguscnt = max_interrupt_work; 2610 void __iomem *ioaddr = tp->mmio_addr; 2611 int status; 2612 int handled = 0; 2613 2614 do { 2615 status = RTL_R16(IntrStatus); 2616 2617 /* hotplug/major error/no more work/shared irq */ 2618 if ((status == 0xFFFF) || !status) 2619 break; 2620 2621 handled = 1; 2622 2623 if (unlikely(!netif_running(dev))) { 2624 rtl8169_asic_down(ioaddr); 2625 goto out; 2626 } 2627 2628 status &= tp->intr_mask; 2629 RTL_W16(IntrStatus, 2630 (status & RxFIFOOver) ? (status | RxOverflow) : status); 2631 2632 if (!(status & rtl8169_intr_mask)) 2633 break; 2634 2635 if (unlikely(status & SYSErr)) { 2636 rtl8169_pcierr_interrupt(dev); 2637 break; 2638 } 2639 2640 if (status & LinkChg) 2641 rtl8169_check_link_status(dev, tp, ioaddr); 2642 2643#ifdef CONFIG_R8169_NAPI 2644 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event); 2645 tp->intr_mask = ~rtl8169_napi_event; 2646 2647 if (likely(netif_rx_schedule_prep(dev))) 2648 __netif_rx_schedule(dev); 2649 else if (netif_msg_intr(tp)) { 2650 printk(KERN_INFO "%s: interrupt %04x taken in poll\n", 2651 dev->name, status); 2652 } 2653 break; 2654#else 2655 /* Rx interrupt */ 2656 if (status & (RxOK | RxOverflow | RxFIFOOver)) { 2657 rtl8169_rx_interrupt(dev, tp, ioaddr); 2658 } 2659 /* Tx interrupt */ 2660 if (status & (TxOK | TxErr)) 2661 rtl8169_tx_interrupt(dev, tp, ioaddr); 2662#endif 2663 2664 boguscnt--; 2665 } while (boguscnt > 0); 2666 2667 if (boguscnt <= 0) { 2668 if (netif_msg_intr(tp) && net_ratelimit() ) { 2669 printk(KERN_WARNING 2670 "%s: Too much work at interrupt!\n", dev->name); 2671 } 2672 /* Clear all interrupt sources. */ 2673 RTL_W16(IntrStatus, 0xffff); 2674 } 2675out: 2676 return IRQ_RETVAL(handled); 2677} 2678 2679#ifdef CONFIG_R8169_NAPI 2680static int rtl8169_poll(struct net_device *dev, int *budget) 2681{ 2682 unsigned int work_done, work_to_do = min(*budget, dev->quota); 2683 struct rtl8169_private *tp = netdev_priv(dev); 2684 void __iomem *ioaddr = tp->mmio_addr; 2685 2686 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr); 2687 rtl8169_tx_interrupt(dev, tp, ioaddr); 2688 2689 *budget -= work_done; 2690 dev->quota -= work_done; 2691 2692 if (work_done < work_to_do) { 2693 netif_rx_complete(dev); 2694 tp->intr_mask = 0xffff; 2695 /* 2696 * 20040426: the barrier is not strictly required but the 2697 * behavior of the irq handler could be less predictable 2698 * without it. Btw, the lack of flush for the posted pci 2699 * write is safe - FR 2700 */ 2701 smp_wmb(); 2702 RTL_W16(IntrMask, rtl8169_intr_mask); 2703 } 2704 2705 return (work_done >= work_to_do); 2706} 2707#endif 2708 2709static void rtl8169_down(struct net_device *dev) 2710{ 2711 struct rtl8169_private *tp = netdev_priv(dev); 2712 void __iomem *ioaddr = tp->mmio_addr; 2713 unsigned int poll_locked = 0; 2714 unsigned int intrmask; 2715 2716 rtl8169_delete_timer(dev); 2717 2718 netif_stop_queue(dev); 2719 2720core_down: 2721 spin_lock_irq(&tp->lock); 2722 2723 rtl8169_asic_down(ioaddr); 2724 2725 /* Update the error counts. */ 2726 tp->stats.rx_missed_errors += RTL_R32(RxMissed); 2727 RTL_W32(RxMissed, 0); 2728 2729 spin_unlock_irq(&tp->lock); 2730 2731 synchronize_irq(dev->irq); 2732 2733 if (!poll_locked) { 2734 netif_poll_disable(dev); 2735 poll_locked++; 2736 } 2737 2738 /* Give a racing hard_start_xmit a few cycles to complete. */ 2739 synchronize_sched(); 2740 2741 /* 2742 * And now for the 50k$ question: are IRQ disabled or not ? 2743 * 2744 * Two paths lead here: 2745 * 1) dev->close 2746 * -> netif_running() is available to sync the current code and the 2747 * IRQ handler. See rtl8169_interrupt for details. 2748 * 2) dev->change_mtu 2749 * -> rtl8169_poll can not be issued again and re-enable the 2750 * interruptions. Let's simply issue the IRQ down sequence again. 2751 * 2752 * No loop if hotpluged or major error (0xffff). 2753 */ 2754 intrmask = RTL_R16(IntrMask); 2755 if (intrmask && (intrmask != 0xffff)) 2756 goto core_down; 2757 2758 rtl8169_tx_clear(tp); 2759 2760 rtl8169_rx_clear(tp); 2761} 2762 2763static int rtl8169_close(struct net_device *dev) 2764{ 2765 struct rtl8169_private *tp = netdev_priv(dev); 2766 struct pci_dev *pdev = tp->pci_dev; 2767 2768 rtl8169_down(dev); 2769 2770 free_irq(dev->irq, dev); 2771 2772 netif_poll_enable(dev); 2773 2774 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, 2775 tp->RxPhyAddr); 2776 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, 2777 tp->TxPhyAddr); 2778 tp->TxDescArray = NULL; 2779 tp->RxDescArray = NULL; 2780 2781 return 0; 2782} 2783 2784static void 2785rtl8169_set_rx_mode(struct net_device *dev) 2786{ 2787 struct rtl8169_private *tp = netdev_priv(dev); 2788 void __iomem *ioaddr = tp->mmio_addr; 2789 unsigned long flags; 2790 u32 mc_filter[2]; /* Multicast hash filter */ 2791 int i, rx_mode; 2792 u32 tmp = 0; 2793 2794 if (dev->flags & IFF_PROMISC) { 2795 /* Unconditionally log net taps. */ 2796 if (netif_msg_link(tp)) { 2797 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", 2798 dev->name); 2799 } 2800 rx_mode = 2801 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2802 AcceptAllPhys; 2803 mc_filter[1] = mc_filter[0] = 0xffffffff; 2804 } else if ((dev->mc_count > multicast_filter_limit) 2805 || (dev->flags & IFF_ALLMULTI)) { 2806 /* Too many to filter perfectly -- accept all multicasts. */ 2807 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2808 mc_filter[1] = mc_filter[0] = 0xffffffff; 2809 } else { 2810 struct dev_mc_list *mclist; 2811 rx_mode = AcceptBroadcast | AcceptMyPhys; 2812 mc_filter[1] = mc_filter[0] = 0; 2813 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; 2814 i++, mclist = mclist->next) { 2815 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; 2816 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2817 rx_mode |= AcceptMulticast; 2818 } 2819 } 2820 2821 spin_lock_irqsave(&tp->lock, flags); 2822 2823 tmp = rtl8169_rx_config | rx_mode | 2824 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 2825 2826 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || 2827 (tp->mac_version == RTL_GIGA_MAC_VER_12) || 2828 (tp->mac_version == RTL_GIGA_MAC_VER_13) || 2829 (tp->mac_version == RTL_GIGA_MAC_VER_14) || 2830 (tp->mac_version == RTL_GIGA_MAC_VER_15)) { 2831 mc_filter[0] = 0xffffffff; 2832 mc_filter[1] = 0xffffffff; 2833 } 2834 2835 RTL_W32(RxConfig, tmp); 2836 RTL_W32(MAR0 + 0, mc_filter[0]); 2837 RTL_W32(MAR0 + 4, mc_filter[1]); 2838 2839 spin_unlock_irqrestore(&tp->lock, flags); 2840} 2841 2842/** 2843 * rtl8169_get_stats - Get rtl8169 read/write statistics 2844 * @dev: The Ethernet Device to get statistics for 2845 * 2846 * Get TX/RX statistics for rtl8169 2847 */ 2848static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) 2849{ 2850 struct rtl8169_private *tp = netdev_priv(dev); 2851 void __iomem *ioaddr = tp->mmio_addr; 2852 unsigned long flags; 2853 2854 if (netif_running(dev)) { 2855 spin_lock_irqsave(&tp->lock, flags); 2856 tp->stats.rx_missed_errors += RTL_R32(RxMissed); 2857 RTL_W32(RxMissed, 0); 2858 spin_unlock_irqrestore(&tp->lock, flags); 2859 } 2860 2861 return &tp->stats; 2862} 2863 2864#ifdef CONFIG_PM 2865 2866static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) 2867{ 2868 struct net_device *dev = pci_get_drvdata(pdev); 2869 struct rtl8169_private *tp = netdev_priv(dev); 2870 void __iomem *ioaddr = tp->mmio_addr; 2871 2872 if (!netif_running(dev)) 2873 goto out_pci_suspend; 2874 2875 netif_device_detach(dev); 2876 netif_stop_queue(dev); 2877 2878 spin_lock_irq(&tp->lock); 2879 2880 rtl8169_asic_down(ioaddr); 2881 2882 tp->stats.rx_missed_errors += RTL_R32(RxMissed); 2883 RTL_W32(RxMissed, 0); 2884 2885 spin_unlock_irq(&tp->lock); 2886 2887out_pci_suspend: 2888 pci_save_state(pdev); 2889 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled); 2890 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2891 2892 return 0; 2893} 2894 2895static int rtl8169_resume(struct pci_dev *pdev) 2896{ 2897 struct net_device *dev = pci_get_drvdata(pdev); 2898 2899 pci_set_power_state(pdev, PCI_D0); 2900 pci_restore_state(pdev); 2901 pci_enable_wake(pdev, PCI_D0, 0); 2902 2903 if (!netif_running(dev)) 2904 goto out; 2905 2906 netif_device_attach(dev); 2907 2908 rtl8169_schedule_work(dev, rtl8169_reset_task); 2909out: 2910 return 0; 2911} 2912 2913#endif /* CONFIG_PM */ 2914 2915static struct pci_driver rtl8169_pci_driver = { 2916 .name = MODULENAME, 2917 .id_table = rtl8169_pci_tbl, 2918 .probe = rtl8169_init_one, 2919 .remove = __devexit_p(rtl8169_remove_one), 2920#ifdef CONFIG_PM 2921 .suspend = rtl8169_suspend, 2922 .resume = rtl8169_resume, 2923#endif 2924}; 2925 2926static int __init 2927rtl8169_init_module(void) 2928{ 2929 return pci_register_driver(&rtl8169_pci_driver); 2930} 2931 2932static void __exit 2933rtl8169_cleanup_module(void) 2934{ 2935 pci_unregister_driver(&rtl8169_pci_driver); 2936} 2937 2938module_init(rtl8169_init_module); 2939module_exit(rtl8169_cleanup_module); 2940