1/* myri_sbus.c: MyriCOM MyriNET SBUS card driver. 2 * 3 * Copyright (C) 1996, 1999, 2006 David S. Miller (davem@davemloft.net) 4 */ 5 6static char version[] = 7 "myri_sbus.c:v2.0 June 23, 2006 David S. Miller (davem@davemloft.net)\n"; 8 9#include <linux/module.h> 10#include <linux/errno.h> 11#include <linux/kernel.h> 12#include <linux/types.h> 13#include <linux/fcntl.h> 14#include <linux/interrupt.h> 15#include <linux/ioport.h> 16#include <linux/in.h> 17#include <linux/slab.h> 18#include <linux/string.h> 19#include <linux/delay.h> 20#include <linux/init.h> 21#include <linux/netdevice.h> 22#include <linux/etherdevice.h> 23#include <linux/skbuff.h> 24#include <linux/bitops.h> 25 26#include <net/dst.h> 27#include <net/arp.h> 28#include <net/sock.h> 29#include <net/ipv6.h> 30 31#include <asm/system.h> 32#include <asm/io.h> 33#include <asm/dma.h> 34#include <asm/byteorder.h> 35#include <asm/idprom.h> 36#include <asm/sbus.h> 37#include <asm/openprom.h> 38#include <asm/oplib.h> 39#include <asm/auxio.h> 40#include <asm/pgtable.h> 41#include <asm/irq.h> 42 43#include "myri_sbus.h" 44#include "myri_code.h" 45 46/* #define DEBUG_DETECT */ 47/* #define DEBUG_IRQ */ 48/* #define DEBUG_TRANSMIT */ 49/* #define DEBUG_RECEIVE */ 50/* #define DEBUG_HEADER */ 51 52#ifdef DEBUG_DETECT 53#define DET(x) printk x 54#else 55#define DET(x) 56#endif 57 58#ifdef DEBUG_IRQ 59#define DIRQ(x) printk x 60#else 61#define DIRQ(x) 62#endif 63 64#ifdef DEBUG_TRANSMIT 65#define DTX(x) printk x 66#else 67#define DTX(x) 68#endif 69 70#ifdef DEBUG_RECEIVE 71#define DRX(x) printk x 72#else 73#define DRX(x) 74#endif 75 76#ifdef DEBUG_HEADER 77#define DHDR(x) printk x 78#else 79#define DHDR(x) 80#endif 81 82static void myri_reset_off(void __iomem *lp, void __iomem *cregs) 83{ 84 /* Clear IRQ mask. */ 85 sbus_writel(0, lp + LANAI_EIMASK); 86 87 /* Turn RESET function off. */ 88 sbus_writel(CONTROL_ROFF, cregs + MYRICTRL_CTRL); 89} 90 91static void myri_reset_on(void __iomem *cregs) 92{ 93 /* Enable RESET function. */ 94 sbus_writel(CONTROL_RON, cregs + MYRICTRL_CTRL); 95 96 /* Disable IRQ's. */ 97 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL); 98} 99 100static void myri_disable_irq(void __iomem *lp, void __iomem *cregs) 101{ 102 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL); 103 sbus_writel(0, lp + LANAI_EIMASK); 104 sbus_writel(ISTAT_HOST, lp + LANAI_ISTAT); 105} 106 107static void myri_enable_irq(void __iomem *lp, void __iomem *cregs) 108{ 109 sbus_writel(CONTROL_EIRQ, cregs + MYRICTRL_CTRL); 110 sbus_writel(ISTAT_HOST, lp + LANAI_EIMASK); 111} 112 113static inline void bang_the_chip(struct myri_eth *mp) 114{ 115 struct myri_shmem __iomem *shmem = mp->shmem; 116 void __iomem *cregs = mp->cregs; 117 118 sbus_writel(1, &shmem->send); 119 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL); 120} 121 122static int myri_do_handshake(struct myri_eth *mp) 123{ 124 struct myri_shmem __iomem *shmem = mp->shmem; 125 void __iomem *cregs = mp->cregs; 126 struct myri_channel __iomem *chan = &shmem->channel; 127 int tick = 0; 128 129 DET(("myri_do_handshake: ")); 130 if (sbus_readl(&chan->state) == STATE_READY) { 131 DET(("Already STATE_READY, failed.\n")); 132 return -1; /* We're hosed... */ 133 } 134 135 myri_disable_irq(mp->lregs, cregs); 136 137 while (tick++ <= 25) { 138 u32 softstate; 139 140 /* Wake it up. */ 141 DET(("shakedown, CONTROL_WON, ")); 142 sbus_writel(1, &shmem->shakedown); 143 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL); 144 145 softstate = sbus_readl(&chan->state); 146 DET(("chanstate[%08x] ", softstate)); 147 if (softstate == STATE_READY) { 148 DET(("wakeup successful, ")); 149 break; 150 } 151 152 if (softstate != STATE_WFN) { 153 DET(("not WFN setting that, ")); 154 sbus_writel(STATE_WFN, &chan->state); 155 } 156 157 udelay(20); 158 } 159 160 myri_enable_irq(mp->lregs, cregs); 161 162 if (tick > 25) { 163 DET(("25 ticks we lose, failure.\n")); 164 return -1; 165 } 166 DET(("success\n")); 167 return 0; 168} 169 170static int __devinit myri_load_lanai(struct myri_eth *mp) 171{ 172 struct net_device *dev = mp->dev; 173 struct myri_shmem __iomem *shmem = mp->shmem; 174 void __iomem *rptr; 175 int i; 176 177 myri_disable_irq(mp->lregs, mp->cregs); 178 myri_reset_on(mp->cregs); 179 180 rptr = mp->lanai; 181 for (i = 0; i < mp->eeprom.ramsz; i++) 182 sbus_writeb(0, rptr + i); 183 184 if (mp->eeprom.cpuvers >= CPUVERS_3_0) 185 sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL); 186 187 /* Load executable code. */ 188 for (i = 0; i < sizeof(lanai4_code); i++) 189 sbus_writeb(lanai4_code[i], rptr + (lanai4_code_off * 2) + i); 190 191 /* Load data segment. */ 192 for (i = 0; i < sizeof(lanai4_data); i++) 193 sbus_writeb(lanai4_data[i], rptr + (lanai4_data_off * 2) + i); 194 195 /* Set device address. */ 196 sbus_writeb(0, &shmem->addr[0]); 197 sbus_writeb(0, &shmem->addr[1]); 198 for (i = 0; i < 6; i++) 199 sbus_writeb(dev->dev_addr[i], 200 &shmem->addr[i + 2]); 201 202 /* Set SBUS bursts and interrupt mask. */ 203 sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst); 204 sbus_writel(SHMEM_IMASK_RX, &shmem->imask); 205 206 /* Release the LANAI. */ 207 myri_disable_irq(mp->lregs, mp->cregs); 208 myri_reset_off(mp->lregs, mp->cregs); 209 myri_disable_irq(mp->lregs, mp->cregs); 210 211 /* Wait for the reset to complete. */ 212 for (i = 0; i < 5000; i++) { 213 if (sbus_readl(&shmem->channel.state) != STATE_READY) 214 break; 215 else 216 udelay(10); 217 } 218 219 if (i == 5000) 220 printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n"); 221 222 i = myri_do_handshake(mp); 223 if (i) 224 printk(KERN_ERR "myricom: Handshake with LANAI failed.\n"); 225 226 if (mp->eeprom.cpuvers == CPUVERS_4_0) 227 sbus_writel(0, mp->lregs + LANAI_VERS); 228 229 return i; 230} 231 232static void myri_clean_rings(struct myri_eth *mp) 233{ 234 struct sendq __iomem *sq = mp->sq; 235 struct recvq __iomem *rq = mp->rq; 236 int i; 237 238 sbus_writel(0, &rq->tail); 239 sbus_writel(0, &rq->head); 240 for (i = 0; i < (RX_RING_SIZE+1); i++) { 241 if (mp->rx_skbs[i] != NULL) { 242 struct myri_rxd __iomem *rxd = &rq->myri_rxd[i]; 243 u32 dma_addr; 244 245 dma_addr = sbus_readl(&rxd->myri_scatters[0].addr); 246 sbus_unmap_single(mp->myri_sdev, dma_addr, RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE); 247 dev_kfree_skb(mp->rx_skbs[i]); 248 mp->rx_skbs[i] = NULL; 249 } 250 } 251 252 mp->tx_old = 0; 253 sbus_writel(0, &sq->tail); 254 sbus_writel(0, &sq->head); 255 for (i = 0; i < TX_RING_SIZE; i++) { 256 if (mp->tx_skbs[i] != NULL) { 257 struct sk_buff *skb = mp->tx_skbs[i]; 258 struct myri_txd __iomem *txd = &sq->myri_txd[i]; 259 u32 dma_addr; 260 261 dma_addr = sbus_readl(&txd->myri_gathers[0].addr); 262 sbus_unmap_single(mp->myri_sdev, dma_addr, (skb->len + 3) & ~3, SBUS_DMA_TODEVICE); 263 dev_kfree_skb(mp->tx_skbs[i]); 264 mp->tx_skbs[i] = NULL; 265 } 266 } 267} 268 269static void myri_init_rings(struct myri_eth *mp, int from_irq) 270{ 271 struct recvq __iomem *rq = mp->rq; 272 struct myri_rxd __iomem *rxd = &rq->myri_rxd[0]; 273 struct net_device *dev = mp->dev; 274 gfp_t gfp_flags = GFP_KERNEL; 275 int i; 276 277 if (from_irq || in_interrupt()) 278 gfp_flags = GFP_ATOMIC; 279 280 myri_clean_rings(mp); 281 for (i = 0; i < RX_RING_SIZE; i++) { 282 struct sk_buff *skb = myri_alloc_skb(RX_ALLOC_SIZE, gfp_flags); 283 u32 dma_addr; 284 285 if (!skb) 286 continue; 287 mp->rx_skbs[i] = skb; 288 skb->dev = dev; 289 skb_put(skb, RX_ALLOC_SIZE); 290 291 dma_addr = sbus_map_single(mp->myri_sdev, skb->data, RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE); 292 sbus_writel(dma_addr, &rxd[i].myri_scatters[0].addr); 293 sbus_writel(RX_ALLOC_SIZE, &rxd[i].myri_scatters[0].len); 294 sbus_writel(i, &rxd[i].ctx); 295 sbus_writel(1, &rxd[i].num_sg); 296 } 297 sbus_writel(0, &rq->head); 298 sbus_writel(RX_RING_SIZE, &rq->tail); 299} 300 301static int myri_init(struct myri_eth *mp, int from_irq) 302{ 303 myri_init_rings(mp, from_irq); 304 return 0; 305} 306 307static void myri_is_not_so_happy(struct myri_eth *mp) 308{ 309} 310 311#ifdef DEBUG_HEADER 312static void dump_ehdr(struct ethhdr *ehdr) 313{ 314 printk("ehdr[h_dst(%02x:%02x:%02x:%02x:%02x:%02x)" 315 "h_source(%02x:%02x:%02x:%02x:%02x:%02x)h_proto(%04x)]\n", 316 ehdr->h_dest[0], ehdr->h_dest[1], ehdr->h_dest[2], 317 ehdr->h_dest[3], ehdr->h_dest[4], ehdr->h_dest[4], 318 ehdr->h_source[0], ehdr->h_source[1], ehdr->h_source[2], 319 ehdr->h_source[3], ehdr->h_source[4], ehdr->h_source[4], 320 ehdr->h_proto); 321} 322 323static void dump_ehdr_and_myripad(unsigned char *stuff) 324{ 325 struct ethhdr *ehdr = (struct ethhdr *) (stuff + 2); 326 327 printk("pad[%02x:%02x]", stuff[0], stuff[1]); 328 printk("ehdr[h_dst(%02x:%02x:%02x:%02x:%02x:%02x)" 329 "h_source(%02x:%02x:%02x:%02x:%02x:%02x)h_proto(%04x)]\n", 330 ehdr->h_dest[0], ehdr->h_dest[1], ehdr->h_dest[2], 331 ehdr->h_dest[3], ehdr->h_dest[4], ehdr->h_dest[4], 332 ehdr->h_source[0], ehdr->h_source[1], ehdr->h_source[2], 333 ehdr->h_source[3], ehdr->h_source[4], ehdr->h_source[4], 334 ehdr->h_proto); 335} 336#endif 337 338static void myri_tx(struct myri_eth *mp, struct net_device *dev) 339{ 340 struct sendq __iomem *sq= mp->sq; 341 int entry = mp->tx_old; 342 int limit = sbus_readl(&sq->head); 343 344 DTX(("entry[%d] limit[%d] ", entry, limit)); 345 if (entry == limit) 346 return; 347 while (entry != limit) { 348 struct sk_buff *skb = mp->tx_skbs[entry]; 349 u32 dma_addr; 350 351 DTX(("SKB[%d] ", entry)); 352 dma_addr = sbus_readl(&sq->myri_txd[entry].myri_gathers[0].addr); 353 sbus_unmap_single(mp->myri_sdev, dma_addr, skb->len, SBUS_DMA_TODEVICE); 354 dev_kfree_skb(skb); 355 mp->tx_skbs[entry] = NULL; 356 mp->enet_stats.tx_packets++; 357 entry = NEXT_TX(entry); 358 } 359 mp->tx_old = entry; 360} 361 362/* Determine the packet's protocol ID. The rule here is that we 363 * assume 802.3 if the type field is short enough to be a length. 364 * This is normal practice and works for any 'now in use' protocol. 365 */ 366static __be16 myri_type_trans(struct sk_buff *skb, struct net_device *dev) 367{ 368 struct ethhdr *eth; 369 unsigned char *rawp; 370 371 skb_set_mac_header(skb, MYRI_PAD_LEN); 372 skb_pull(skb, dev->hard_header_len); 373 eth = eth_hdr(skb); 374 375#ifdef DEBUG_HEADER 376 DHDR(("myri_type_trans: ")); 377 dump_ehdr(eth); 378#endif 379 if (*eth->h_dest & 1) { 380 if (memcmp(eth->h_dest, dev->broadcast, ETH_ALEN)==0) 381 skb->pkt_type = PACKET_BROADCAST; 382 else 383 skb->pkt_type = PACKET_MULTICAST; 384 } else if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) { 385 if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) 386 skb->pkt_type = PACKET_OTHERHOST; 387 } 388 389 if (ntohs(eth->h_proto) >= 1536) 390 return eth->h_proto; 391 392 rawp = skb->data; 393 394 /* This is a magic hack to spot IPX packets. Older Novell breaks 395 * the protocol design and runs IPX over 802.3 without an 802.2 LLC 396 * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This 397 * won't work for fault tolerant netware but does for the rest. 398 */ 399 if (*(unsigned short *)rawp == 0xFFFF) 400 return htons(ETH_P_802_3); 401 402 /* Real 802.2 LLC */ 403 return htons(ETH_P_802_2); 404} 405 406static void myri_rx(struct myri_eth *mp, struct net_device *dev) 407{ 408 struct recvq __iomem *rq = mp->rq; 409 struct recvq __iomem *rqa = mp->rqack; 410 int entry = sbus_readl(&rqa->head); 411 int limit = sbus_readl(&rqa->tail); 412 int drops; 413 414 DRX(("entry[%d] limit[%d] ", entry, limit)); 415 if (entry == limit) 416 return; 417 drops = 0; 418 DRX(("\n")); 419 while (entry != limit) { 420 struct myri_rxd __iomem *rxdack = &rqa->myri_rxd[entry]; 421 u32 csum = sbus_readl(&rxdack->csum); 422 int len = sbus_readl(&rxdack->myri_scatters[0].len); 423 int index = sbus_readl(&rxdack->ctx); 424 struct myri_rxd __iomem *rxd = &rq->myri_rxd[sbus_readl(&rq->tail)]; 425 struct sk_buff *skb = mp->rx_skbs[index]; 426 427 /* Ack it. */ 428 sbus_writel(NEXT_RX(entry), &rqa->head); 429 430 /* Check for errors. */ 431 DRX(("rxd[%d]: %p len[%d] csum[%08x] ", entry, rxd, len, csum)); 432 sbus_dma_sync_single_for_cpu(mp->myri_sdev, 433 sbus_readl(&rxd->myri_scatters[0].addr), 434 RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE); 435 if (len < (ETH_HLEN + MYRI_PAD_LEN) || (skb->data[0] != MYRI_PAD_LEN)) { 436 DRX(("ERROR[")); 437 mp->enet_stats.rx_errors++; 438 if (len < (ETH_HLEN + MYRI_PAD_LEN)) { 439 DRX(("BAD_LENGTH] ")); 440 mp->enet_stats.rx_length_errors++; 441 } else { 442 DRX(("NO_PADDING] ")); 443 mp->enet_stats.rx_frame_errors++; 444 } 445 446 /* Return it to the LANAI. */ 447 drop_it: 448 drops++; 449 DRX(("DROP ")); 450 mp->enet_stats.rx_dropped++; 451 sbus_dma_sync_single_for_device(mp->myri_sdev, 452 sbus_readl(&rxd->myri_scatters[0].addr), 453 RX_ALLOC_SIZE, 454 SBUS_DMA_FROMDEVICE); 455 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len); 456 sbus_writel(index, &rxd->ctx); 457 sbus_writel(1, &rxd->num_sg); 458 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail); 459 goto next; 460 } 461 462 DRX(("len[%d] ", len)); 463 if (len > RX_COPY_THRESHOLD) { 464 struct sk_buff *new_skb; 465 u32 dma_addr; 466 467 DRX(("BIGBUFF ")); 468 new_skb = myri_alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC); 469 if (new_skb == NULL) { 470 DRX(("skb_alloc(FAILED) ")); 471 goto drop_it; 472 } 473 sbus_unmap_single(mp->myri_sdev, 474 sbus_readl(&rxd->myri_scatters[0].addr), 475 RX_ALLOC_SIZE, 476 SBUS_DMA_FROMDEVICE); 477 mp->rx_skbs[index] = new_skb; 478 new_skb->dev = dev; 479 skb_put(new_skb, RX_ALLOC_SIZE); 480 dma_addr = sbus_map_single(mp->myri_sdev, 481 new_skb->data, 482 RX_ALLOC_SIZE, 483 SBUS_DMA_FROMDEVICE); 484 sbus_writel(dma_addr, &rxd->myri_scatters[0].addr); 485 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len); 486 sbus_writel(index, &rxd->ctx); 487 sbus_writel(1, &rxd->num_sg); 488 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail); 489 490 /* Trim the original skb for the netif. */ 491 DRX(("trim(%d) ", len)); 492 skb_trim(skb, len); 493 } else { 494 struct sk_buff *copy_skb = dev_alloc_skb(len); 495 496 DRX(("SMALLBUFF ")); 497 if (copy_skb == NULL) { 498 DRX(("dev_alloc_skb(FAILED) ")); 499 goto drop_it; 500 } 501 /* DMA sync already done above. */ 502 copy_skb->dev = dev; 503 DRX(("resv_and_put ")); 504 skb_put(copy_skb, len); 505 skb_copy_from_linear_data(skb, copy_skb->data, len); 506 507 /* Reuse original ring buffer. */ 508 DRX(("reuse ")); 509 sbus_dma_sync_single_for_device(mp->myri_sdev, 510 sbus_readl(&rxd->myri_scatters[0].addr), 511 RX_ALLOC_SIZE, 512 SBUS_DMA_FROMDEVICE); 513 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len); 514 sbus_writel(index, &rxd->ctx); 515 sbus_writel(1, &rxd->num_sg); 516 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail); 517 518 skb = copy_skb; 519 } 520 521 /* Just like the happy meal we get checksums from this card. */ 522 skb->csum = csum; 523 skb->ip_summed = CHECKSUM_UNNECESSARY; 524 525 skb->protocol = myri_type_trans(skb, dev); 526 DRX(("prot[%04x] netif_rx ", skb->protocol)); 527 netif_rx(skb); 528 529 dev->last_rx = jiffies; 530 mp->enet_stats.rx_packets++; 531 mp->enet_stats.rx_bytes += len; 532 next: 533 DRX(("NEXT\n")); 534 entry = NEXT_RX(entry); 535 } 536} 537 538static irqreturn_t myri_interrupt(int irq, void *dev_id) 539{ 540 struct net_device *dev = (struct net_device *) dev_id; 541 struct myri_eth *mp = (struct myri_eth *) dev->priv; 542 void __iomem *lregs = mp->lregs; 543 struct myri_channel __iomem *chan = &mp->shmem->channel; 544 unsigned long flags; 545 u32 status; 546 int handled = 0; 547 548 spin_lock_irqsave(&mp->irq_lock, flags); 549 550 status = sbus_readl(lregs + LANAI_ISTAT); 551 DIRQ(("myri_interrupt: status[%08x] ", status)); 552 if (status & ISTAT_HOST) { 553 u32 softstate; 554 555 handled = 1; 556 DIRQ(("IRQ_DISAB ")); 557 myri_disable_irq(lregs, mp->cregs); 558 softstate = sbus_readl(&chan->state); 559 DIRQ(("state[%08x] ", softstate)); 560 if (softstate != STATE_READY) { 561 DIRQ(("myri_not_so_happy ")); 562 myri_is_not_so_happy(mp); 563 } 564 DIRQ(("\nmyri_rx: ")); 565 myri_rx(mp, dev); 566 DIRQ(("\nistat=ISTAT_HOST ")); 567 sbus_writel(ISTAT_HOST, lregs + LANAI_ISTAT); 568 DIRQ(("IRQ_ENAB ")); 569 myri_enable_irq(lregs, mp->cregs); 570 } 571 DIRQ(("\n")); 572 573 spin_unlock_irqrestore(&mp->irq_lock, flags); 574 575 return IRQ_RETVAL(handled); 576} 577 578static int myri_open(struct net_device *dev) 579{ 580 struct myri_eth *mp = (struct myri_eth *) dev->priv; 581 582 return myri_init(mp, in_interrupt()); 583} 584 585static int myri_close(struct net_device *dev) 586{ 587 struct myri_eth *mp = (struct myri_eth *) dev->priv; 588 589 myri_clean_rings(mp); 590 return 0; 591} 592 593static void myri_tx_timeout(struct net_device *dev) 594{ 595 struct myri_eth *mp = (struct myri_eth *) dev->priv; 596 597 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); 598 599 mp->enet_stats.tx_errors++; 600 myri_init(mp, 0); 601 netif_wake_queue(dev); 602} 603 604static int myri_start_xmit(struct sk_buff *skb, struct net_device *dev) 605{ 606 struct myri_eth *mp = (struct myri_eth *) dev->priv; 607 struct sendq __iomem *sq = mp->sq; 608 struct myri_txd __iomem *txd; 609 unsigned long flags; 610 unsigned int head, tail; 611 int len, entry; 612 u32 dma_addr; 613 614 DTX(("myri_start_xmit: ")); 615 616 myri_tx(mp, dev); 617 618 netif_stop_queue(dev); 619 620 /* This is just to prevent multiple PIO reads for TX_BUFFS_AVAIL. */ 621 head = sbus_readl(&sq->head); 622 tail = sbus_readl(&sq->tail); 623 624 if (!TX_BUFFS_AVAIL(head, tail)) { 625 DTX(("no buffs available, returning 1\n")); 626 return 1; 627 } 628 629 spin_lock_irqsave(&mp->irq_lock, flags); 630 631 DHDR(("xmit[skbdata(%p)]\n", skb->data)); 632#ifdef DEBUG_HEADER 633 dump_ehdr_and_myripad(((unsigned char *) skb->data)); 634#endif 635 636 len = skb->len; 637 if (len & 3) { 638 DTX(("len&3 ")); 639 len = (len + 4) & (~3); 640 } 641 642 entry = sbus_readl(&sq->tail); 643 644 txd = &sq->myri_txd[entry]; 645 mp->tx_skbs[entry] = skb; 646 647 /* Must do this before we sbus map it. */ 648 if (skb->data[MYRI_PAD_LEN] & 0x1) { 649 sbus_writew(0xffff, &txd->addr[0]); 650 sbus_writew(0xffff, &txd->addr[1]); 651 sbus_writew(0xffff, &txd->addr[2]); 652 sbus_writew(0xffff, &txd->addr[3]); 653 } else { 654 sbus_writew(0xffff, &txd->addr[0]); 655 sbus_writew((skb->data[0] << 8) | skb->data[1], &txd->addr[1]); 656 sbus_writew((skb->data[2] << 8) | skb->data[3], &txd->addr[2]); 657 sbus_writew((skb->data[4] << 8) | skb->data[5], &txd->addr[3]); 658 } 659 660 dma_addr = sbus_map_single(mp->myri_sdev, skb->data, len, SBUS_DMA_TODEVICE); 661 sbus_writel(dma_addr, &txd->myri_gathers[0].addr); 662 sbus_writel(len, &txd->myri_gathers[0].len); 663 sbus_writel(1, &txd->num_sg); 664 sbus_writel(KERNEL_CHANNEL, &txd->chan); 665 sbus_writel(len, &txd->len); 666 sbus_writel((u32)-1, &txd->csum_off); 667 sbus_writel(0, &txd->csum_field); 668 669 sbus_writel(NEXT_TX(entry), &sq->tail); 670 DTX(("BangTheChip ")); 671 bang_the_chip(mp); 672 673 DTX(("tbusy=0, returning 0\n")); 674 netif_start_queue(dev); 675 spin_unlock_irqrestore(&mp->irq_lock, flags); 676 return 0; 677} 678 679/* Create the MyriNet MAC header for an arbitrary protocol layer 680 * 681 * saddr=NULL means use device source address 682 * daddr=NULL means leave destination address (eg unresolved arp) 683 */ 684static int myri_header(struct sk_buff *skb, struct net_device *dev, unsigned short type, 685 void *daddr, void *saddr, unsigned len) 686{ 687 struct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN); 688 unsigned char *pad = (unsigned char *) skb_push(skb, MYRI_PAD_LEN); 689 690#ifdef DEBUG_HEADER 691 DHDR(("myri_header: pad[%02x,%02x] ", pad[0], pad[1])); 692 dump_ehdr(eth); 693#endif 694 695 /* Set the MyriNET padding identifier. */ 696 pad[0] = MYRI_PAD_LEN; 697 pad[1] = 0xab; 698 699 /* Set the protocol type. For a packet of type ETH_P_802_3 we put the length 700 * in here instead. It is up to the 802.2 layer to carry protocol information. 701 */ 702 if (type != ETH_P_802_3) 703 eth->h_proto = htons(type); 704 else 705 eth->h_proto = htons(len); 706 707 /* Set the source hardware address. */ 708 if (saddr) 709 memcpy(eth->h_source, saddr, dev->addr_len); 710 else 711 memcpy(eth->h_source, dev->dev_addr, dev->addr_len); 712 713 /* Anyway, the loopback-device should never use this function... */ 714 if (dev->flags & IFF_LOOPBACK) { 715 int i; 716 for (i = 0; i < dev->addr_len; i++) 717 eth->h_dest[i] = 0; 718 return(dev->hard_header_len); 719 } 720 721 if (daddr) { 722 memcpy(eth->h_dest, daddr, dev->addr_len); 723 return dev->hard_header_len; 724 } 725 return -dev->hard_header_len; 726} 727 728/* Rebuild the MyriNet MAC header. This is called after an ARP 729 * (or in future other address resolution) has completed on this 730 * sk_buff. We now let ARP fill in the other fields. 731 */ 732static int myri_rebuild_header(struct sk_buff *skb) 733{ 734 unsigned char *pad = (unsigned char *) skb->data; 735 struct ethhdr *eth = (struct ethhdr *) (pad + MYRI_PAD_LEN); 736 struct net_device *dev = skb->dev; 737 738#ifdef DEBUG_HEADER 739 DHDR(("myri_rebuild_header: pad[%02x,%02x] ", pad[0], pad[1])); 740 dump_ehdr(eth); 741#endif 742 743 /* Refill MyriNet padding identifiers, this is just being anal. */ 744 pad[0] = MYRI_PAD_LEN; 745 pad[1] = 0xab; 746 747 switch (eth->h_proto) 748 { 749#ifdef CONFIG_INET 750 case __constant_htons(ETH_P_IP): 751 return arp_find(eth->h_dest, skb); 752#endif 753 754 default: 755 printk(KERN_DEBUG 756 "%s: unable to resolve type %X addresses.\n", 757 dev->name, (int)eth->h_proto); 758 759 memcpy(eth->h_source, dev->dev_addr, dev->addr_len); 760 return 0; 761 break; 762 } 763 764 return 0; 765} 766 767int myri_header_cache(struct neighbour *neigh, struct hh_cache *hh) 768{ 769 unsigned short type = hh->hh_type; 770 unsigned char *pad; 771 struct ethhdr *eth; 772 struct net_device *dev = neigh->dev; 773 774 pad = ((unsigned char *) hh->hh_data) + 775 HH_DATA_OFF(sizeof(*eth) + MYRI_PAD_LEN); 776 eth = (struct ethhdr *) (pad + MYRI_PAD_LEN); 777 778 if (type == __constant_htons(ETH_P_802_3)) 779 return -1; 780 781 /* Refill MyriNet padding identifiers, this is just being anal. */ 782 pad[0] = MYRI_PAD_LEN; 783 pad[1] = 0xab; 784 785 eth->h_proto = type; 786 memcpy(eth->h_source, dev->dev_addr, dev->addr_len); 787 memcpy(eth->h_dest, neigh->ha, dev->addr_len); 788 hh->hh_len = 16; 789 return 0; 790} 791 792 793/* Called by Address Resolution module to notify changes in address. */ 794void myri_header_cache_update(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr) 795{ 796 memcpy(((u8*)hh->hh_data) + HH_DATA_OFF(sizeof(struct ethhdr)), 797 haddr, dev->addr_len); 798} 799 800static int myri_change_mtu(struct net_device *dev, int new_mtu) 801{ 802 if ((new_mtu < (ETH_HLEN + MYRI_PAD_LEN)) || (new_mtu > MYRINET_MTU)) 803 return -EINVAL; 804 dev->mtu = new_mtu; 805 return 0; 806} 807 808static struct net_device_stats *myri_get_stats(struct net_device *dev) 809{ return &(((struct myri_eth *)dev->priv)->enet_stats); } 810 811static void myri_set_multicast(struct net_device *dev) 812{ 813 /* Do nothing, all MyriCOM nodes transmit multicast frames 814 * as broadcast packets... 815 */ 816} 817 818static inline void set_boardid_from_idprom(struct myri_eth *mp, int num) 819{ 820 mp->eeprom.id[0] = 0; 821 mp->eeprom.id[1] = idprom->id_machtype; 822 mp->eeprom.id[2] = (idprom->id_sernum >> 16) & 0xff; 823 mp->eeprom.id[3] = (idprom->id_sernum >> 8) & 0xff; 824 mp->eeprom.id[4] = (idprom->id_sernum >> 0) & 0xff; 825 mp->eeprom.id[5] = num; 826} 827 828static inline void determine_reg_space_size(struct myri_eth *mp) 829{ 830 switch(mp->eeprom.cpuvers) { 831 case CPUVERS_2_3: 832 case CPUVERS_3_0: 833 case CPUVERS_3_1: 834 case CPUVERS_3_2: 835 mp->reg_size = (3 * 128 * 1024) + 4096; 836 break; 837 838 case CPUVERS_4_0: 839 case CPUVERS_4_1: 840 mp->reg_size = ((4096<<1) + mp->eeprom.ramsz); 841 break; 842 843 case CPUVERS_4_2: 844 case CPUVERS_5_0: 845 default: 846 printk("myricom: AIEEE weird cpu version %04x assuming pre4.0\n", 847 mp->eeprom.cpuvers); 848 mp->reg_size = (3 * 128 * 1024) + 4096; 849 }; 850} 851 852#ifdef DEBUG_DETECT 853static void dump_eeprom(struct myri_eth *mp) 854{ 855 printk("EEPROM: clockval[%08x] cpuvers[%04x] " 856 "id[%02x,%02x,%02x,%02x,%02x,%02x]\n", 857 mp->eeprom.cval, mp->eeprom.cpuvers, 858 mp->eeprom.id[0], mp->eeprom.id[1], mp->eeprom.id[2], 859 mp->eeprom.id[3], mp->eeprom.id[4], mp->eeprom.id[5]); 860 printk("EEPROM: ramsz[%08x]\n", mp->eeprom.ramsz); 861 printk("EEPROM: fvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", 862 mp->eeprom.fvers[0], mp->eeprom.fvers[1], mp->eeprom.fvers[2], 863 mp->eeprom.fvers[3], mp->eeprom.fvers[4], mp->eeprom.fvers[5], 864 mp->eeprom.fvers[6], mp->eeprom.fvers[7]); 865 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", 866 mp->eeprom.fvers[8], mp->eeprom.fvers[9], mp->eeprom.fvers[10], 867 mp->eeprom.fvers[11], mp->eeprom.fvers[12], mp->eeprom.fvers[13], 868 mp->eeprom.fvers[14], mp->eeprom.fvers[15]); 869 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", 870 mp->eeprom.fvers[16], mp->eeprom.fvers[17], mp->eeprom.fvers[18], 871 mp->eeprom.fvers[19], mp->eeprom.fvers[20], mp->eeprom.fvers[21], 872 mp->eeprom.fvers[22], mp->eeprom.fvers[23]); 873 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n", 874 mp->eeprom.fvers[24], mp->eeprom.fvers[25], mp->eeprom.fvers[26], 875 mp->eeprom.fvers[27], mp->eeprom.fvers[28], mp->eeprom.fvers[29], 876 mp->eeprom.fvers[30], mp->eeprom.fvers[31]); 877 printk("EEPROM: mvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", 878 mp->eeprom.mvers[0], mp->eeprom.mvers[1], mp->eeprom.mvers[2], 879 mp->eeprom.mvers[3], mp->eeprom.mvers[4], mp->eeprom.mvers[5], 880 mp->eeprom.mvers[6], mp->eeprom.mvers[7]); 881 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n", 882 mp->eeprom.mvers[8], mp->eeprom.mvers[9], mp->eeprom.mvers[10], 883 mp->eeprom.mvers[11], mp->eeprom.mvers[12], mp->eeprom.mvers[13], 884 mp->eeprom.mvers[14], mp->eeprom.mvers[15]); 885 printk("EEPROM: dlval[%04x] brd_type[%04x] bus_type[%04x] prod_code[%04x]\n", 886 mp->eeprom.dlval, mp->eeprom.brd_type, mp->eeprom.bus_type, 887 mp->eeprom.prod_code); 888 printk("EEPROM: serial_num[%08x]\n", mp->eeprom.serial_num); 889} 890#endif 891 892static int __devinit myri_ether_init(struct sbus_dev *sdev) 893{ 894 static int num; 895 static unsigned version_printed; 896 struct net_device *dev; 897 struct myri_eth *mp; 898 unsigned char prop_buf[32]; 899 int i; 900 901 DET(("myri_ether_init(%p,%d):\n", sdev, num)); 902 dev = alloc_etherdev(sizeof(struct myri_eth)); 903 904 if (!dev) 905 return -ENOMEM; 906 907 if (version_printed++ == 0) 908 printk(version); 909 910 SET_MODULE_OWNER(dev); 911 SET_NETDEV_DEV(dev, &sdev->ofdev.dev); 912 913 mp = (struct myri_eth *) dev->priv; 914 spin_lock_init(&mp->irq_lock); 915 mp->myri_sdev = sdev; 916 917 /* Clean out skb arrays. */ 918 for (i = 0; i < (RX_RING_SIZE + 1); i++) 919 mp->rx_skbs[i] = NULL; 920 921 for (i = 0; i < TX_RING_SIZE; i++) 922 mp->tx_skbs[i] = NULL; 923 924 /* First check for EEPROM information. */ 925 i = prom_getproperty(sdev->prom_node, "myrinet-eeprom-info", 926 (char *)&mp->eeprom, sizeof(struct myri_eeprom)); 927 DET(("prom_getprop(myrinet-eeprom-info) returns %d\n", i)); 928 if (i == 0 || i == -1) { 929 /* No eeprom property, must cook up the values ourselves. */ 930 DET(("No EEPROM: ")); 931 mp->eeprom.bus_type = BUS_TYPE_SBUS; 932 mp->eeprom.cpuvers = prom_getintdefault(sdev->prom_node,"cpu_version",0); 933 mp->eeprom.cval = prom_getintdefault(sdev->prom_node,"clock_value",0); 934 mp->eeprom.ramsz = prom_getintdefault(sdev->prom_node,"sram_size",0); 935 DET(("cpuvers[%d] cval[%d] ramsz[%d]\n", mp->eeprom.cpuvers, 936 mp->eeprom.cval, mp->eeprom.ramsz)); 937 if (mp->eeprom.cpuvers == 0) { 938 DET(("EEPROM: cpuvers was zero, setting to %04x\n",CPUVERS_2_3)); 939 mp->eeprom.cpuvers = CPUVERS_2_3; 940 } 941 if (mp->eeprom.cpuvers < CPUVERS_3_0) { 942 DET(("EEPROM: cpuvers < CPUVERS_3_0, clockval set to zero.\n")); 943 mp->eeprom.cval = 0; 944 } 945 if (mp->eeprom.ramsz == 0) { 946 DET(("EEPROM: ramsz == 0, setting to 128k\n")); 947 mp->eeprom.ramsz = (128 * 1024); 948 } 949 i = prom_getproperty(sdev->prom_node, "myrinet-board-id", 950 &prop_buf[0], 10); 951 DET(("EEPROM: prom_getprop(myrinet-board-id) returns %d\n", i)); 952 if ((i != 0) && (i != -1)) 953 memcpy(&mp->eeprom.id[0], &prop_buf[0], 6); 954 else 955 set_boardid_from_idprom(mp, num); 956 i = prom_getproperty(sdev->prom_node, "fpga_version", 957 &mp->eeprom.fvers[0], 32); 958 DET(("EEPROM: prom_getprop(fpga_version) returns %d\n", i)); 959 if (i == 0 || i == -1) 960 memset(&mp->eeprom.fvers[0], 0, 32); 961 962 if (mp->eeprom.cpuvers == CPUVERS_4_1) { 963 DET(("EEPROM: cpuvers CPUVERS_4_1, ")); 964 if (mp->eeprom.ramsz == (128 * 1024)) { 965 DET(("ramsize 128k, setting to 256k, ")); 966 mp->eeprom.ramsz = (256 * 1024); 967 } 968 if ((mp->eeprom.cval==0x40414041)||(mp->eeprom.cval==0x90449044)){ 969 DET(("changing cval from %08x to %08x ", 970 mp->eeprom.cval, 0x50e450e4)); 971 mp->eeprom.cval = 0x50e450e4; 972 } 973 DET(("\n")); 974 } 975 } 976#ifdef DEBUG_DETECT 977 dump_eeprom(mp); 978#endif 979 980 for (i = 0; i < 6; i++) 981 dev->dev_addr[i] = mp->eeprom.id[i]; 982 983 determine_reg_space_size(mp); 984 985 /* Map in the MyriCOM register/localram set. */ 986 if (mp->eeprom.cpuvers < CPUVERS_4_0) { 987 DET(("Mapping regs for cpuvers < CPUVERS_4_0\n")); 988 mp->regs = sbus_ioremap(&sdev->resource[0], 0, 989 mp->reg_size, "MyriCOM Regs"); 990 if (!mp->regs) { 991 printk("MyriCOM: Cannot map MyriCOM registers.\n"); 992 goto err; 993 } 994 mp->lanai = mp->regs + (256 * 1024); 995 mp->lregs = mp->lanai + (0x10000 * 2); 996 } else { 997 DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n")); 998 mp->cregs = sbus_ioremap(&sdev->resource[0], 0, 999 PAGE_SIZE, "MyriCOM Control Regs"); 1000 mp->lregs = sbus_ioremap(&sdev->resource[0], (256 * 1024), 1001 PAGE_SIZE, "MyriCOM LANAI Regs"); 1002 mp->lanai = 1003 sbus_ioremap(&sdev->resource[0], (512 * 1024), 1004 mp->eeprom.ramsz, "MyriCOM SRAM"); 1005 } 1006 DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n", 1007 mp->cregs, mp->lregs, mp->lanai)); 1008 1009 if (mp->eeprom.cpuvers >= CPUVERS_4_0) 1010 mp->shmem_base = 0xf000; 1011 else 1012 mp->shmem_base = 0x8000; 1013 1014 DET(("Shared memory base is %04x, ", mp->shmem_base)); 1015 1016 mp->shmem = (struct myri_shmem __iomem *) 1017 (mp->lanai + (mp->shmem_base * 2)); 1018 DET(("shmem mapped at %p\n", mp->shmem)); 1019 1020 mp->rqack = &mp->shmem->channel.recvqa; 1021 mp->rq = &mp->shmem->channel.recvq; 1022 mp->sq = &mp->shmem->channel.sendq; 1023 1024 /* Reset the board. */ 1025 DET(("Resetting LANAI\n")); 1026 myri_reset_off(mp->lregs, mp->cregs); 1027 myri_reset_on(mp->cregs); 1028 1029 /* Turn IRQ's off. */ 1030 myri_disable_irq(mp->lregs, mp->cregs); 1031 1032 /* Reset once more. */ 1033 myri_reset_on(mp->cregs); 1034 1035 /* Get the supported DVMA burst sizes from our SBUS. */ 1036 mp->myri_bursts = prom_getintdefault(mp->myri_sdev->bus->prom_node, 1037 "burst-sizes", 0x00); 1038 1039 if (!sbus_can_burst64(sdev)) 1040 mp->myri_bursts &= ~(DMA_BURST64); 1041 1042 DET(("MYRI bursts %02x\n", mp->myri_bursts)); 1043 1044 /* Encode SBUS interrupt level in second control register. */ 1045 i = prom_getint(sdev->prom_node, "interrupts"); 1046 if (i == 0) 1047 i = 4; 1048 DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n", 1049 i, (1 << i))); 1050 1051 sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL); 1052 1053 mp->dev = dev; 1054 dev->open = &myri_open; 1055 dev->stop = &myri_close; 1056 dev->hard_start_xmit = &myri_start_xmit; 1057 dev->tx_timeout = &myri_tx_timeout; 1058 dev->watchdog_timeo = 5*HZ; 1059 dev->get_stats = &myri_get_stats; 1060 dev->set_multicast_list = &myri_set_multicast; 1061 dev->irq = sdev->irqs[0]; 1062 1063 /* Register interrupt handler now. */ 1064 DET(("Requesting MYRIcom IRQ line.\n")); 1065 if (request_irq(dev->irq, &myri_interrupt, 1066 IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) { 1067 printk("MyriCOM: Cannot register interrupt handler.\n"); 1068 goto err; 1069 } 1070 1071 dev->mtu = MYRINET_MTU; 1072 dev->change_mtu = myri_change_mtu; 1073 dev->hard_header = myri_header; 1074 dev->rebuild_header = myri_rebuild_header; 1075 dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN); 1076 dev->hard_header_cache = myri_header_cache; 1077 dev->header_cache_update= myri_header_cache_update; 1078 1079 /* Load code onto the LANai. */ 1080 DET(("Loading LANAI firmware\n")); 1081 myri_load_lanai(mp); 1082 1083 if (register_netdev(dev)) { 1084 printk("MyriCOM: Cannot register device.\n"); 1085 goto err_free_irq; 1086 } 1087 1088 dev_set_drvdata(&sdev->ofdev.dev, mp); 1089 1090 num++; 1091 1092 printk("%s: MyriCOM MyriNET Ethernet ", dev->name); 1093 1094 for (i = 0; i < 6; i++) 1095 printk("%2.2x%c", dev->dev_addr[i], 1096 i == 5 ? ' ' : ':'); 1097 printk("\n"); 1098 1099 return 0; 1100 1101err_free_irq: 1102 free_irq(dev->irq, dev); 1103err: 1104 /* This will also free the co-allocated 'dev->priv' */ 1105 free_netdev(dev); 1106 return -ENODEV; 1107} 1108 1109 1110static int __devinit myri_sbus_probe(struct of_device *dev, const struct of_device_id *match) 1111{ 1112 struct sbus_dev *sdev = to_sbus_device(&dev->dev); 1113 1114 return myri_ether_init(sdev); 1115} 1116 1117static int __devexit myri_sbus_remove(struct of_device *dev) 1118{ 1119 struct myri_eth *mp = dev_get_drvdata(&dev->dev); 1120 struct net_device *net_dev = mp->dev; 1121 1122 unregister_netdevice(net_dev); 1123 1124 free_irq(net_dev->irq, net_dev); 1125 1126 if (mp->eeprom.cpuvers < CPUVERS_4_0) { 1127 sbus_iounmap(mp->regs, mp->reg_size); 1128 } else { 1129 sbus_iounmap(mp->cregs, PAGE_SIZE); 1130 sbus_iounmap(mp->lregs, (256 * 1024)); 1131 sbus_iounmap(mp->lanai, (512 * 1024)); 1132 } 1133 1134 free_netdev(net_dev); 1135 1136 dev_set_drvdata(&dev->dev, NULL); 1137 1138 return 0; 1139} 1140 1141static struct of_device_id myri_sbus_match[] = { 1142 { 1143 .name = "MYRICOM,mlanai", 1144 }, 1145 { 1146 .name = "myri", 1147 }, 1148 {}, 1149}; 1150 1151MODULE_DEVICE_TABLE(of, myri_sbus_match); 1152 1153static struct of_platform_driver myri_sbus_driver = { 1154 .name = "myri", 1155 .match_table = myri_sbus_match, 1156 .probe = myri_sbus_probe, 1157 .remove = __devexit_p(myri_sbus_remove), 1158}; 1159 1160static int __init myri_sbus_init(void) 1161{ 1162 return of_register_driver(&myri_sbus_driver, &sbus_bus_type); 1163} 1164 1165static void __exit myri_sbus_exit(void) 1166{ 1167 of_unregister_driver(&myri_sbus_driver); 1168} 1169 1170module_init(myri_sbus_init); 1171module_exit(myri_sbus_exit); 1172 1173MODULE_LICENSE("GPL"); 1174