1/* $Id: cassini.h,v 1.1.1.1 2007/08/03 18:52:44 Exp $ 2 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver. 3 * 4 * Copyright (C) 2004 Sun Microsystems Inc. 5 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of the 10 * License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 20 * 02111-1307, USA. 21 * 22 * vendor id: 0x108E (Sun Microsystems, Inc.) 23 * device id: 0xabba (Cassini) 24 * revision ids: 0x01 = Cassini 25 * 0x02 = Cassini rev 2 26 * 0x10 = Cassini+ 27 * 0x11 = Cassini+ 0.2u 28 * 29 * vendor id: 0x100b (National Semiconductor) 30 * device id: 0x0035 (DP83065/Saturn) 31 * revision ids: 0x30 = Saturn B2 32 * 33 * rings are all offset from 0. 34 * 35 * there are two clock domains: 36 * PCI: 33/66MHz clock 37 * chip: 125MHz clock 38 */ 39 40#ifndef _CASSINI_H 41#define _CASSINI_H 42 43/* cassini register map: 2M memory mapped in 32-bit memory space accessible as 44 * 32-bit words. there is no i/o port access. REG_ addresses are 45 * shared between cassini and cassini+. REG_PLUS_ addresses only 46 * appear in cassini+. REG_MINUS_ addresses only appear in cassini. 47 */ 48#define CAS_ID_REV2 0x02 49#define CAS_ID_REVPLUS 0x10 50#define CAS_ID_REVPLUS02u 0x11 51#define CAS_ID_REVSATURNB2 0x30 52 53/** global resources **/ 54 55/* this register sets the weights for the weighted round robin arbiter. e.g., 56 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit 57 * for its next turn to access the pci bus. 58 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 59 * DEFAULT: 0x0, SIZE: 5 bits 60 */ 61#define REG_CAWR 0x0004 /* core arbitration weight */ 62#define CAWR_RX_DMA_WEIGHT_SHIFT 0 63#define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */ 64#define CAWR_TX_DMA_WEIGHT_SHIFT 2 65#define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */ 66#define CAWR_RR_DIS 0x10 /* [4] */ 67 68/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst 69 * sizes determined by length of packet or descriptor transfer and the 70 * max length allowed by the target. 71 * DEFAULT: 0x0, SIZE: 1 bit 72 */ 73#define REG_INF_BURST 0x0008 /* infinite burst enable reg */ 74#define INF_BURST_EN 0x1 /* enable */ 75 76/* top level interrupts [0-9] are auto-cleared to 0 when the status 77 * register is read. second level interrupts [13 - 18] are cleared at 78 * the source. tx completion register 3 is replicated in [19 - 31] 79 * DEFAULT: 0x00000000, SIZE: 29 bits 80 */ 81#define REG_INTR_STATUS 0x000C /* interrupt status register */ 82#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set 83 xferred from host queue to 84 TX FIFO */ 85#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into 86 TX FIFO. i.e., 87 TX Kick == TX complete. if 88 PACED_MODE set, then TX FIFO 89 also empty */ 90#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx 91 FIFO */ 92#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing 93 corrupted. FATAL ERROR */ 94#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred 95 from RX FIFO to host mem. 96 RX completion reg updated. 97 may be delayed by recv 98 intr blanking. */ 99#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers. 100 RX Kick == RX complete */ 101#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing 102 corrupted. FATAL ERROR */ 103#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion 104 ring to post descriptors. 105 RX complete head incr to 106 almost reach RX complete 107 tail */ 108#define INTR_RX_BUF_AE 0x00000100 /* less than the 109 programmable threshold # 110 of free descr avail for 111 hw use */ 112#define INTR_RX_COMP_AF 0x00000200 /* less than the 113 programmable threshold # 114 of descr spaces for hw 115 use in completion descr 116 ring */ 117#define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC != 118 len of non-reassembly pkt 119 from fifo during DMA or 120 header parser provides TCP 121 header and payload size > 122 MAC packet size. 123 FATAL ERROR */ 124#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this 125 bit will be set if an interrupt 126 generated on the pci bus. useful 127 when driver is polling for 128 interrupts */ 129#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */ 130#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at 131 least 1 unmasked interrupt set */ 132#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at 133 least 1 unmasked interrupt set */ 134#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has 135 at least 1 unmasked interrupt 136 set */ 137#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least 138 1 unmasked interrupt set */ 139#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the 140 BIF has at least 1 unmasked 141 interrupt set */ 142#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion 143 3 reg data */ 144#define INTR_TX_COMP_3_SHIFT 19 145#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \ 146 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \ 147 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \ 148 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \ 149 INTR_MAC_CTRL_STATUS) 150 151/* determines which status events will cause an interrupt. layout same 152 * as REG_INTR_STATUS. 153 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits 154 */ 155#define REG_INTR_MASK 0x0010 /* Interrupt mask */ 156 157/* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS. 158 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK. 159 * DEFAULT: 0x00000000, SIZE: 12 bits 160 */ 161#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask 162 (used w/ status alias) */ 163/* same as REG_INTR_STATUS except that only bits cleared are those selected by 164 * REG_ALIAS_CLEAR 165 * DEFAULT: 0x00000000, SIZE: 29 bits 166 */ 167#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias 168 (selective clear) */ 169 170/* DEFAULT: 0x0, SIZE: 3 bits */ 171#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */ 172#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+. 173 set if no ACK64# during ABS64 cycle 174 in Cassini. */ 175#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if 176 no read retry after 2^15 clocks */ 177#define PCI_ERR_OTHER 0x04 /* other PCI errors */ 178#define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req. 179 unused in Cassini. */ 180#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req. 181 unused in Cassini. */ 182#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during 183 DMA. unused in cassini. */ 184 185/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event 186 * causes an interrupt to be generated. 187 * DEFAULT: 0x7, SIZE: 3 bits 188 */ 189#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */ 190 191/* used to configure PCI related parameters that are not in PCI config space. 192 * DEFAULT: 0bxx000, SIZE: 5 bits 193 */ 194#define REG_BIM_CFG 0x1008 /* BIM Configuration */ 195#define BIM_CFG_RESERVED0 0x001 /* reserved */ 196#define BIM_CFG_RESERVED1 0x002 /* reserved */ 197#define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */ 198#define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */ 199#define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */ 200#define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */ 201#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */ 202#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */ 203#define BIM_CFG_RESERVED2 0x100 /* reserved */ 204#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global 205 reset. reserved in Cassini. */ 206#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended. 207 reserved in Cassini. */ 208#define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0. 209 reserved in Cassini. */ 210 211/* DEFAULT: 0x00000000, SIZE: 32 bits */ 212#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */ 213#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state 214 machine bits [21:0] */ 215#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state 216 machine bits [6:0] */ 217 218/* writing to SW_RESET_TX and SW_RESET_RX will issue a global 219 * reset. poll until TX and RX read back as 0's for completion. 220 */ 221#define REG_SW_RESET 0x1010 /* Software reset */ 222#define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until 223 cleared to 0. */ 224#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until 225 cleared to 0. */ 226#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low). 227 resets PHY and anything else 228 connected to RSTOUT#. RSTOUT# 229 is also activated by local PCI 230 reset when hot-swap is being 231 done. */ 232#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with 233 this bit set, PCS and SLINK 234 modules won't be reset. 235 i.e., link won't drop. */ 236#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */ 237#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits: 238 0b000: ARB_IDLE1 239 0b001: ARB_IDLE2 240 0b010: ARB_WB_ACK 241 0b011: ARB_WB_WAT 242 0b100: ARB_RB_ACK 243 0b101: ARB_RB_WAT 244 0b110: ARB_RB_END 245 0b111: ARB_WB_END */ 246#define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits: 247 0b00: RD_PCI_WAT 248 0b01: RD_PCI_RDY 249 0b11: RD_PCI_ACK */ 250#define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits: 251 0b00: AD_IDL_RX 252 0b01: AD_ACK_RX 253 0b10: AD_ACK_TX 254 0b11: AD_IDL_TX */ 255#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits 256 0b00: WR_PCI_WAT 257 0b01: WR_PCI_RDY 258 0b11: WR_PCI_ACK */ 259#define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits: 260 0b000: ARB_IDLE1 261 0b001: ARB_IDLE2 262 0b010: ARB_TX_ACK 263 0b011: ARB_TX_WAT 264 0b100: ARB_RX_ACK 265 0b110: ARB_RX_WAT */ 266 267/* Cassini only. 64-bit register used to check PCI datapath. when read, 268 * value written has both lower and upper 32-bit halves rotated to the right 269 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF 270 */ 271#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test 272 Cassini+: reserved */ 273 274/* output enables are provided for each device's chip select and for the rest 275 * of the outputs from cassini to its local bus devices. two sw programmable 276 * bits are connected to general purpus control/status bits. 277 * DEFAULT: 0x7 278 */ 279#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device 280 output EN. default: 0x7 */ 281#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and 282 OE signal output enable on the 283 local bus interface. these 284 are shared between both local 285 bus devices. tristate when 0. */ 286#define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */ 287#define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip 288 select output enable */ 289#define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */ 290#define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */ 291#define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */ 292 293/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR 294 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI. 295 * _DATA_HI should be the last access of the sequence. 296 * DEFAULT: undefined 297 */ 298#define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for 299 purposes. */ 300#define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */ 301#define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1 302 read buffer access = 0 */ 303/* DEFAULT: undefined */ 304#define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */ 305#define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */ 306 307/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer. 308 * bit auto-clears when done with status read from _SUMMARY and _PASS bits. 309 */ 310#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST 311 control/status */ 312#define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */ 313#define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer. 314 Cassini only. reserved in 315 Cassini+. */ 316#define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read 317 buffer. */ 318#define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write 319 buffer. Cassini only. reserved 320 in Cassini+. */ 321#define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */ 322#define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */ 323#define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST. 324 Cassini only. reserved in 325 Cassini+. */ 326#define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST. 327 Cassini only. reserved in 328 Cassini+. */ 329 330/* ASUN: i'm not sure what this does as it's not in the spec. 331 * DEFAULT: 0xFC 332 */ 333#define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux 334 select register */ 335 336/* enable probe monitoring mode and select data appearing on the P_A* bus. bit 337 * values for _SEL_HI_MASK and _SEL_LOW_MASK: 338 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w, 339 * wtc empty r, post pci) 340 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp, 341 * pci rpkt comp, txdma wr req, txdma wr ack, 342 * txdma wr rdy, txdma wr xfr done) 343 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd, 344 * rd arb state, rd pci state) 345 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state, 346 * wrpci state) 347 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8] 348 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24] 349 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40] 350 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56] 351 * the following are not available in Cassini: 352 * 0xc: rx probe[7:0] 0xd: tx probe[7:0] 353 * 0xe: hp probe[7:0] 0xf: mac probe[7:0] 354 */ 355#define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */ 356#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be 357 driven on local bus P_A[15:0] 358 for debugging */ 359#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals: 360 0x03 = mac[1:0] 361 0x0C = rx[1:0] 362 0x30 = tx[1:0] 363 0xC0 = hp[1:0] */ 364#define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear 365 on P_A[15:8]. see above for 366 values. */ 367#define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear 368 on P_A[7:0]. see above for 369 values. */ 370 371/* values mean the same thing as REG_INTR_MASK excep that it's for INTB. 372 DEFAULT: 0x1F */ 373#define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask 374 register 2 for INTB */ 375#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16) 376/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to 377 * all of the alternate (2-4) INTR registers while _1 corresponds to only 378 * _MASK_1 and _STATUS_1 registers. 379 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers 380 */ 381#define INTR_RX_DONE_ALT 0x01 382#define INTR_RX_COMP_FULL_ALT 0x02 383#define INTR_RX_COMP_AF_ALT 0x04 384#define INTR_RX_BUF_UNAVAIL_1 0x08 385#define INTR_RX_BUF_AE_1 0x10 /* almost empty */ 386#define INTRN_MASK_RX_EN 0x80 387#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \ 388 INTR_RX_COMP_FULL_ALT | \ 389 INTR_RX_COMP_AF_ALT | \ 390 INTR_RX_BUF_UNAVAIL_1 | \ 391 INTR_RX_BUF_AE_1) 392#define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status 393 register 2 for INTB. default: 0x1F */ 394#define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16) 395#define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the 396 flags are set. enables desc ring. */ 397 398#define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask 399 register 2 for INTB */ 400#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16) 401 402#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status 403 register alias 2 for INTB */ 404#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16) 405 406#define REG_SATURN_PCFG 0x106c /* pin configuration register for 407 integrated macphy */ 408 409#define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */ 410#define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */ 411#define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */ 412#define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */ 413#define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */ 414#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode. 415 0 = normal */ 416#define SATURN_PCFG_MTP 0x00000080 /* test point select */ 417#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 = 418 GMII on SERDES pins for 419 monitoring. */ 420#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all 421 pins configed as outputs. 422 for power saving when using 423 internal phy. */ 424#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl 425 polarity from strapping 426 value. 427 1 = mac core led ctrl 428 polarity active low. */ 429 430 431/** transmit dma registers **/ 432#define MAX_TX_RINGS_SHIFT 2 433#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT) 434#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1) 435 436/* TX configuration. 437 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8 438 * DEFAULT: 0x3F000001 439 */ 440#define REG_TX_CFG 0x2004 /* TX config */ 441#define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA 442 will stop after xfer of current 443 buffer has been completed. */ 444#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be 445 accessed w/ FIFO addr 446 and data registers. 447 TX DMA should be 448 disabled. */ 449#define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in 450 ring 1. */ 451#define TX_CFG_DESC_RING0_SHIFT 2 452#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4) 453#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4) 454#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after 455 TX FIFO becomes empty. 456 if 0, TX_ALL set 457 if descr queue empty. */ 458#define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */ 459#define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at 460 the end of every packet kicked 461 through Q1. */ 462#define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at 463 the end of every packet kicked 464 through Q2. */ 465#define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at 466 the end of every packet kicked 467 through Q3 */ 468#define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at 469 the end of every packet kicked 470 through Q4 */ 471#define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion 472 writeback */ 473#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port 474 connection 475 0b00: tx mac req, 476 tx mac retry req, 477 tx ack and tx tag. 478 0b01: txdma rd req, 479 txdma rd ack, 480 txdma rd rdy, 481 txdma rd type0 482 0b11: txdma wr req, 483 txdma wr ack, 484 txdma wr rdy, 485 txdma wr xfr done. */ 486#define TX_CFG_CTX_SEL_SHIFT 30 487 488/* 11-bit counters that point to next location in FIFO to be loaded/retrieved. 489 * used for diagnostics only. 490 */ 491#define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */ 492#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write 493 pointer. temp hold reg. 494 diagnostics only. */ 495#define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */ 496#define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read 497 pointer */ 498 499/* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */ 500#define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */ 501 502/* current state of all state machines in TX */ 503#define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */ 504#define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */ 505#define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */ 506#define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine. 507 = 0x01 when TX disabled. */ 508#define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */ 509#define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller 510 state machine */ 511#define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */ 512 513#define REG_TX_SM_2 0x202C /* TX state machine reg #2 */ 514#define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */ 515#define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */ 516#define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */ 517 518/* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented 519 * while the upper 23 bits are taken from the TX descriptor 520 */ 521#define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */ 522#define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */ 523 524/* 13 bit registers written by driver w/ descriptor value that follows 525 * last valid xmit descriptor. kick # and complete # values are used by 526 * the xmit dma engine to control tx descr fetching. if > 1 valid 527 * tx descr is available within the cache line being read, cassini will 528 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro. 529 */ 530#define REG_TX_KICK0 0x2038 /* TX kick reg #1 */ 531#define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4) 532#define REG_TX_COMP0 0x2048 /* TX completion reg #1 */ 533#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4) 534 535/* values of TX_COMPLETE_1-4 are written. each completion register 536 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment. 537 * NOTE: completion reg values are only written back prior to TX_INTME and 538 * TX_ALL interrupts. at all other times, the most up-to-date index values 539 * should be obtained from the REG_TX_COMPLETE_# registers. 540 * here's the layout: 541 * offset from base addr completion # byte 542 * 0 TX_COMPLETE_1_MSB 543 * 1 TX_COMPLETE_1_LSB 544 * 2 TX_COMPLETE_2_MSB 545 * 3 TX_COMPLETE_2_LSB 546 * 4 TX_COMPLETE_3_MSB 547 * 5 TX_COMPLETE_3_LSB 548 * 6 TX_COMPLETE_4_MSB 549 * 7 TX_COMPLETE_4_LSB 550 */ 551#define TX_COMPWB_SIZE 8 552#define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back 553 base low */ 554#define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back 555 base high */ 556#define TX_COMPWB_MSB_MASK 0x00000000000000FFULL 557#define TX_COMPWB_MSB_SHIFT 0 558#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL 559#define TX_COMPWB_LSB_SHIFT 8 560#define TX_COMPWB_NEXT(x) ((x) >> 16) 561 562/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must 563 * be 2KB-aligned. */ 564#define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */ 565#define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */ 566#define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8) 567#define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8) 568 569/* 16-bit registers hold weights for the weighted round-robin of the 570 * four CBQ TX descr rings. weights correspond to # bytes xferred from 571 * host to TXFIFO in a round of WRR arbitration. can be set 572 * dynamically with new weights set upon completion of the current 573 * packet transfer from host memory to TXFIFO. a dummy write to any of 574 * these registers causes a queue1 pre-emption with all historical bw 575 * deficit data reset to 0 (useful when congestion requires a 576 * pre-emption/re-allocation of network bandwidth 577 */ 578#define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */ 579#define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */ 580#define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */ 581#define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */ 582 583/* diagnostics access to any TX FIFO location. every access is 65 584 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit. 585 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag 586 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if 587 * TX FIFO data integrity is desired, TX DMA should be 588 * disabled. _DATA_HI_Tx should be the last access of the sequence. 589 */ 590#define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */ 591#define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */ 592#define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */ 593#define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */ 594#define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */ 595#define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */ 596 597/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST 598 * passed for the specified memory 599 */ 600#define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */ 601#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST 602 controller state machine */ 603#define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */ 604#define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */ 605#define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */ 606#define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */ 607#define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */ 608#define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self 609 clears on completion. */ 610 611/** receive dma registers **/ 612#define MAX_RX_DESC_RINGS 2 613#define MAX_RX_COMP_RINGS 4 614 615/* receive DMA channel configuration. default: 0x80910 616 * free ring size = (1 << n)*32 -> [32 - 8k] 617 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9 618 * DEFAULT: 0x80910 619 */ 620#define REG_RX_CFG 0x4000 /* RX config */ 621#define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops 622 channel as soon as current 623 frame xfer has completed. 624 driver should disable MAC 625 for 200ms before disabling 626 RX */ 627#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX 628 free desc ring. 629 def: 0x8 = 8k */ 630#define RX_CFG_DESC_RING_SHIFT 1 631#define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete 632 ring. def: 0x8 = 32k */ 633#define RX_CFG_COMP_RING_SHIFT 5 634#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc 635 batching. def: 0x0 = 636 enabled */ 637#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st 638 data byte of the packet 639 w/in 8 byte boundares. 640 this swivels the data 641 DMA'ed to header 642 buffers, jumbo buffers 643 when header split is not 644 requested and MTU sized 645 buffers. def: 0x2 */ 646#define RX_CFG_SWIVEL_SHIFT 10 647 648/* cassini+ only */ 649#define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in 650 RX free desc ring 2. 651 def: 0x8 = 8k */ 652#define RX_CFG_DESC_RING1_SHIFT 16 653 654 655/* the page size register allows cassini chips to do the following with 656 * received data: 657 * [--------------------------------------------------------------] page 658 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad] 659 * |--------------| = PAGE_SIZE_BUFFER_STRIDE 660 * page = PAGE_SIZE 661 * offset = PAGE_SIZE_MTU_OFF 662 * for the above example, MTU_BUFFER_COUNT = 4. 663 * NOTE: as is apparent, you need to ensure that the following holds: 664 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE 665 * DEFAULT: 0x48002002 (8k pages) 666 */ 667#define REG_RX_PAGE_SIZE 0x4004 /* RX page size */ 668#define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to 669 by receive descriptors. 670 if jumbo buffers are 671 supported the page size 672 should not be < 8k. 673 0b00 = 2k, 0b01 = 4k 674 0b10 = 8k, 0b11 = 16k 675 DEFAULT: 8k */ 676#define RX_PAGE_SIZE_SHIFT 0 677#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw 678 packs into a page. 679 DEFAULT: 4 */ 680#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11 681#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate 682 each MTU buffer + 683 offset from each 684 other. 685 0b00 = 1k, 0b01 = 2k 686 0b10 = 4k, 0b11 = 8k 687 DEFAULT: 0x1 */ 688#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27 689#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that 690 hw writes the MTU buffer 691 into. 692 0b00 = 0, 693 0b01 = 64 bytes 694 0b10 = 96, 0b11 = 128 695 DEFAULT: 0x1 */ 696#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30 697 698/* 11-bit counter points to next location in RX FIFO to be loaded/read. 699 * shadow write pointers enable retries in case of early receive aborts. 700 * DEFAULT: 0x0. generated on 64-bit boundaries. 701 */ 702#define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */ 703#define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */ 704#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write 705 pointer */ 706#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read 707 pointer */ 708#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read 709 pointer. (8-bit counter) */ 710 711/* current state of RX DMA state engines + other info 712 * DEFAULT: 0x0 713 */ 714#define REG_RX_DEBUG 0x401C /* RX debug */ 715#define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC: 716 0x0 = idle, 0x1 = load_bop 717 0x2 = load 1, 0x3 = load 2 718 0x4 = load 3, 0x5 = load 4 719 0x6 = last detect 720 0x7 = wait req 721 0x8 = wait req statuss 1st 722 0x9 = load st 723 0xa = bubble mac 724 0xb = error */ 725#define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and 726 RX FIFO: 727 0x0 = idle, 0x1 = hp xfr 728 0x2 = wait hp ready 729 0x3 = wait flow code 730 0x4 = fifo xfer 731 0x5 = make status 732 0x6 = csum ready 733 0x7 = error */ 734#define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine 735 w/ MAC: 736 0x0 = idle 737 0x1 = wait xoff ack 738 0x2 = wait xon 739 0x3 = wait xon ack */ 740#define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine 741 states: 742 0x0 = idle data 743 0x1 = header begin 744 0x2 = xfer header 745 0x3 = xfer header ld 746 0x4 = mtu begin 747 0x5 = xfer mtu 748 0x6 = xfer mtu ld 749 0x7 = jumbo begin 750 0x8 = xfer jumbo 751 0x9 = xfer jumbo ld 752 0xa = reas begin 753 0xb = xfer reas 754 0xc = flush tag 755 0xd = xfer reas ld 756 0xe = error 757 0xf = bubble idle */ 758#define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine 759 states: 760 0x0 = idle desc 761 0x1 = wait ack 762 0x9 = wait ack 2 763 0x2 = fetch desc 1 764 0xa = fetch desc 2 765 0x3 = load ptrs 766 0x4 = wait dma 767 0x5 = wait ack batch 768 0x6 = post batch 769 0x7 = xfr done */ 770#define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the 771 interrupt queue */ 772#define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer 773 of the interrupt queue */ 774 775/* flow control frames are emmitted using two PAUSE thresholds: 776 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg 777 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes. 778 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated 779 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames 780 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max 781 * value is is 0x6F. 782 * DEFAULT: 0x00078 783 */ 784#define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */ 785#define RX_PAUSE_THRESH_QUANTUM 64 786#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when 787 RX FIFO occupancy > 788 value*64B */ 789#define RX_PAUSE_THRESH_OFF_SHIFT 0 790#define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after 791 emitting XOFF PAUSE when RX 792 FIFO occupancy falls below 793 this value*64B. must be 794 < XOFF threshold. if = 795 RX_FIFO_SIZE< XON frames are 796 never emitted. */ 797#define RX_PAUSE_THRESH_ON_SHIFT 12 798 799/* 13-bit register used to control RX desc fetching and intr generation. if 4+ 800 * valid RX descriptors are available, Cassini will read 4 at a time. 801 * writing N means that all desc up to *but* excluding N are available. N must 802 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned. 803 * DEFAULT: 0 on reset 804 */ 805#define REG_RX_KICK 0x4024 /* RX kick reg */ 806 807/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings. 808 * lower 13 bits of the low register are hard-wired to 0. 809 */ 810#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring 811 base low */ 812#define REG_RX_DB_HI 0x402C /* RX descriptor ring 813 base hi */ 814#define REG_RX_CB_LOW 0x4030 /* RX completion ring 815 base low */ 816#define REG_RX_CB_HI 0x4034 /* RX completion ring 817 base hi */ 818/* 13-bit register indicate desc used by cassini for receive frames. used 819 * for diagnostic purposes. 820 * DEFAULT: 0 on reset 821 */ 822#define REG_RX_COMP 0x4038 /* (ro) RX completion */ 823 824/* HEAD and TAIL are used to control RX desc posting and interrupt 825 * generation. hw moves the head register to pass ownership to sw. sw 826 * moves the tail register to pass ownership back to hw. to give all 827 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no 828 * more entries are available, DMA will pause and an interrupt will be 829 * generated to indicate no more entries are available. sw can use 830 * this interrupt to reduce the # of times it must update the 831 * completion tail register. 832 * DEFAULT: 0 on reset 833 */ 834#define REG_RX_COMP_HEAD 0x403C /* RX completion head */ 835#define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */ 836 837/* values used for receive interrupt blanking. loaded each time the ISR is read 838 * DEFAULT: 0x00000000 839 */ 840#define REG_RX_BLANK 0x4044 /* RX blanking register 841 for ISR read */ 842#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if 843 this many sets of completion 844 writebacks (up to 2 packets) 845 occur since the last time 846 the ISR was read. 0 = no 847 packet blanking */ 848#define RX_BLANK_INTR_PKT_SHIFT 0 849#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted 850 if that many clocks were 851 counted since last time the 852 ISR was read. 853 each count is 512 core 854 clocks (125MHz). 0 = no 855 time blanking */ 856#define RX_BLANK_INTR_TIME_SHIFT 12 857 858/* values used for interrupt generation based on threshold values of how 859 * many free desc and completion entries are available for hw use. 860 * DEFAULT: 0x00000000 861 */ 862#define REG_RX_AE_THRESH 0x4048 /* RX almost empty 863 thresholds */ 864#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be 865 generated if # desc 866 avail for hw use <= 867 # */ 868#define RX_AE_THRESH_FREE_SHIFT 0 869#define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be 870 generated if # of 871 completion entries 872 avail for hw use <= 873 # */ 874#define RX_AE_THRESH_COMP_SHIFT 13 875 876/* probabilities for random early drop (RED) thresholds on a FIFO threshold 877 * basis. probability should increase when the FIFO level increases. control 878 * packets are never dropped and not counted in stats. probability programmed 879 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped. 880 * DEFAULT: 0x00000000 881 */ 882#define REG_RX_RED 0x404C /* RX random early detect enable */ 883#define RX_RED_4K_6K_FIFO_MASK 0x000000FF /* 4KB < FIFO thresh < 6KB */ 884#define RX_RED_6K_8K_FIFO_MASK 0x0000FF00 /* 6KB < FIFO thresh < 8KB */ 885#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */ 886#define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */ 887 888/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO. 889 * RX control FIFO = # of packets in RX FIFO. 890 * DEFAULT: 0x0 891 */ 892#define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */ 893#define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000 /* level w/ 8B granularity */ 894#define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00 /* level w/ 8B granularity */ 895#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */ 896#define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */ 897#define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */ 898#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr 899 high */ 900 901#define REG_RX_BIST 0x4060 /* (ro) RX BIST */ 902#define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */ 903#define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */ 904#define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */ 905#define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */ 906#define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */ 907#define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */ 908#define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */ 909#define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */ 910#define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */ 911#define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */ 912#define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */ 913#define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */ 914#define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */ 915#define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */ 916#define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */ 917#define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */ 918#define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */ 919#define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */ 920#define RX_BIST_SUMMARY 0x00000002 /* when BIST complete, 921 summary pass bit 922 contains AND of BIST 923 results of all 16 924 RAMS */ 925#define RX_BIST_START 0x00000001 /* write 1 to start 926 BIST. self clears 927 on completion. */ 928 929/* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read 930 * from to retrieve packet control info. 931 * DEFAULT: 0 932 */ 933#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO 934 write ptr */ 935#define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read 936 ptr */ 937 938/* receive interrupt blanking. loaded each time interrupt alias register is 939 * read. 940 * DEFAULT: 0x0 941 */ 942#define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for 943 alias read */ 944#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if # 945 completion writebacks 946 > # since last ISR 947 read. 0 = no 948 blanking. up to 2 949 packets per 950 completion wb. */ 951#define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if # 952 clocks > # since last 953 ISR read. each count 954 is 512 core clocks 955 (125MHz). 0 = no 956 blanking. */ 957 958/* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed 959 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0 960 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset 961 * to normal operation after diagnostics, write to address location 0x0. 962 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should 963 * be the last write access of a write sequence. 964 * DEFAULT: undefined 965 */ 966#define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */ 967#define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */ 968#define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */ 969#define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */ 970#define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */ 971 972/* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of 973 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit 974 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control 975 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI 976 * should be last write access of the write sequence. 977 * DEFAULT: undefined 978 */ 979#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and 980 Batching FIFO addr */ 981#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data 982 low */ 983#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data 984 mid */ 985#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data 986 hi and flow id */ 987#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */ 988#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */ 989 990/* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO. 991 * DEFAULT: undefined 992 */ 993#define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */ 994#define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */ 995#define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */ 996#define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high 997 T0 */ 998#define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high 999 T1 */ 1000 1001/* 64-bit pointer to receive data buffer in host memory used for headers and 1002 * small packets. MSB in high register. loaded by DMA state machine and 1003 * increments as DMA writes receive data. only 50 LSB are incremented. top 1004 * 13 bits taken from RX descriptor. 1005 * DEFAULT: undefined 1006 */ 1007#define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr 1008 low */ 1009#define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr 1010 high */ 1011#define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer 1012 low */ 1013#define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer 1014 high */ 1015 1016/* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds 1017 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of 1018 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB. 1019 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set 1020 * to 0 for PIO access. DATA_HIGH should be last write of write sequence. 1021 * layout: 1022 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0] 1023 * DEFAULT: undefined 1024 */ 1025#define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table 1026 address */ 1027#define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */ 1028 1029#define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table 1030 data low */ 1031#define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table 1032 data mid */ 1033#define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table 1034 data high */ 1035 1036/* cassini+ only */ 1037/* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to 1038 * 0. same semantics as primary desc/complete rings. 1039 */ 1040#define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring 1041 2 base low */ 1042#define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring 1043 2 base high */ 1044#define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring 1045 2 base low. 4 total */ 1046#define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring 1047 2 base high. 4 total */ 1048#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1)) 1049#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1)) 1050#define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */ 1051#define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2 1052 reg */ 1053#define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2 1054 head reg. 4 total. */ 1055#define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2 1056 tail reg. 4 total. */ 1057#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1)) 1058#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1)) 1059#define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2 1060 thresholds */ 1061#define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK 1062#define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT 1063 1064/** header parser registers **/ 1065 1066/* RX parser configuration register. 1067 * DEFAULT: 0x1651004 1068 */ 1069#define REG_HP_CFG 0x4140 /* header parser 1070 configuration reg */ 1071#define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */ 1072#define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors 1073 0 = 64. 0x3f = 63 */ 1074#define HP_CFG_NUM_CPU_SHIFT 2 1075#define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment 1076 TCP seq # by one when 1077 stored in FDBM */ 1078#define HP_CFG_TCP_THRESH_MASK 0x000FFE00 /* # bytes of TCP data 1079 needed to be considered 1080 for reassembly */ 1081#define HP_CFG_TCP_THRESH_SHIFT 9 1082 1083/* access to RX Instruction RAM. 5-bit register/counter holds addr 1084 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI. 1085 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access 1086 * of sequence. 1087 * DEFAULT: undefined 1088 */ 1089#define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM 1090 address */ 1091#define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */ 1092#define REG_HP_INSTR_RAM_DATA_LOW 0x4148 /* HP instruction RAM 1093 data low */ 1094#define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF 1095#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0 1096#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000 1097#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16 1098#define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000 1099#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20 1100#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000 1101#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22 1102#define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM 1103 data mid */ 1104#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003 1105#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0 1106#define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C 1107#define HP_INSTR_RAM_MID_OUTOP_SHIFT 2 1108#define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0 1109#define HP_INSTR_RAM_MID_FNEXT_SHIFT 6 1110#define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800 1111#define HP_INSTR_RAM_MID_FOFF_SHIFT 11 1112#define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000 1113#define HP_INSTR_RAM_MID_SNEXT_SHIFT 18 1114#define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000 1115#define HP_INSTR_RAM_MID_SOFF_SHIFT 23 1116#define HP_INSTR_RAM_MID_OP_MASK 0xC0000000 1117#define HP_INSTR_RAM_MID_OP_SHIFT 30 1118#define REG_HP_INSTR_RAM_DATA_HI 0x4150 /* HP instruction RAM 1119 data high */ 1120#define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF 1121#define HP_INSTR_RAM_HI_VAL_SHIFT 0 1122#define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000 1123#define HP_INSTR_RAM_HI_MASK_SHIFT 16 1124 1125/* PIO access into RX Header parser data RAM and flow database. 1126 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits. 1127 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM. 1128 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120] 1129 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access 1130 * flow database. 1131 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg 1132 * should be the last write access of the write sequence. 1133 * DEFAULT: undefined 1134 */ 1135#define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB 1136 RAM address */ 1137#define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte 1138 locations in header 1139 parser data ram to 1140 read/write */ 1141#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations 1142 in the flow database */ 1143#define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */ 1144 1145/* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes 1146 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64] 1147 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0] 1148 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64] 1149 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0] 1150 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]} 1151 * FLOW_DB(10) = bit 0 has value for flow valid 1152 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0] 1153 */ 1154#define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */ 1155#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4) 1156 1157/* diagnostics for RX Header Parser block. 1158 * ASUN: the header parser state machine register is used for diagnostics 1159 * purposes. however, the spec doesn't have any details on it. 1160 */ 1161#define REG_HP_STATE_MACHINE 0x418C /* (ro) HP state machine */ 1162#define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */ 1163#define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */ 1164#define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */ 1165#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU 1166 number */ 1167#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */ 1168 1169#define REG_HP_STATUS1 0x4194 /* (ro) HP status 2 */ 1170#define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */ 1171#define HP_STATUS1_FLOWID_MASK 0x1F800000 /* flow id */ 1172#define HP_STATUS1_TCP_OFF_MASK 0x007F0000 /* tcp payload offset */ 1173#define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF /* tcp payload size */ 1174 1175#define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */ 1176#define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */ 1177#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start 1178 start offset */ 1179#define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */ 1180#define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */ 1181#define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o 1182 reassembly */ 1183#define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split 1184 enable */ 1185#define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload 1186 check */ 1187#define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length 1188 equal to zero */ 1189#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload 1190 chk */ 1191#define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload 1192 threshold */ 1193#define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */ 1194#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */ 1195#define HP_STATUS2_TCP_FLAG_CHECK 0x00000008 /* tcp flag check */ 1196#define HP_STATUS2_SYN_FLAG 0x00000004 /* syn flag */ 1197#define HP_STATUS2_TCP_CHECK 0x00000002 /* tcp payload chk */ 1198#define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */ 1199 1200/* BIST for header parser(HP) and flow database memories (FDBM). set _START 1201 * to start BIST. controller clears _START on completion. _START can also 1202 * be cleared to force termination of BIST. a bit set indicates that that 1203 * memory passed its BIST. 1204 */ 1205#define REG_HP_RAM_BIST 0x419C /* HP RAM BIST reg */ 1206#define HP_RAM_BIST_HP_DATA_PASS 0x80000000 /* HP data ram */ 1207#define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000 /* HP instr ram 0 */ 1208#define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000 /* HP instr ram 1 */ 1209#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */ 1210#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */ 1211#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */ 1212#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0 1213 bank 0 */ 1214#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1 1215 bank 0 */ 1216#define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000 /* FDBM flowid RAM2 1217 bank 0 */ 1218#define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000 /* FDBM flowid RAM3 1219 bank 0 */ 1220#define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000 /* FDBM flowid RAM0 1221 bank 1 */ 1222#define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000 /* FDBM flowid RAM1 1223 bank 2 */ 1224#define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000 /* FDBM flowid RAM2 1225 bank 1 */ 1226#define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000 /* FDBM flowid RAM3 1227 bank 1 */ 1228#define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000 /* FDBM tcp sequence 1229 RAM */ 1230#define HP_RAM_BIST_SUMMARY 0x00000002 /* all BIST tests */ 1231#define HP_RAM_BIST_START 0x00000001 /* start/stop BIST */ 1232 1233 1234/** MAC registers. **/ 1235/* reset bits are set using a PIO write and self-cleared after the command 1236 * execution has completed. 1237 */ 1238#define REG_MAC_TX_RESET 0x6000 /* TX MAC software reset 1239 command (default: 0x0) */ 1240#define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset 1241 command (default: 0x0) */ 1242/* execute a pause flow control frame transmission 1243 DEFAULT: 0x0XXXX */ 1244#define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */ 1245#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time 1246 to be sent on network 1247 in units of slot 1248 times */ 1249#define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl 1250 frame on network */ 1251 1252/* bit set indicates that event occurred. auto-cleared when status register 1253 * is read and have corresponding mask bits in mask register. events will 1254 * trigger an interrupt if the corresponding mask bit is 0. 1255 * status register default: 0x00000000 1256 * mask register default = 0xFFFFFFFF on reset 1257 */ 1258#define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */ 1259#define MAC_TX_FRAME_XMIT 0x0001 /* successful frame 1260 transmision */ 1261#define MAC_TX_UNDERRUN 0x0002 /* terminated frame 1262 transmission due to 1263 data starvation in the 1264 xmit data path */ 1265#define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed 1266 length passed to TX MAC 1267 by the DMA engine */ 1268#define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal 1269 collision counter */ 1270#define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive 1271 collision counter */ 1272#define MAC_TX_COLL_LATE 0x0020 /* rollover of the late 1273 collision counter */ 1274#define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first 1275 collision counter */ 1276#define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer 1277 timer */ 1278#define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak 1279 attempts counter */ 1280 1281#define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */ 1282#define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of 1283 a frame */ 1284#define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to 1285 RX FIFO overflow */ 1286#define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame 1287 counter */ 1288#define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment 1289 error counter */ 1290#define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error 1291 counter */ 1292#define MAC_RX_LEN_ERR 0x0020 /* rollover of length 1293 error counter */ 1294#define MAC_RX_VIOL_ERR 0x0040 /* rollover of code 1295 violation error */ 1296 1297/* DEFAULT: 0xXXXX0000 on reset */ 1298#define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */ 1299#define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful 1300 reception of a 1301 pause control 1302 frame */ 1303#define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a 1304 transition from 1305 "not paused" to 1306 "paused" */ 1307#define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a 1308 transition from 1309 "paused" to "not 1310 paused" */ 1311#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time 1312 operand that was 1313 received in the last 1314 pause flow control 1315 frame */ 1316 1317/* layout identical to TX MAC[8:0] */ 1318#define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */ 1319/* layout identical to RX MAC[6:0] */ 1320#define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */ 1321/* layout identical to CTRL MAC[2:0] */ 1322#define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */ 1323 1324/* to ensure proper operation, CFG_EN must be cleared to 0 and a delay 1325 * imposed before writes to other bits in the TX_MAC_CFG register or any of 1326 * the MAC parameters is performed. delay dependent upon time required to 1327 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g., 1328 * the delay for a 1518-byte frame on a 100Mbps network is 125us. 1329 * alternatively, just poll TX_CFG_EN until it reads back as 0. 1330 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and 1331 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should 1332 * be 0x200 (slot time of 512 bytes) 1333 */ 1334#define REG_MAC_TX_CFG 0x6030 /* TX MAC config reg */ 1335#define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will 1336 force TXMAC state 1337 machine to remain in 1338 idle state or to 1339 transition to idle state 1340 on completion of an 1341 ongoing packet. */ 1342#define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral 1343 process. set to 1 when 1344 full duplex and 0 when 1345 half duplex */ 1346#define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff 1347 algorithm. set to 1 when 1348 full duplex and 0 when 1349 half duplex */ 1350#define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the 1351 Rx-to-TX IPG. after 1352 receiving a frame, TX 1353 MAC will reset its 1354 deferral process to 1355 carrier sense for the 1356 amount of time = IPG0 + 1357 IPG1 and commit to 1358 transmission for time 1359 specified in IPG2. when 1360 0 or when xmitting frames 1361 back-to-pack (Tx-to-Tx 1362 IPG), TX MAC ignores 1363 IPG0 and will only use 1364 IPG1 for deferral time. 1365 IPG2 still used. */ 1366#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily 1367 give up on frame 1368 xmission. if backoff 1369 algorithm reaches the 1370 ATTEMPT_LIMIT, it will 1371 clear attempts counter 1372 and continue trying to 1373 send the frame as 1374 specified by 1375 GIVE_UP_LIM. when 0, 1376 TX MAC will execute 1377 standard CSMA/CD prot. */ 1378#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will 1379 continue to try to xmit 1380 until successful. when 1381 0, TX MAC will continue 1382 to try xmitting until 1383 successful or backoff 1384 algorithm reaches 1385 ATTEMPT_LIMIT*16 */ 1386#define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable 1387 backoff algorithm. TX 1388 MAC will not back off 1389 after a xmission attempt 1390 that resulted in a 1391 collision. */ 1392#define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that 1393 deferral process is reset 1394 in response to carrier 1395 sense during the entire 1396 duration of IPG. TX MAC 1397 will only commit to frame 1398 xmission after frame 1399 xmission has actually 1400 begun. */ 1401#define MAC_TX_CFG_NO_FCS 0x0100 /* TX MAC will not generate 1402 CRC for all xmitted 1403 packets. when clear, CRC 1404 generation is dependent 1405 upon NO_CRC bit in the 1406 xmit control word from 1407 TX DMA */ 1408#define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the 1409 carrier extension 1410 feature. this allows for 1411 longer collision domains 1412 by extending the carrier 1413 and collision window 1414 from the end of FCS until 1415 the end of the slot time 1416 if necessary. Required 1417 for half-duplex at 1Gbps, 1418 clear otherwise. */ 1419 1420/* when CRC is not stripped, reassembly packets will not contain the CRC. 1421 * these will be stripped by HRP because it reassembles layer 4 data, and the 1422 * CRC is layer 2. however, non-reassembly packets will still contain the CRC 1423 * when passed to the host. to ensure proper operation, need to wait 3.2ms 1424 * after clearing RX_CFG_EN before writing to any other RX MAC registers 1425 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears 1426 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same 1427 * restrictions as CFG_EN. 1428 */ 1429#define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */ 1430#define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */ 1431#define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0. 1432 feature not supported */ 1433#define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the 1434 last 4 bytes of a 1435 received frame. */ 1436#define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */ 1437#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid 1438 multicast frames (group 1439 bit in DA field set) */ 1440#define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter 1441 multicast addresses */ 1442#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use 1443 address filtering regs 1444 to filter both unicast 1445 and multicast 1446 addresses */ 1447#define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to 1448 RX DMA by setting BAD 1449 bit but not Abort bit 1450 in the status. CRC, 1451 framing, and length errs 1452 will not increment 1453 error counters. frames 1454 which don't match dest 1455 addr will be passed up 1456 w/ BAD bit set. */ 1457#define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of 1458 packet bursts generated 1459 by carrier extension 1460 with packet bursting 1461 senders. only applies 1462 to half-duplex 1Gbps */ 1463 1464/* DEFAULT: 0x0 */ 1465#define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */ 1466#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for 1467 sending pause flow ctrl 1468 frames */ 1469#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received 1470 pause flow ctrl frames */ 1471#define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl 1472 packets to RX DMA */ 1473 1474/* to ensure proper operation, a global initialization sequence should be 1475 * performed when a loopback config is entered or exited. if programmed after 1476 * a hw or global sw reset, RX/TX MAC software reset and initialization 1477 * should be done to ensure stable clocking. 1478 * DEFAULT: 0x0 1479 */ 1480#define REG_MAC_XIF_CFG 0x603C /* XIF config reg */ 1481#define MAC_XIF_TX_MII_OUTPUT_EN 0x0001 /* enable output drivers 1482 on MII xmit bus */ 1483#define MAC_XIF_MII_INT_LOOPBACK 0x0002 /* loopback GMII xmit data 1484 path to GMII recv data 1485 path. phy mode register 1486 clock selection must be 1487 set to GMII mode and 1488 GMII_MODE should be set 1489 to 1. in loopback mode, 1490 REFCLK will drive the 1491 entire mac core. 0 for 1492 normal operation. */ 1493#define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data 1494 path during packet 1495 xmission. clear to 0 1496 in any full duplex mode, 1497 in any loopback mode, 1498 or in half-duplex SERDES 1499 or SLINK modes. set when 1500 in half-duplex when 1501 using external phy. */ 1502#define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII 1503 clocks and datapath */ 1504#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable 1505 external tristate buffer 1506 on the MII receive 1507 bus. */ 1508#define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */ 1509#define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */ 1510 1511#define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg. 1512 recommended: 0x00 */ 1513#define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg 1514 recommended: 0x08 */ 1515#define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg 1516 recommended: 0x04 */ 1517#define REG_MAC_SLOT_TIME 0x604C /* slot time reg 1518 recommended: 0x40 */ 1519#define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg 1520 recommended: 0x40 */ 1521 1522/* FRAMESIZE_MAX holds both the max frame size as well as the max burst size. 1523 * recommended value: 0x2000.05EE 1524 */ 1525#define REG_MAC_FRAMESIZE_MAX 0x6054 /* max frame size reg */ 1526#define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000 /* max burst size */ 1527#define MAC_FRAMESIZE_MAX_BURST_SHIFT 16 1528#define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF /* max frame size */ 1529#define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0 1530#define REG_MAC_PA_SIZE 0x6058 /* PA size reg. number of 1531 preamble bytes that the 1532 TX MAC will xmit at the 1533 beginning of each frame 1534 value should be 2 or 1535 greater. recommended 1536 value: 0x07 */ 1537#define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration 1538 of jam in units of media 1539 byte time. recommended 1540 value: 0x04 */ 1541#define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. # 1542 of attempts TX MAC will 1543 make to xmit a frame 1544 before it resets its 1545 attempts counter. after 1546 the limit has been 1547 reached, TX MAC may or 1548 may not drop the frame 1549 dependent upon value 1550 in TX_MAC_CFG. 1551 recommended 1552 value: 0x10 */ 1553#define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg. 1554 type field of a MAC 1555 ctrl frame. recommended 1556 value: 0x8808 */ 1557 1558/* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes. 1559 * register contains comparison 1560 * 0 16 MSB of primary MAC addr [47:32] of DA field 1561 * 1 16 middle bits "" [31:16] of DA field 1562 * 2 16 LSB "" [15:0] of DA field 1563 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field 1564 * 4*x 16 middle bits "" [31:16] 1565 * 5*x 16 LSB "" [15:0] 1566 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 1567 * 43 16 middle bits "" [31:16] 1568 * 44 16 LSB "" [15:0] 1569 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 1570 * if there is a match, MAC will set the bit for alternative address 1571 * filter pass [15] 1572 1573 * here is the map of registers given MAC address notation: a:b:c:d:e:f 1574 * ab cd ef 1575 * primary addr reg 2 reg 1 reg 0 1576 * alt addr 1 reg 5 reg 4 reg 3 1577 * alt addr x reg 5*x reg 4*x reg 3*x 1578 * ctrl addr reg 44 reg 43 reg 42 1579 */ 1580#define REG_MAC_ADDR0 0x6080 /* MAC address 0 reg */ 1581#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4) 1582#define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg 1583 [47:32] */ 1584#define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg 1585 [31:16] */ 1586#define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg 1587 [15:0] */ 1588#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1 1589 mask reg. 8-bit reg 1590 contains nibble mask for 1591 reg 2 and 1. */ 1592#define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask 1593 reg */ 1594 1595/* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes 1596 * 16-bit registers contain bits of the hash table. 1597 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)]. 1598 * e.g., 15 -> [15:0], 0 -> [255:240] 1599 */ 1600#define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */ 1601#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4) 1602 1603/* statistics registers. these registers generate an interrupt on 1604 * overflow. recommended initialization: 0x0000. most are 16-bits except 1605 * for PEAK_ATTEMPTS register which is 8 bits. 1606 */ 1607#define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision 1608 counter. */ 1609#define REG_MAC_COLL_FIRST 0x61A4 /* first attempt 1610 successful collision 1611 counter */ 1612#define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision 1613 counter */ 1614#define REG_MAC_COLL_LATE 0x61AC /* late collision counter */ 1615#define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base 1616 is the media byte 1617 clock/256 */ 1618#define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */ 1619#define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */ 1620#define REG_MAC_LEN_ERR 0x61BC /* length error counter */ 1621#define REG_MAC_ALIGN_ERR 0x61C0 /* alignment error counter */ 1622#define REG_MAC_FCS_ERR 0x61C4 /* FCS error counter */ 1623#define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation 1624 error counter */ 1625 1626/* misc registers */ 1627#define REG_MAC_RANDOM_SEED 0x61CC /* random number seed reg. 1628 10-bit register used as a 1629 seed for the random number 1630 generator for the CSMA/CD 1631 backoff algorithm. only 1632 programmed after power-on 1633 reset and should be a 1634 random value which has a 1635 high likelihood of being 1636 unique for each MAC 1637 attached to a network 1638 segment (e.g., 10 LSB of 1639 MAC address) */ 1640 1641/* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address 1642 * map 1643 */ 1644 1645/* 27-bit register has the current state for key state machines in the MAC */ 1646#define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */ 1647#define MAC_SM_RLM_MASK 0x07800000 1648#define MAC_SM_RLM_SHIFT 23 1649#define MAC_SM_RX_FC_MASK 0x00700000 1650#define MAC_SM_RX_FC_SHIFT 20 1651#define MAC_SM_TLM_MASK 0x000F0000 1652#define MAC_SM_TLM_SHIFT 16 1653#define MAC_SM_ENCAP_SM_MASK 0x0000F000 1654#define MAC_SM_ENCAP_SM_SHIFT 12 1655#define MAC_SM_TX_REQ_MASK 0x00000C00 1656#define MAC_SM_TX_REQ_SHIFT 10 1657#define MAC_SM_TX_FC_MASK 0x000003C0 1658#define MAC_SM_TX_FC_SHIFT 6 1659#define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 1660#define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 1661#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 1662#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 1663 1664/** MIF registers. the MIF can be programmed in either bit-bang or 1665 * frame mode. 1666 **/ 1667#define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock. 1668 1 -> 0 will generate a 1669 rising edge. 0 -> 1 will 1670 generate a falling edge. */ 1671#define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit 1672 register generates data */ 1673#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output 1674 enable. enable when 1675 xmitting data from MIF to 1676 transceiver. */ 1677 1678/* 32-bit register serves as an instruction register when the MIF is 1679 * programmed in frame mode. load this register w/ a valid instruction 1680 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1681 * execution completion. during a read operation, this register will also 1682 * contain the 16-bit data returned by the tranceiver. unless specified 1683 * otherwise, fields are considered "don't care" when polling for 1684 * completion. 1685 */ 1686#define REG_MIF_FRAME 0x620C /* MIF frame/output reg */ 1687#define MIF_FRAME_START_MASK 0xC0000000 /* start of frame. 1688 load w/ 01 when 1689 issuing an instr */ 1690#define MIF_FRAME_ST 0x40000000 /* STart of frame */ 1691#define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a 1692 write. 10 for a 1693 read */ 1694#define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */ 1695#define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */ 1696#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when 1697 issuing an instr, 1698 this field should be 1699 loaded w/ the XCVR 1700 addr */ 1701#define MIF_FRAME_PHY_ADDR_SHIFT 23 1702#define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* register address. 1703 when issuing an instr, 1704 addr of register 1705 to be read/written */ 1706#define MIF_FRAME_REG_ADDR_SHIFT 18 1707#define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. 1708 when issuing an instr, 1709 set this bit to 1 */ 1710#define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. 1711 when issuing an instr, 1712 set this bit to 0. 1713 when polling for 1714 completion, 1 means 1715 that instr execution 1716 has been completed */ 1717#define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload 1718 load with 16-bit data 1719 to be written in 1720 transceiver reg for a 1721 write. doesn't matter 1722 in a read. when 1723 polling for 1724 completion, field is 1725 "don't care" for write 1726 and 16-bit data 1727 returned by the 1728 transceiver for a 1729 read (if valid bit 1730 is set) */ 1731#define REG_MIF_CFG 0x6210 /* MIF config reg */ 1732#define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1 1733 0 -> select MDIO_0 */ 1734#define MIF_CFG_POLL_EN 0x0002 /* enable polling 1735 mechanism. if set, 1736 BB_MODE should be 0 */ 1737#define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode 1738 0 -> frame mode */ 1739#define MIF_CFG_POLL_REG_MASK 0x00F8 /* register address to be 1740 used by polling mode. 1741 only meaningful if POLL_EN 1742 is set to 1 */ 1743#define MIF_CFG_POLL_REG_SHIFT 3 1744#define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose. 1745 when MDIO_0 is idle, 1746 1 -> tranceiver is 1747 connected to MDIO_0. 1748 when MIF is communicating 1749 w/ MDIO_0 in bit-bang 1750 mode, this bit indicates 1751 the incoming bit stream 1752 during a read op */ 1753#define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose. 1754 when MDIO_1 is idle, 1755 1 -> transceiver is 1756 connected to MDIO_1. 1757 when MIF is communicating 1758 w/ MDIO_1 in bit-bang 1759 mode, this bit indicates 1760 the incoming bit stream 1761 during a read op */ 1762#define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to 1763 be polled */ 1764#define MIF_CFG_POLL_PHY_SHIFT 10 1765 1766/* 16-bit register used to determine which bits in the POLL_STATUS portion of 1767 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0, 1768 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when 1769 * set. DEFAULT: 0xFFFF 1770 */ 1771#define REG_MIF_MASK 0x6214 /* MIF mask reg */ 1772 1773/* 32-bit register used when in poll mode. auto-cleared after being read */ 1774#define REG_MIF_STATUS 0x6218 /* MIF status reg */ 1775#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains 1776 the "latest image" 1777 update of the XCVR 1778 reg being read */ 1779#define MIF_STATUS_POLL_DATA_SHIFT 16 1780#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates 1781 which bits in the 1782 POLL_DATA field have 1783 changed since the 1784 MIF_STATUS reg was 1785 last read */ 1786#define MIF_STATUS_POLL_STATUS_SHIFT 0 1787 1788/* 7-bit register has current state for all state machines in the MIF */ 1789#define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */ 1790#define MIF_SM_CONTROL_MASK 0x07 /* control state machine 1791 state */ 1792#define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine 1793 state */ 1794 1795/** PCS/Serialink. the following registers are equivalent to the standard 1796 * MII management registers except that they're directly mapped in 1797 * Cassini's register space. 1798 **/ 1799 1800/* the auto-negotiation enable bit should be programmed the same at 1801 * the link partner as in the local device to enable auto-negotiation to 1802 * complete. when that bit is reprogrammed, auto-neg/manual config is 1803 * restarted automatically. 1804 * DEFAULT: 0x1040 1805 */ 1806#define REG_PCS_MII_CTRL 0x9000 /* PCS MII control reg */ 1807#define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on 1808 writes */ 1809#define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal at the PCS 1810 to MAC interface is 1811 activated regardless 1812 of activity */ 1813#define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS 1814 behaviour same for 1815 half and full dplx */ 1816#define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. 1817 restart auto- 1818 negotiation */ 1819#define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored 1820 on writes */ 1821#define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored 1822 on writes */ 1823#define PCS_MII_AUTONEG_EN 0x1000 /* default 1. PCS goes 1824 through automatic 1825 link config before it 1826 can be used. when 0, 1827 link can be used 1828 w/out any link config 1829 phase */ 1830#define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on 1831 writes */ 1832#define PCS_MII_RESET 0x8000 /* reset PCS. self-clears 1833 when done */ 1834 1835/* DEFAULT: 0x0108 */ 1836#define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */ 1837#define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1838#define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1839#define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up. 1840 0 -> link down. 0 is 1841 latched so that 0 is 1842 kept until read. read 1843 2x to determine if the 1844 link has gone up again */ 1845#define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 (able to perform 1846 auto-neg) */ 1847#define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected 1848 from received link code 1849 word. only valid after 1850 auto-neg completed */ 1851#define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation 1852 completed 1853 0 -> auto-negotiation not 1854 completed */ 1855#define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* reads as 1. used as an 1856 indication that this is 1857 a 1000 Base-X PHY. writes 1858 to it are ignored */ 1859 1860/* used during auto-negotiation. 1861 * DEFAULT: 0x00E0 1862 */ 1863#define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement 1864 reg */ 1865#define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex 1866 1000 Base-X */ 1867#define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex 1868 1000 Base-X */ 1869#define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE 1870 symmetric capability */ 1871#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE 1872 asymmetric capability */ 1873#define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13 1874 to optionally indicate to 1875 link partner that chip is 1876 going off-line. bit12 will 1877 get set when signal 1878 detect == FAIL and will 1879 remain set until 1880 successful negotiation */ 1881#define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1882#define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1883 1884/* contents updated as a result of autonegotiation. layout and definitions 1885 * identical to PCS_MII_ADVERT 1886 */ 1887#define REG_PCS_MII_LPA 0x900C /* PCS MII link partner 1888 ability reg */ 1889#define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1890#define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1891#define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1892#define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1893#define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1894#define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1895#define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1896 1897/* DEFAULT: 0x0 */ 1898#define REG_PCS_CFG 0x9010 /* PCS config reg */ 1899#define PCS_CFG_EN 0x01 /* enable PCS. must be 1900 0 when modifying 1901 PCS_MII_ADVERT */ 1902#define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to 1903 OK. bit is 1904 non-resettable */ 1905#define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation 1906 of optical signal to make 1907 signal detect okay when 1908 signal is low */ 1909#define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter 1910 measurements. a single 1911 code group is xmitted 1912 regularly. 1913 0x0 = normal operation 1914 0x1 = high freq test 1915 pattern, D21.5 1916 0x2 = low freq test 1917 pattern, K28.7 1918 0x3 = reserved */ 1919#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto- 1920 negotiation timer to 1921 a few cycles for test 1922 purposes */ 1923 1924/* used for diagnostic purposes. bits 20-22 autoclear on read */ 1925#define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine 1926 and diagnostic reg */ 1927#define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate 1928 xmission of idle. 1929 otherwise, xmission of 1930 a packet */ 1931#define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception 1932 of idle. otherwise, 1933 reception of packet */ 1934#define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* 0 indicates loss of 1935 sync */ 1936#define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3 1937 indicates reception of 1938 Config codes. cycling 1939 through 0-1 indicates 1940 reception of idles */ 1941#define PCS_SM_LINK_STATE_MASK 0x0001E000 1942#define SM_LINK_STATE_UP 0x00016000 /* link state is up */ 1943 1944#define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to 1945 recept of Config 1946 codes */ 1947#define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to 1948 loss of sync */ 1949#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes 1950 from OK to FAIL. bit29 1951 will also be set if 1952 this is set */ 1953#define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to 1954 receipt of breaklink 1955 C codes from partner. 1956 C codes w/ 0 content 1957 received triggering 1958 start/restart of 1959 autonegotiation. 1960 should be sent for 1961 no longer than 20ms */ 1962#define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being 1963 initialized. see serdes 1964 state reg */ 1965#define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or 1966 not received */ 1967#define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not 1968 achieved */ 1969#define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes 1970 w/ ack bit set */ 1971#define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues 1972 to send C codes 1973 instead of idle 1974 symbols or pkt data */ 1975 1976/* this register indicates interrupt changes in specific PCS MII status bits. 1977 * PCS_INT may be masked at the ISR level. only a single bit is implemented 1978 * for link status change. 1979 */ 1980#define REG_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */ 1981#define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed 1982 since last read */ 1983 1984/* control which network interface is used. no more than one bit should 1985 * be set. 1986 * DEFAULT: none 1987 */ 1988#define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */ 1989#define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and 1990 MII/GMII is selected. 1991 selection between MII and 1992 GMII is controlled by 1993 XIF_CFG */ 1994#define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the 1995 10-bit interface */ 1996 1997/* input to serdes chip or serialink block */ 1998#define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */ 1999#define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on 2000 serdes interface */ 2001#define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier 2002 detection. should be 2003 0x0 for normal 2004 operation */ 2005#define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1] 2006 to REFCLK when set. 2007 when clear, receiver 2008 clock locks to incoming 2009 serial data */ 2010 2011/* multiplex test outputs into the PROM address (PA_3 through PA_0) pins. 2012 * should be 0x0 for normal operations. 2013 * 0b000 normal operation, PROM address[3:0] selected 2014 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read 2015 * 0b010 rxmac req, rx ack, rx tag, rx clk shared 2016 * 0b011 txmac req, tx ack, tx tag, tx retry req 2017 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0 2018 * 0b101 R period RX, R period TX, R period HP, R period BIM 2019 * DEFAULT: 0x0 2020 */ 2021#define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */ 2022#define PCS_SOS_PROM_ADDR_MASK 0x0007 2023 2024/* used for diagnostics. this register indicates progress of the SERDES 2025 * boot up. 2026 * 0b00 undergoing reset 2027 * 0b01 waiting 500us while lockrefn is asserted 2028 * 0b10 waiting for comma detect 2029 * 0b11 receive data is synchronized 2030 * DEFAULT: 0x0 2031 */ 2032#define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */ 2033#define PCS_SERDES_STATE_MASK 0x03 2034 2035/* used for diagnostics. indicates number of packets transmitted or received. 2036 * counters rollover w/out generating an interrupt. 2037 * DEFAULT: 0x0 2038 */ 2039#define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */ 2040#define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */ 2041#define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS 2042 whether they 2043 encountered an error 2044 or not */ 2045 2046/** LocalBus Devices. the following provides run-time access to the 2047 * Cassini's PROM 2048 ***/ 2049#define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time 2050 access */ 2051#define REG_EXPANSION_ROM_RUN_END 0x17FFFF 2052 2053#define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus 2054 device */ 2055#define REG_SECOND_LOCALBUS_END 0x1FFFFF 2056 2057/* entropy device */ 2058#define REG_ENTROPY_START REG_SECOND_LOCALBUS_START 2059#define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00) 2060#define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04) 2061#define ENTROPY_STATUS_DRDY 0x01 2062#define ENTROPY_STATUS_BUSY 0x02 2063#define ENTROPY_STATUS_CIPHER 0x04 2064#define ENTROPY_STATUS_BYPASS_MASK 0x18 2065#define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05) 2066#define ENTROPY_MODE_KEY_MASK 0x07 2067#define ENTROPY_MODE_ENCRYPT 0x40 2068#define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06) 2069#define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07) 2070#define ENTROPY_RESET_DES_IO 0x01 2071#define ENTROPY_RESET_STC_MODE 0x02 2072#define ENTROPY_RESET_KEY_CACHE 0x04 2073#define ENTROPY_RESET_IV 0x08 2074#define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08) 2075#define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10) 2076#define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x)) 2077 2078/* phys of interest w/ their special mii registers */ 2079#define PHY_LUCENT_B0 0x00437421 2080#define LUCENT_MII_REG 0x1F 2081 2082#define PHY_NS_DP83065 0x20005c78 2083#define DP83065_MII_MEM 0x16 2084#define DP83065_MII_REGD 0x1D 2085#define DP83065_MII_REGE 0x1E 2086 2087#define PHY_BROADCOM_5411 0x00206071 2088#define PHY_BROADCOM_B0 0x00206050 2089#define BROADCOM_MII_REG4 0x14 2090#define BROADCOM_MII_REG5 0x15 2091#define BROADCOM_MII_REG7 0x17 2092#define BROADCOM_MII_REG8 0x18 2093 2094#define CAS_MII_ANNPTR 0x07 2095#define CAS_MII_ANNPRR 0x08 2096#define CAS_MII_1000_CTRL 0x09 2097#define CAS_MII_1000_STATUS 0x0A 2098#define CAS_MII_1000_EXTEND 0x0F 2099 2100#define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */ 2101/* 2102 * if autoneg is disabled, here's the table: 2103 * BMCR_SPEED100 = 100Mbps 2104 * BMCR_SPEED1000 = 1000Mbps 2105 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps 2106 */ 2107#define CAS_BMCR_SPEED1000 0x0040 /* Select 1000Mbps */ 2108 2109#define CAS_ADVERTISE_1000HALF 0x0100 2110#define CAS_ADVERTISE_1000FULL 0x0200 2111#define CAS_ADVERTISE_PAUSE 0x0400 2112#define CAS_ADVERTISE_ASYM_PAUSE 0x0800 2113 2114/* regular lpa register */ 2115#define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE 2116#define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE 2117 2118/* 1000_STATUS register */ 2119#define CAS_LPA_1000HALF 0x0400 2120#define CAS_LPA_1000FULL 0x0800 2121 2122#define CAS_EXTEND_1000XFULL 0x8000 2123#define CAS_EXTEND_1000XHALF 0x4000 2124#define CAS_EXTEND_1000TFULL 0x2000 2125#define CAS_EXTEND_1000THALF 0x1000 2126 2127/* cassini header parser firmware */ 2128typedef struct cas_hp_inst { 2129 const char *note; 2130 2131 u16 mask, val; 2132 2133 u8 op; 2134 u8 soff, snext; /* if match succeeds, new offset and match */ 2135 u8 foff, fnext; /* if match fails, new offset and match */ 2136 /* output info */ 2137 u8 outop; /* output opcode */ 2138 2139 u16 outarg; /* output argument */ 2140 u8 outenab; /* output enable: 0 = not, 1 = if match 2141 2 = if !match, 3 = always */ 2142 u8 outshift; /* barrel shift right, 4 bits */ 2143 u16 outmask; 2144} cas_hp_inst_t; 2145 2146/* comparison */ 2147#define OP_EQ 0 /* packet == value */ 2148#define OP_LT 1 /* packet < value */ 2149#define OP_GT 2 /* packet > value */ 2150#define OP_NP 3 /* new packet */ 2151 2152/* output opcodes */ 2153#define CL_REG 0 2154#define LD_FID 1 2155#define LD_SEQ 2 2156#define LD_CTL 3 2157#define LD_SAP 4 2158#define LD_R1 5 2159#define LD_L3 6 2160#define LD_SUM 7 2161#define LD_HDR 8 2162#define IM_FID 9 2163#define IM_SEQ 10 2164#define IM_SAP 11 2165#define IM_R1 12 2166#define IM_CTL 13 2167#define LD_LEN 14 2168#define ST_FLG 15 2169 2170/* match setp #s for IP4TCP4 */ 2171#define S1_PCKT 0 2172#define S1_VLAN 1 2173#define S1_CFI 2 2174#define S1_8023 3 2175#define S1_LLC 4 2176#define S1_LLCc 5 2177#define S1_IPV4 6 2178#define S1_IPV4c 7 2179#define S1_IPV4F 8 2180#define S1_TCP44 9 2181#define S1_IPV6 10 2182#define S1_IPV6L 11 2183#define S1_IPV6c 12 2184#define S1_TCP64 13 2185#define S1_TCPSQ 14 2186#define S1_TCPFG 15 2187#define S1_TCPHL 16 2188#define S1_TCPHc 17 2189#define S1_CLNP 18 2190#define S1_CLNP2 19 2191#define S1_DROP 20 2192#define S2_HTTP 21 2193#define S1_ESP4 22 2194#define S1_AH4 23 2195#define S1_ESP6 24 2196#define S1_AH6 25 2197 2198#define CAS_PROG_IP46TCP4_PREAMBLE \ 2199{ "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \ 2200 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \ 2201{ "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \ 2202 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \ 2203{ "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \ 2204 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2205{ "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \ 2206 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2207{ "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \ 2208 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2209{ "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \ 2210 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2211{ "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \ 2212 LD_SAP, 0x100, 3, 0x0, 0xffff}, \ 2213{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \ 2214 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \ 2215{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \ 2216 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \ 2217{ "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \ 2218 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \ 2219{ "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \ 2220 LD_SUM, 0x015, 1, 0x0, 0x0000}, \ 2221{ "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \ 2222 IM_R1, 0x128, 1, 0x0, 0xffff}, \ 2223{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \ 2224 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \ 2225{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \ 2226 LD_LEN, 0x03f, 1, 0x0, 0xffff} 2227 2228#ifdef USE_HP_IP46TCP4 2229static cas_hp_inst_t cas_prog_ip46tcp4tab[] = { 2230 CAS_PROG_IP46TCP4_PREAMBLE, 2231 { "TCP seq", /* DADDR should point to dest port */ 2232 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 2233 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2234 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2235 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2236 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, 2237 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, 2238 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2239 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2240 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2241 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2242 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2243 IM_CTL, 0x000, 0, 0x0, 0x0000}, 2244 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2245 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2246 { NULL }, 2247}; 2248#ifdef HP_IP46TCP4_DEFAULT 2249#define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab 2250#endif 2251#endif 2252 2253/* 2254 * Alternate table load which excludes HTTP server traffic from reassembly. 2255 * It is substantially similar to the basic table, with one extra state 2256 * and a few extra compares. */ 2257#ifdef USE_HP_IP46TCP4NOHTTP 2258static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = { 2259 CAS_PROG_IP46TCP4_PREAMBLE, 2260 { "TCP seq", /* DADDR should point to dest port */ 2261 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 2262 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */ 2263 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, 2264 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */ 2265 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2266 LD_R1, 0x205, 3, 0xB, 0xf000}, 2267 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2268 LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2269 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2270 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2271 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2272 CL_REG, 0x002, 3, 0x0, 0x0000}, 2273 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2274 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2275 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2276 IM_CTL, 0x044, 3, 0x0, 0xffff}, 2277 { NULL }, 2278}; 2279#ifdef HP_IP46TCP4NOHTTP_DEFAULT 2280#define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab 2281#endif 2282#endif 2283 2284/* match step #s for IP4FRAG */ 2285#define S3_IPV6c 11 2286#define S3_TCP64 12 2287#define S3_TCPSQ 13 2288#define S3_TCPFG 14 2289#define S3_TCPHL 15 2290#define S3_TCPHc 16 2291#define S3_FRAG 17 2292#define S3_FOFF 18 2293#define S3_CLNP 19 2294 2295#ifdef USE_HP_IP4FRAG 2296static cas_hp_inst_t cas_prog_ip4fragtab[] = { 2297 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, 2298 CL_REG, 0x3ff, 1, 0x0, 0x0000}, 2299 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2300 IM_CTL, 0x00a, 3, 0x0, 0xffff}, 2301 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023, 2302 CL_REG, 0x000, 0, 0x0, 0x0000}, 2303 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2304 CL_REG, 0x000, 0, 0x0, 0x0000}, 2305 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP, 2306 CL_REG, 0x000, 0, 0x0, 0x0000}, 2307 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP, 2308 CL_REG, 0x000, 0, 0x0, 0x0000}, 2309 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2310 LD_SAP, 0x100, 3, 0x0, 0xffff}, 2311 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP, 2312 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2313 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG, 2314 LD_LEN, 0x03e, 3, 0x0, 0xffff}, 2315 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP, 2316 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2317 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP, 2318 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2319 { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP, 2320 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2321 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP, 2322 LD_LEN, 0x03f, 1, 0x0, 0xffff}, 2323 { "TCP seq", /* DADDR should point to dest port */ 2324 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ, 2325 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2326 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0, 2327 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2328 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc, 2329 LD_R1, 0x205, 3, 0xB, 0xf000}, 2330 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2331 LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2332 { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, 2333 LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */ 2334 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, 2335 LD_SEQ, 0x040, 1, 0xD, 0xfff8}, 2336 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2337 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2338 { NULL }, 2339}; 2340#ifdef HP_IP4FRAG_DEFAULT 2341#define CAS_HP_FIRMWARE cas_prog_ip4fragtab 2342#endif 2343#endif 2344 2345/* 2346 * Alternate table which does batching without reassembly 2347 */ 2348#ifdef USE_HP_IP46TCP4BATCH 2349static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = { 2350 CAS_PROG_IP46TCP4_PREAMBLE, 2351 { "TCP seq", /* DADDR should point to dest port */ 2352 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ, 2353 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2354 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2355 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */ 2356 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, 2357 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, 2358 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2359 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */ 2360 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2361 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2362 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2363 S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff}, 2364 { NULL }, 2365}; 2366#ifdef HP_IP46TCP4BATCH_DEFAULT 2367#define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab 2368#endif 2369#endif 2370 2371#ifdef USE_HP_WORKAROUND 2372static cas_hp_inst_t cas_prog_workaroundtab[] = { 2373 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, 2374 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} , 2375 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2376 IM_CTL, 0x04a, 3, 0x0, 0xffff}, 2377 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, 2378 CL_REG, 0x000, 0, 0x0, 0x0000}, 2379 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2380 CL_REG, 0x000, 0, 0x0, 0x0000}, 2381 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, 2382 CL_REG, 0x000, 0, 0x0, 0x0000}, 2383 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, 2384 CL_REG, 0x000, 0, 0x0, 0x0000}, 2385 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2386 IM_SAP, 0x6AE, 3, 0x0, 0xffff}, 2387 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, 2388 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2389 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, 2390 LD_LEN, 0x03e, 1, 0x0, 0xffff}, 2391 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, 2392 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2393 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, 2394 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2395 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, 2396 IM_R1, 0x128, 1, 0x0, 0xffff}, 2397 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, 2398 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2399 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, 2400 LD_LEN, 0x03f, 1, 0x0, 0xffff}, 2401 { "TCP seq", /* DADDR should point to dest port */ 2402 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 2403 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2404 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2405 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2406 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2407 LD_R1, 0x205, 3, 0xB, 0xf000}, 2408 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2409 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2410 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2411 IM_SAP, 0x6AE, 3, 0x0, 0xffff} , 2412 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2413 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2414 { NULL }, 2415}; 2416#ifdef HP_WORKAROUND_DEFAULT 2417#define CAS_HP_FIRMWARE cas_prog_workaroundtab 2418#endif 2419#endif 2420 2421#ifdef USE_HP_ENCRYPT 2422static cas_hp_inst_t cas_prog_encryptiontab[] = { 2423 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, 2424 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000}, 2425 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2426 IM_CTL, 0x00a, 3, 0x0, 0xffff}, 2427 { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */ 2428 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, 2429 CL_REG, 0x000, 0, 0x0, 0x0000}, 2430 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2431 CL_REG, 0x000, 0, 0x0, 0x0000}, 2432 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, 2433 CL_REG, 0x000, 0, 0x0, 0x0000}, 2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, 2435 CL_REG, 0x000, 0, 0x0, 0x0000}, 2436 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2437 LD_SAP, 0x100, 3, 0x0, 0xffff}, 2438 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, 2439 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2440 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, 2441 LD_LEN, 0x03e, 1, 0x0, 0xffff}, 2442 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4, 2443 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2444 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, 2445 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2446 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, 2447 IM_R1, 0x128, 1, 0x0, 0xffff}, 2448 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, 2449 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2450 { "TCP64?", 2451 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 2452 0x03f, 1, 0x0, 0xffff}, 2453 { "TCP seq", /* 14:DADDR should point to dest port */ 2454 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 2455 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2456 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, 2457 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */ 2458 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2459 LD_R1, 0x205, 3, 0xB, 0xf000} , 2460 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2461 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2462 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2463 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2464 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2465 CL_REG, 0x002, 3, 0x0, 0x0000}, 2466 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2467 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2468 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2469 IM_CTL, 0x044, 3, 0x0, 0xffff}, 2470 { "IPV4 ESP encrypted?", /* S1_ESP4 */ 2471 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL, 2472 0x021, 1, 0x0, 0xffff}, 2473 { "IPV4 AH encrypted?", /* S1_AH4 */ 2474 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 2475 0x021, 1, 0x0, 0xffff}, 2476 { "IPV6 ESP encrypted?", /* S1_ESP6 */ 2477 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 2478 0x021, 1, 0x0, 0xffff}, 2479 { "IPV6 AH encrypted?", /* S1_AH6 */ 2480 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 2481 0x021, 1, 0x0, 0xffff}, 2482 { NULL }, 2483}; 2484#ifdef HP_ENCRYPT_DEFAULT 2485#define CAS_HP_FIRMWARE cas_prog_encryptiontab 2486#endif 2487#endif 2488 2489static cas_hp_inst_t cas_prog_null[] = { {NULL} }; 2490#ifdef HP_NULL_DEFAULT 2491#define CAS_HP_FIRMWARE cas_prog_null 2492#endif 2493 2494/* firmware patch for NS_DP83065 */ 2495typedef struct cas_saturn_patch { 2496 u16 addr; 2497 u16 val; 2498} cas_saturn_patch_t; 2499 2500cas_saturn_patch_t cas_saturn_patch[] = { 2501{0x8200, 0x007e}, {0x8201, 0x0082}, {0x8202, 0x0009}, 2502{0x8203, 0x0000}, {0x8204, 0x0000}, {0x8205, 0x0000}, 2503{0x8206, 0x0000}, {0x8207, 0x0000}, {0x8208, 0x0000}, 2504{0x8209, 0x008e}, {0x820a, 0x008e}, {0x820b, 0x00ff}, 2505{0x820c, 0x00ce}, {0x820d, 0x0082}, {0x820e, 0x0025}, 2506{0x820f, 0x00ff}, {0x8210, 0x0001}, {0x8211, 0x000f}, 2507{0x8212, 0x00ce}, {0x8213, 0x0084}, {0x8214, 0x0026}, 2508{0x8215, 0x00ff}, {0x8216, 0x0001}, {0x8217, 0x0011}, 2509{0x8218, 0x00ce}, {0x8219, 0x0085}, {0x821a, 0x003d}, 2510{0x821b, 0x00df}, {0x821c, 0x00e5}, {0x821d, 0x0086}, 2511{0x821e, 0x0039}, {0x821f, 0x00b7}, {0x8220, 0x008f}, 2512{0x8221, 0x00f8}, {0x8222, 0x007e}, {0x8223, 0x00c3}, 2513{0x8224, 0x00c2}, {0x8225, 0x0096}, {0x8226, 0x0047}, 2514{0x8227, 0x0084}, {0x8228, 0x00f3}, {0x8229, 0x008a}, 2515{0x822a, 0x0000}, {0x822b, 0x0097}, {0x822c, 0x0047}, 2516{0x822d, 0x00ce}, {0x822e, 0x0082}, {0x822f, 0x0033}, 2517{0x8230, 0x00ff}, {0x8231, 0x0001}, {0x8232, 0x000f}, 2518{0x8233, 0x0096}, {0x8234, 0x0046}, {0x8235, 0x0084}, 2519{0x8236, 0x000c}, {0x8237, 0x0081}, {0x8238, 0x0004}, 2520{0x8239, 0x0027}, {0x823a, 0x000b}, {0x823b, 0x0096}, 2521{0x823c, 0x0046}, {0x823d, 0x0084}, {0x823e, 0x000c}, 2522{0x823f, 0x0081}, {0x8240, 0x0008}, {0x8241, 0x0027}, 2523{0x8242, 0x0057}, {0x8243, 0x007e}, {0x8244, 0x0084}, 2524{0x8245, 0x0025}, {0x8246, 0x0096}, {0x8247, 0x0047}, 2525{0x8248, 0x0084}, {0x8249, 0x00f3}, {0x824a, 0x008a}, 2526{0x824b, 0x0004}, {0x824c, 0x0097}, {0x824d, 0x0047}, 2527{0x824e, 0x00ce}, {0x824f, 0x0082}, {0x8250, 0x0054}, 2528{0x8251, 0x00ff}, {0x8252, 0x0001}, {0x8253, 0x000f}, 2529{0x8254, 0x0096}, {0x8255, 0x0046}, {0x8256, 0x0084}, 2530{0x8257, 0x000c}, {0x8258, 0x0081}, {0x8259, 0x0004}, 2531{0x825a, 0x0026}, {0x825b, 0x0038}, {0x825c, 0x00b6}, 2532{0x825d, 0x0012}, {0x825e, 0x0020}, {0x825f, 0x0084}, 2533{0x8260, 0x0020}, {0x8261, 0x0026}, {0x8262, 0x0003}, 2534{0x8263, 0x007e}, {0x8264, 0x0084}, {0x8265, 0x0025}, 2535{0x8266, 0x0096}, {0x8267, 0x007b}, {0x8268, 0x00d6}, 2536{0x8269, 0x007c}, {0x826a, 0x00fe}, {0x826b, 0x008f}, 2537{0x826c, 0x0056}, {0x826d, 0x00bd}, {0x826e, 0x00f7}, 2538{0x826f, 0x00b6}, {0x8270, 0x00fe}, {0x8271, 0x008f}, 2539{0x8272, 0x004e}, {0x8273, 0x00bd}, {0x8274, 0x00ec}, 2540{0x8275, 0x008e}, {0x8276, 0x00bd}, {0x8277, 0x00fa}, 2541{0x8278, 0x00f7}, {0x8279, 0x00bd}, {0x827a, 0x00f7}, 2542{0x827b, 0x0028}, {0x827c, 0x00ce}, {0x827d, 0x0082}, 2543{0x827e, 0x0082}, {0x827f, 0x00ff}, {0x8280, 0x0001}, 2544{0x8281, 0x000f}, {0x8282, 0x0096}, {0x8283, 0x0046}, 2545{0x8284, 0x0084}, {0x8285, 0x000c}, {0x8286, 0x0081}, 2546{0x8287, 0x0004}, {0x8288, 0x0026}, {0x8289, 0x000a}, 2547{0x828a, 0x00b6}, {0x828b, 0x0012}, {0x828c, 0x0020}, 2548{0x828d, 0x0084}, {0x828e, 0x0020}, {0x828f, 0x0027}, 2549{0x8290, 0x00b5}, {0x8291, 0x007e}, {0x8292, 0x0084}, 2550{0x8293, 0x0025}, {0x8294, 0x00bd}, {0x8295, 0x00f7}, 2551{0x8296, 0x001f}, {0x8297, 0x007e}, {0x8298, 0x0084}, 2552{0x8299, 0x001f}, {0x829a, 0x0096}, {0x829b, 0x0047}, 2553{0x829c, 0x0084}, {0x829d, 0x00f3}, {0x829e, 0x008a}, 2554{0x829f, 0x0008}, {0x82a0, 0x0097}, {0x82a1, 0x0047}, 2555{0x82a2, 0x00de}, {0x82a3, 0x00e1}, {0x82a4, 0x00ad}, 2556{0x82a5, 0x0000}, {0x82a6, 0x00ce}, {0x82a7, 0x0082}, 2557{0x82a8, 0x00af}, {0x82a9, 0x00ff}, {0x82aa, 0x0001}, 2558{0x82ab, 0x000f}, {0x82ac, 0x007e}, {0x82ad, 0x0084}, 2559{0x82ae, 0x0025}, {0x82af, 0x0096}, {0x82b0, 0x0041}, 2560{0x82b1, 0x0085}, {0x82b2, 0x0010}, {0x82b3, 0x0026}, 2561{0x82b4, 0x0006}, {0x82b5, 0x0096}, {0x82b6, 0x0023}, 2562{0x82b7, 0x0085}, {0x82b8, 0x0040}, {0x82b9, 0x0027}, 2563{0x82ba, 0x0006}, {0x82bb, 0x00bd}, {0x82bc, 0x00ed}, 2564{0x82bd, 0x0000}, {0x82be, 0x007e}, {0x82bf, 0x0083}, 2565{0x82c0, 0x00a2}, {0x82c1, 0x00de}, {0x82c2, 0x0042}, 2566{0x82c3, 0x00bd}, {0x82c4, 0x00eb}, {0x82c5, 0x008e}, 2567{0x82c6, 0x0096}, {0x82c7, 0x0024}, {0x82c8, 0x0084}, 2568{0x82c9, 0x0008}, {0x82ca, 0x0027}, {0x82cb, 0x0003}, 2569{0x82cc, 0x007e}, {0x82cd, 0x0083}, {0x82ce, 0x00df}, 2570{0x82cf, 0x0096}, {0x82d0, 0x007b}, {0x82d1, 0x00d6}, 2571{0x82d2, 0x007c}, {0x82d3, 0x00fe}, {0x82d4, 0x008f}, 2572{0x82d5, 0x0056}, {0x82d6, 0x00bd}, {0x82d7, 0x00f7}, 2573{0x82d8, 0x00b6}, {0x82d9, 0x00fe}, {0x82da, 0x008f}, 2574{0x82db, 0x0050}, {0x82dc, 0x00bd}, {0x82dd, 0x00ec}, 2575{0x82de, 0x008e}, {0x82df, 0x00bd}, {0x82e0, 0x00fa}, 2576{0x82e1, 0x00f7}, {0x82e2, 0x0086}, {0x82e3, 0x0011}, 2577{0x82e4, 0x00c6}, {0x82e5, 0x0049}, {0x82e6, 0x00bd}, 2578{0x82e7, 0x00e4}, {0x82e8, 0x0012}, {0x82e9, 0x00ce}, 2579{0x82ea, 0x0082}, {0x82eb, 0x00ef}, {0x82ec, 0x00ff}, 2580{0x82ed, 0x0001}, {0x82ee, 0x000f}, {0x82ef, 0x0096}, 2581{0x82f0, 0x0046}, {0x82f1, 0x0084}, {0x82f2, 0x000c}, 2582{0x82f3, 0x0081}, {0x82f4, 0x0000}, {0x82f5, 0x0027}, 2583{0x82f6, 0x0017}, {0x82f7, 0x00c6}, {0x82f8, 0x0049}, 2584{0x82f9, 0x00bd}, {0x82fa, 0x00e4}, {0x82fb, 0x0091}, 2585{0x82fc, 0x0024}, {0x82fd, 0x000d}, {0x82fe, 0x00b6}, 2586{0x82ff, 0x0012}, {0x8300, 0x0020}, {0x8301, 0x0085}, 2587{0x8302, 0x0020}, {0x8303, 0x0026}, {0x8304, 0x000c}, 2588{0x8305, 0x00ce}, {0x8306, 0x0082}, {0x8307, 0x00c1}, 2589{0x8308, 0x00ff}, {0x8309, 0x0001}, {0x830a, 0x000f}, 2590{0x830b, 0x007e}, {0x830c, 0x0084}, {0x830d, 0x0025}, 2591{0x830e, 0x007e}, {0x830f, 0x0084}, {0x8310, 0x0016}, 2592{0x8311, 0x00fe}, {0x8312, 0x008f}, {0x8313, 0x0052}, 2593{0x8314, 0x00bd}, {0x8315, 0x00ec}, {0x8316, 0x008e}, 2594{0x8317, 0x00bd}, {0x8318, 0x00fa}, {0x8319, 0x00f7}, 2595{0x831a, 0x0086}, {0x831b, 0x006a}, {0x831c, 0x00c6}, 2596{0x831d, 0x0049}, {0x831e, 0x00bd}, {0x831f, 0x00e4}, 2597{0x8320, 0x0012}, {0x8321, 0x00ce}, {0x8322, 0x0083}, 2598{0x8323, 0x0027}, {0x8324, 0x00ff}, {0x8325, 0x0001}, 2599{0x8326, 0x000f}, {0x8327, 0x0096}, {0x8328, 0x0046}, 2600{0x8329, 0x0084}, {0x832a, 0x000c}, {0x832b, 0x0081}, 2601{0x832c, 0x0000}, {0x832d, 0x0027}, {0x832e, 0x000a}, 2602{0x832f, 0x00c6}, {0x8330, 0x0049}, {0x8331, 0x00bd}, 2603{0x8332, 0x00e4}, {0x8333, 0x0091}, {0x8334, 0x0025}, 2604{0x8335, 0x0006}, {0x8336, 0x007e}, {0x8337, 0x0084}, 2605{0x8338, 0x0025}, {0x8339, 0x007e}, {0x833a, 0x0084}, 2606{0x833b, 0x0016}, {0x833c, 0x00b6}, {0x833d, 0x0018}, 2607{0x833e, 0x0070}, {0x833f, 0x00bb}, {0x8340, 0x0019}, 2608{0x8341, 0x0070}, {0x8342, 0x002a}, {0x8343, 0x0004}, 2609{0x8344, 0x0081}, {0x8345, 0x00af}, {0x8346, 0x002e}, 2610{0x8347, 0x0019}, {0x8348, 0x0096}, {0x8349, 0x007b}, 2611{0x834a, 0x00f6}, {0x834b, 0x0020}, {0x834c, 0x0007}, 2612{0x834d, 0x00fa}, {0x834e, 0x0020}, {0x834f, 0x0027}, 2613{0x8350, 0x00c4}, {0x8351, 0x0038}, {0x8352, 0x0081}, 2614{0x8353, 0x0038}, {0x8354, 0x0027}, {0x8355, 0x000b}, 2615{0x8356, 0x00f6}, {0x8357, 0x0020}, {0x8358, 0x0007}, 2616{0x8359, 0x00fa}, {0x835a, 0x0020}, {0x835b, 0x0027}, 2617{0x835c, 0x00cb}, {0x835d, 0x0008}, {0x835e, 0x007e}, 2618{0x835f, 0x0082}, {0x8360, 0x00d3}, {0x8361, 0x00bd}, 2619{0x8362, 0x00f7}, {0x8363, 0x0066}, {0x8364, 0x0086}, 2620{0x8365, 0x0074}, {0x8366, 0x00c6}, {0x8367, 0x0049}, 2621{0x8368, 0x00bd}, {0x8369, 0x00e4}, {0x836a, 0x0012}, 2622{0x836b, 0x00ce}, {0x836c, 0x0083}, {0x836d, 0x0071}, 2623{0x836e, 0x00ff}, {0x836f, 0x0001}, {0x8370, 0x000f}, 2624{0x8371, 0x0096}, {0x8372, 0x0046}, {0x8373, 0x0084}, 2625{0x8374, 0x000c}, {0x8375, 0x0081}, {0x8376, 0x0008}, 2626{0x8377, 0x0026}, {0x8378, 0x000a}, {0x8379, 0x00c6}, 2627{0x837a, 0x0049}, {0x837b, 0x00bd}, {0x837c, 0x00e4}, 2628{0x837d, 0x0091}, {0x837e, 0x0025}, {0x837f, 0x0006}, 2629{0x8380, 0x007e}, {0x8381, 0x0084}, {0x8382, 0x0025}, 2630{0x8383, 0x007e}, {0x8384, 0x0084}, {0x8385, 0x0016}, 2631{0x8386, 0x00bd}, {0x8387, 0x00f7}, {0x8388, 0x003e}, 2632{0x8389, 0x0026}, {0x838a, 0x000e}, {0x838b, 0x00bd}, 2633{0x838c, 0x00e5}, {0x838d, 0x0009}, {0x838e, 0x0026}, 2634{0x838f, 0x0006}, {0x8390, 0x00ce}, {0x8391, 0x0082}, 2635{0x8392, 0x00c1}, {0x8393, 0x00ff}, {0x8394, 0x0001}, 2636{0x8395, 0x000f}, {0x8396, 0x007e}, {0x8397, 0x0084}, 2637{0x8398, 0x0025}, {0x8399, 0x00fe}, {0x839a, 0x008f}, 2638{0x839b, 0x0054}, {0x839c, 0x00bd}, {0x839d, 0x00ec}, 2639{0x839e, 0x008e}, {0x839f, 0x00bd}, {0x83a0, 0x00fa}, 2640{0x83a1, 0x00f7}, {0x83a2, 0x00bd}, {0x83a3, 0x00f7}, 2641{0x83a4, 0x0033}, {0x83a5, 0x0086}, {0x83a6, 0x000f}, 2642{0x83a7, 0x00c6}, {0x83a8, 0x0051}, {0x83a9, 0x00bd}, 2643{0x83aa, 0x00e4}, {0x83ab, 0x0012}, {0x83ac, 0x00ce}, 2644{0x83ad, 0x0083}, {0x83ae, 0x00b2}, {0x83af, 0x00ff}, 2645{0x83b0, 0x0001}, {0x83b1, 0x000f}, {0x83b2, 0x0096}, 2646{0x83b3, 0x0046}, {0x83b4, 0x0084}, {0x83b5, 0x000c}, 2647{0x83b6, 0x0081}, {0x83b7, 0x0008}, {0x83b8, 0x0026}, 2648{0x83b9, 0x005c}, {0x83ba, 0x00b6}, {0x83bb, 0x0012}, 2649{0x83bc, 0x0020}, {0x83bd, 0x0084}, {0x83be, 0x003f}, 2650{0x83bf, 0x0081}, {0x83c0, 0x003a}, {0x83c1, 0x0027}, 2651{0x83c2, 0x001c}, {0x83c3, 0x0096}, {0x83c4, 0x0023}, 2652{0x83c5, 0x0085}, {0x83c6, 0x0040}, {0x83c7, 0x0027}, 2653{0x83c8, 0x0003}, {0x83c9, 0x007e}, {0x83ca, 0x0084}, 2654{0x83cb, 0x0025}, {0x83cc, 0x00c6}, {0x83cd, 0x0051}, 2655{0x83ce, 0x00bd}, {0x83cf, 0x00e4}, {0x83d0, 0x0091}, 2656{0x83d1, 0x0025}, {0x83d2, 0x0003}, {0x83d3, 0x007e}, 2657{0x83d4, 0x0084}, {0x83d5, 0x0025}, {0x83d6, 0x00ce}, 2658{0x83d7, 0x0082}, {0x83d8, 0x00c1}, {0x83d9, 0x00ff}, 2659{0x83da, 0x0001}, {0x83db, 0x000f}, {0x83dc, 0x007e}, 2660{0x83dd, 0x0084}, {0x83de, 0x0025}, {0x83df, 0x00bd}, 2661{0x83e0, 0x00f8}, {0x83e1, 0x0037}, {0x83e2, 0x007c}, 2662{0x83e3, 0x0000}, {0x83e4, 0x007a}, {0x83e5, 0x00ce}, 2663{0x83e6, 0x0083}, {0x83e7, 0x00ee}, {0x83e8, 0x00ff}, 2664{0x83e9, 0x0001}, {0x83ea, 0x000f}, {0x83eb, 0x007e}, 2665{0x83ec, 0x0084}, {0x83ed, 0x0025}, {0x83ee, 0x0096}, 2666{0x83ef, 0x0046}, {0x83f0, 0x0084}, {0x83f1, 0x000c}, 2667{0x83f2, 0x0081}, {0x83f3, 0x0008}, {0x83f4, 0x0026}, 2668{0x83f5, 0x0020}, {0x83f6, 0x0096}, {0x83f7, 0x0024}, 2669{0x83f8, 0x0084}, {0x83f9, 0x0008}, {0x83fa, 0x0026}, 2670{0x83fb, 0x0029}, {0x83fc, 0x00b6}, {0x83fd, 0x0018}, 2671{0x83fe, 0x0082}, {0x83ff, 0x00bb}, {0x8400, 0x0019}, 2672{0x8401, 0x0082}, {0x8402, 0x00b1}, {0x8403, 0x0001}, 2673{0x8404, 0x003b}, {0x8405, 0x0022}, {0x8406, 0x0009}, 2674{0x8407, 0x00b6}, {0x8408, 0x0012}, {0x8409, 0x0020}, 2675{0x840a, 0x0084}, {0x840b, 0x0037}, {0x840c, 0x0081}, 2676{0x840d, 0x0032}, {0x840e, 0x0027}, {0x840f, 0x0015}, 2677{0x8410, 0x00bd}, {0x8411, 0x00f8}, {0x8412, 0x0044}, 2678{0x8413, 0x007e}, {0x8414, 0x0082}, {0x8415, 0x00c1}, 2679{0x8416, 0x00bd}, {0x8417, 0x00f7}, {0x8418, 0x001f}, 2680{0x8419, 0x00bd}, {0x841a, 0x00f8}, {0x841b, 0x0044}, 2681{0x841c, 0x00bd}, {0x841d, 0x00fc}, {0x841e, 0x0029}, 2682{0x841f, 0x00ce}, {0x8420, 0x0082}, {0x8421, 0x0025}, 2683{0x8422, 0x00ff}, {0x8423, 0x0001}, {0x8424, 0x000f}, 2684{0x8425, 0x0039}, {0x8426, 0x0096}, {0x8427, 0x0047}, 2685{0x8428, 0x0084}, {0x8429, 0x00fc}, {0x842a, 0x008a}, 2686{0x842b, 0x0000}, {0x842c, 0x0097}, {0x842d, 0x0047}, 2687{0x842e, 0x00ce}, {0x842f, 0x0084}, {0x8430, 0x0034}, 2688{0x8431, 0x00ff}, {0x8432, 0x0001}, {0x8433, 0x0011}, 2689{0x8434, 0x0096}, {0x8435, 0x0046}, {0x8436, 0x0084}, 2690{0x8437, 0x0003}, {0x8438, 0x0081}, {0x8439, 0x0002}, 2691{0x843a, 0x0027}, {0x843b, 0x0003}, {0x843c, 0x007e}, 2692{0x843d, 0x0085}, {0x843e, 0x001e}, {0x843f, 0x0096}, 2693{0x8440, 0x0047}, {0x8441, 0x0084}, {0x8442, 0x00fc}, 2694{0x8443, 0x008a}, {0x8444, 0x0002}, {0x8445, 0x0097}, 2695{0x8446, 0x0047}, {0x8447, 0x00de}, {0x8448, 0x00e1}, 2696{0x8449, 0x00ad}, {0x844a, 0x0000}, {0x844b, 0x0086}, 2697{0x844c, 0x0001}, {0x844d, 0x00b7}, {0x844e, 0x0012}, 2698{0x844f, 0x0051}, {0x8450, 0x00bd}, {0x8451, 0x00f7}, 2699{0x8452, 0x0014}, {0x8453, 0x00b6}, {0x8454, 0x0010}, 2700{0x8455, 0x0031}, {0x8456, 0x0084}, {0x8457, 0x00fd}, 2701{0x8458, 0x00b7}, {0x8459, 0x0010}, {0x845a, 0x0031}, 2702{0x845b, 0x00bd}, {0x845c, 0x00f8}, {0x845d, 0x001e}, 2703{0x845e, 0x0096}, {0x845f, 0x0081}, {0x8460, 0x00d6}, 2704{0x8461, 0x0082}, {0x8462, 0x00fe}, {0x8463, 0x008f}, 2705{0x8464, 0x005a}, {0x8465, 0x00bd}, {0x8466, 0x00f7}, 2706{0x8467, 0x00b6}, {0x8468, 0x00fe}, {0x8469, 0x008f}, 2707{0x846a, 0x005c}, {0x846b, 0x00bd}, {0x846c, 0x00ec}, 2708{0x846d, 0x008e}, {0x846e, 0x00bd}, {0x846f, 0x00fa}, 2709{0x8470, 0x00f7}, {0x8471, 0x0086}, {0x8472, 0x0008}, 2710{0x8473, 0x00d6}, {0x8474, 0x0000}, {0x8475, 0x00c5}, 2711{0x8476, 0x0010}, {0x8477, 0x0026}, {0x8478, 0x0002}, 2712{0x8479, 0x008b}, {0x847a, 0x0020}, {0x847b, 0x00c6}, 2713{0x847c, 0x0051}, {0x847d, 0x00bd}, {0x847e, 0x00e4}, 2714{0x847f, 0x0012}, {0x8480, 0x00ce}, {0x8481, 0x0084}, 2715{0x8482, 0x0086}, {0x8483, 0x00ff}, {0x8484, 0x0001}, 2716{0x8485, 0x0011}, {0x8486, 0x0096}, {0x8487, 0x0046}, 2717{0x8488, 0x0084}, {0x8489, 0x0003}, {0x848a, 0x0081}, 2718{0x848b, 0x0002}, {0x848c, 0x0027}, {0x848d, 0x0003}, 2719{0x848e, 0x007e}, {0x848f, 0x0085}, {0x8490, 0x000f}, 2720{0x8491, 0x00c6}, {0x8492, 0x0051}, {0x8493, 0x00bd}, 2721{0x8494, 0x00e4}, {0x8495, 0x0091}, {0x8496, 0x0025}, 2722{0x8497, 0x0003}, {0x8498, 0x007e}, {0x8499, 0x0085}, 2723{0x849a, 0x001e}, {0x849b, 0x0096}, {0x849c, 0x0044}, 2724{0x849d, 0x0085}, {0x849e, 0x0010}, {0x849f, 0x0026}, 2725{0x84a0, 0x000a}, {0x84a1, 0x00b6}, {0x84a2, 0x0012}, 2726{0x84a3, 0x0050}, {0x84a4, 0x00ba}, {0x84a5, 0x0001}, 2727{0x84a6, 0x003c}, {0x84a7, 0x0085}, {0x84a8, 0x0010}, 2728{0x84a9, 0x0027}, {0x84aa, 0x00a8}, {0x84ab, 0x00bd}, 2729{0x84ac, 0x00f7}, {0x84ad, 0x0066}, {0x84ae, 0x00ce}, 2730{0x84af, 0x0084}, {0x84b0, 0x00b7}, {0x84b1, 0x00ff}, 2731{0x84b2, 0x0001}, {0x84b3, 0x0011}, {0x84b4, 0x007e}, 2732{0x84b5, 0x0085}, {0x84b6, 0x001e}, {0x84b7, 0x0096}, 2733{0x84b8, 0x0046}, {0x84b9, 0x0084}, {0x84ba, 0x0003}, 2734{0x84bb, 0x0081}, {0x84bc, 0x0002}, {0x84bd, 0x0026}, 2735{0x84be, 0x0050}, {0x84bf, 0x00b6}, {0x84c0, 0x0012}, 2736{0x84c1, 0x0030}, {0x84c2, 0x0084}, {0x84c3, 0x0003}, 2737{0x84c4, 0x0081}, {0x84c5, 0x0001}, {0x84c6, 0x0027}, 2738{0x84c7, 0x0003}, {0x84c8, 0x007e}, {0x84c9, 0x0085}, 2739{0x84ca, 0x001e}, {0x84cb, 0x0096}, {0x84cc, 0x0044}, 2740{0x84cd, 0x0085}, {0x84ce, 0x0010}, {0x84cf, 0x0026}, 2741{0x84d0, 0x0013}, {0x84d1, 0x00b6}, {0x84d2, 0x0012}, 2742{0x84d3, 0x0050}, {0x84d4, 0x00ba}, {0x84d5, 0x0001}, 2743{0x84d6, 0x003c}, {0x84d7, 0x0085}, {0x84d8, 0x0010}, 2744{0x84d9, 0x0026}, {0x84da, 0x0009}, {0x84db, 0x00ce}, 2745{0x84dc, 0x0084}, {0x84dd, 0x0053}, {0x84de, 0x00ff}, 2746{0x84df, 0x0001}, {0x84e0, 0x0011}, {0x84e1, 0x007e}, 2747{0x84e2, 0x0085}, {0x84e3, 0x001e}, {0x84e4, 0x00b6}, 2748{0x84e5, 0x0010}, {0x84e6, 0x0031}, {0x84e7, 0x008a}, 2749{0x84e8, 0x0002}, {0x84e9, 0x00b7}, {0x84ea, 0x0010}, 2750{0x84eb, 0x0031}, {0x84ec, 0x00bd}, {0x84ed, 0x0085}, 2751{0x84ee, 0x001f}, {0x84ef, 0x00bd}, {0x84f0, 0x00f8}, 2752{0x84f1, 0x0037}, {0x84f2, 0x007c}, {0x84f3, 0x0000}, 2753{0x84f4, 0x0080}, {0x84f5, 0x00ce}, {0x84f6, 0x0084}, 2754{0x84f7, 0x00fe}, {0x84f8, 0x00ff}, {0x84f9, 0x0001}, 2755{0x84fa, 0x0011}, {0x84fb, 0x007e}, {0x84fc, 0x0085}, 2756{0x84fd, 0x001e}, {0x84fe, 0x0096}, {0x84ff, 0x0046}, 2757{0x8500, 0x0084}, {0x8501, 0x0003}, {0x8502, 0x0081}, 2758{0x8503, 0x0002}, {0x8504, 0x0026}, {0x8505, 0x0009}, 2759{0x8506, 0x00b6}, {0x8507, 0x0012}, {0x8508, 0x0030}, 2760{0x8509, 0x0084}, {0x850a, 0x0003}, {0x850b, 0x0081}, 2761{0x850c, 0x0001}, {0x850d, 0x0027}, {0x850e, 0x000f}, 2762{0x850f, 0x00bd}, {0x8510, 0x00f8}, {0x8511, 0x0044}, 2763{0x8512, 0x00bd}, {0x8513, 0x00f7}, {0x8514, 0x000b}, 2764{0x8515, 0x00bd}, {0x8516, 0x00fc}, {0x8517, 0x0029}, 2765{0x8518, 0x00ce}, {0x8519, 0x0084}, {0x851a, 0x0026}, 2766{0x851b, 0x00ff}, {0x851c, 0x0001}, {0x851d, 0x0011}, 2767{0x851e, 0x0039}, {0x851f, 0x00d6}, {0x8520, 0x0022}, 2768{0x8521, 0x00c4}, {0x8522, 0x000f}, {0x8523, 0x00b6}, 2769{0x8524, 0x0012}, {0x8525, 0x0030}, {0x8526, 0x00ba}, 2770{0x8527, 0x0012}, {0x8528, 0x0032}, {0x8529, 0x0084}, 2771{0x852a, 0x0004}, {0x852b, 0x0027}, {0x852c, 0x000d}, 2772{0x852d, 0x0096}, {0x852e, 0x0022}, {0x852f, 0x0085}, 2773{0x8530, 0x0004}, {0x8531, 0x0027}, {0x8532, 0x0005}, 2774{0x8533, 0x00ca}, {0x8534, 0x0010}, {0x8535, 0x007e}, 2775{0x8536, 0x0085}, {0x8537, 0x003a}, {0x8538, 0x00ca}, 2776{0x8539, 0x0020}, {0x853a, 0x00d7}, {0x853b, 0x0022}, 2777{0x853c, 0x0039}, {0x853d, 0x0086}, {0x853e, 0x0000}, 2778{0x853f, 0x0097}, {0x8540, 0x0083}, {0x8541, 0x0018}, 2779{0x8542, 0x00ce}, {0x8543, 0x001c}, {0x8544, 0x0000}, 2780{0x8545, 0x00bd}, {0x8546, 0x00eb}, {0x8547, 0x0046}, 2781{0x8548, 0x0096}, {0x8549, 0x0057}, {0x854a, 0x0085}, 2782{0x854b, 0x0001}, {0x854c, 0x0027}, {0x854d, 0x0002}, 2783{0x854e, 0x004f}, {0x854f, 0x0039}, {0x8550, 0x0085}, 2784{0x8551, 0x0002}, {0x8552, 0x0027}, {0x8553, 0x0001}, 2785{0x8554, 0x0039}, {0x8555, 0x007f}, {0x8556, 0x008f}, 2786{0x8557, 0x007d}, {0x8558, 0x0086}, {0x8559, 0x0004}, 2787{0x855a, 0x00b7}, {0x855b, 0x0012}, {0x855c, 0x0004}, 2788{0x855d, 0x0086}, {0x855e, 0x0008}, {0x855f, 0x00b7}, 2789{0x8560, 0x0012}, {0x8561, 0x0007}, {0x8562, 0x0086}, 2790{0x8563, 0x0010}, {0x8564, 0x00b7}, {0x8565, 0x0012}, 2791{0x8566, 0x000c}, {0x8567, 0x0086}, {0x8568, 0x0007}, 2792{0x8569, 0x00b7}, {0x856a, 0x0012}, {0x856b, 0x0006}, 2793{0x856c, 0x00b6}, {0x856d, 0x008f}, {0x856e, 0x007d}, 2794{0x856f, 0x00b7}, {0x8570, 0x0012}, {0x8571, 0x0070}, 2795{0x8572, 0x0086}, {0x8573, 0x0001}, {0x8574, 0x00ba}, 2796{0x8575, 0x0012}, {0x8576, 0x0004}, {0x8577, 0x00b7}, 2797{0x8578, 0x0012}, {0x8579, 0x0004}, {0x857a, 0x0001}, 2798{0x857b, 0x0001}, {0x857c, 0x0001}, {0x857d, 0x0001}, 2799{0x857e, 0x0001}, {0x857f, 0x0001}, {0x8580, 0x00b6}, 2800{0x8581, 0x0012}, {0x8582, 0x0004}, {0x8583, 0x0084}, 2801{0x8584, 0x00fe}, {0x8585, 0x008a}, {0x8586, 0x0002}, 2802{0x8587, 0x00b7}, {0x8588, 0x0012}, {0x8589, 0x0004}, 2803{0x858a, 0x0001}, {0x858b, 0x0001}, {0x858c, 0x0001}, 2804{0x858d, 0x0001}, {0x858e, 0x0001}, {0x858f, 0x0001}, 2805{0x8590, 0x0086}, {0x8591, 0x00fd}, {0x8592, 0x00b4}, 2806{0x8593, 0x0012}, {0x8594, 0x0004}, {0x8595, 0x00b7}, 2807{0x8596, 0x0012}, {0x8597, 0x0004}, {0x8598, 0x00b6}, 2808{0x8599, 0x0012}, {0x859a, 0x0000}, {0x859b, 0x0084}, 2809{0x859c, 0x0008}, {0x859d, 0x0081}, {0x859e, 0x0008}, 2810{0x859f, 0x0027}, {0x85a0, 0x0016}, {0x85a1, 0x00b6}, 2811{0x85a2, 0x008f}, {0x85a3, 0x007d}, {0x85a4, 0x0081}, 2812{0x85a5, 0x000c}, {0x85a6, 0x0027}, {0x85a7, 0x0008}, 2813{0x85a8, 0x008b}, {0x85a9, 0x0004}, {0x85aa, 0x00b7}, 2814{0x85ab, 0x008f}, {0x85ac, 0x007d}, {0x85ad, 0x007e}, 2815{0x85ae, 0x0085}, {0x85af, 0x006c}, {0x85b0, 0x0086}, 2816{0x85b1, 0x0003}, {0x85b2, 0x0097}, {0x85b3, 0x0040}, 2817{0x85b4, 0x007e}, {0x85b5, 0x0089}, {0x85b6, 0x006e}, 2818{0x85b7, 0x0086}, {0x85b8, 0x0007}, {0x85b9, 0x00b7}, 2819{0x85ba, 0x0012}, {0x85bb, 0x0006}, {0x85bc, 0x005f}, 2820{0x85bd, 0x00f7}, {0x85be, 0x008f}, {0x85bf, 0x0082}, 2821{0x85c0, 0x005f}, {0x85c1, 0x00f7}, {0x85c2, 0x008f}, 2822{0x85c3, 0x007f}, {0x85c4, 0x00f7}, {0x85c5, 0x008f}, 2823{0x85c6, 0x0070}, {0x85c7, 0x00f7}, {0x85c8, 0x008f}, 2824{0x85c9, 0x0071}, {0x85ca, 0x00f7}, {0x85cb, 0x008f}, 2825{0x85cc, 0x0072}, {0x85cd, 0x00f7}, {0x85ce, 0x008f}, 2826{0x85cf, 0x0073}, {0x85d0, 0x00f7}, {0x85d1, 0x008f}, 2827{0x85d2, 0x0074}, {0x85d3, 0x00f7}, {0x85d4, 0x008f}, 2828{0x85d5, 0x0075}, {0x85d6, 0x00f7}, {0x85d7, 0x008f}, 2829{0x85d8, 0x0076}, {0x85d9, 0x00f7}, {0x85da, 0x008f}, 2830{0x85db, 0x0077}, {0x85dc, 0x00f7}, {0x85dd, 0x008f}, 2831{0x85de, 0x0078}, {0x85df, 0x00f7}, {0x85e0, 0x008f}, 2832{0x85e1, 0x0079}, {0x85e2, 0x00f7}, {0x85e3, 0x008f}, 2833{0x85e4, 0x007a}, {0x85e5, 0x00f7}, {0x85e6, 0x008f}, 2834{0x85e7, 0x007b}, {0x85e8, 0x00b6}, {0x85e9, 0x0012}, 2835{0x85ea, 0x0004}, {0x85eb, 0x008a}, {0x85ec, 0x0010}, 2836{0x85ed, 0x00b7}, {0x85ee, 0x0012}, {0x85ef, 0x0004}, 2837{0x85f0, 0x0086}, {0x85f1, 0x00e4}, {0x85f2, 0x00b7}, 2838{0x85f3, 0x0012}, {0x85f4, 0x0070}, {0x85f5, 0x00b7}, 2839{0x85f6, 0x0012}, {0x85f7, 0x0007}, {0x85f8, 0x00f7}, 2840{0x85f9, 0x0012}, {0x85fa, 0x0005}, {0x85fb, 0x00f7}, 2841{0x85fc, 0x0012}, {0x85fd, 0x0009}, {0x85fe, 0x0086}, 2842{0x85ff, 0x0008}, {0x8600, 0x00ba}, {0x8601, 0x0012}, 2843{0x8602, 0x0004}, {0x8603, 0x00b7}, {0x8604, 0x0012}, 2844{0x8605, 0x0004}, {0x8606, 0x0086}, {0x8607, 0x00f7}, 2845{0x8608, 0x00b4}, {0x8609, 0x0012}, {0x860a, 0x0004}, 2846{0x860b, 0x00b7}, {0x860c, 0x0012}, {0x860d, 0x0004}, 2847{0x860e, 0x0001}, {0x860f, 0x0001}, {0x8610, 0x0001}, 2848{0x8611, 0x0001}, {0x8612, 0x0001}, {0x8613, 0x0001}, 2849{0x8614, 0x00b6}, {0x8615, 0x0012}, {0x8616, 0x0008}, 2850{0x8617, 0x0027}, {0x8618, 0x007f}, {0x8619, 0x0081}, 2851{0x861a, 0x0080}, {0x861b, 0x0026}, {0x861c, 0x000b}, 2852{0x861d, 0x0086}, {0x861e, 0x0008}, {0x861f, 0x00ce}, 2853{0x8620, 0x008f}, {0x8621, 0x0079}, {0x8622, 0x00bd}, 2854{0x8623, 0x0089}, {0x8624, 0x007b}, {0x8625, 0x007e}, 2855{0x8626, 0x0086}, {0x8627, 0x008e}, {0x8628, 0x0081}, 2856{0x8629, 0x0040}, {0x862a, 0x0026}, {0x862b, 0x000b}, 2857{0x862c, 0x0086}, {0x862d, 0x0004}, {0x862e, 0x00ce}, 2858{0x862f, 0x008f}, {0x8630, 0x0076}, {0x8631, 0x00bd}, 2859{0x8632, 0x0089}, {0x8633, 0x007b}, {0x8634, 0x007e}, 2860{0x8635, 0x0086}, {0x8636, 0x008e}, {0x8637, 0x0081}, 2861{0x8638, 0x0020}, {0x8639, 0x0026}, {0x863a, 0x000b}, 2862{0x863b, 0x0086}, {0x863c, 0x0002}, {0x863d, 0x00ce}, 2863{0x863e, 0x008f}, {0x863f, 0x0073}, {0x8640, 0x00bd}, 2864{0x8641, 0x0089}, {0x8642, 0x007b}, {0x8643, 0x007e}, 2865{0x8644, 0x0086}, {0x8645, 0x008e}, {0x8646, 0x0081}, 2866{0x8647, 0x0010}, {0x8648, 0x0026}, {0x8649, 0x000b}, 2867{0x864a, 0x0086}, {0x864b, 0x0001}, {0x864c, 0x00ce}, 2868{0x864d, 0x008f}, {0x864e, 0x0070}, {0x864f, 0x00bd}, 2869{0x8650, 0x0089}, {0x8651, 0x007b}, {0x8652, 0x007e}, 2870{0x8653, 0x0086}, {0x8654, 0x008e}, {0x8655, 0x0081}, 2871{0x8656, 0x0008}, {0x8657, 0x0026}, {0x8658, 0x000b}, 2872{0x8659, 0x0086}, {0x865a, 0x0008}, {0x865b, 0x00ce}, 2873{0x865c, 0x008f}, {0x865d, 0x0079}, {0x865e, 0x00bd}, 2874{0x865f, 0x0089}, {0x8660, 0x007f}, {0x8661, 0x007e}, 2875{0x8662, 0x0086}, {0x8663, 0x008e}, {0x8664, 0x0081}, 2876{0x8665, 0x0004}, {0x8666, 0x0026}, {0x8667, 0x000b}, 2877{0x8668, 0x0086}, {0x8669, 0x0004}, {0x866a, 0x00ce}, 2878{0x866b, 0x008f}, {0x866c, 0x0076}, {0x866d, 0x00bd}, 2879{0x866e, 0x0089}, {0x866f, 0x007f}, {0x8670, 0x007e}, 2880{0x8671, 0x0086}, {0x8672, 0x008e}, {0x8673, 0x0081}, 2881{0x8674, 0x0002}, {0x8675, 0x0026}, {0x8676, 0x000b}, 2882{0x8677, 0x008a}, {0x8678, 0x0002}, {0x8679, 0x00ce}, 2883{0x867a, 0x008f}, {0x867b, 0x0073}, {0x867c, 0x00bd}, 2884{0x867d, 0x0089}, {0x867e, 0x007f}, {0x867f, 0x007e}, 2885{0x8680, 0x0086}, {0x8681, 0x008e}, {0x8682, 0x0081}, 2886{0x8683, 0x0001}, {0x8684, 0x0026}, {0x8685, 0x0008}, 2887{0x8686, 0x0086}, {0x8687, 0x0001}, {0x8688, 0x00ce}, 2888{0x8689, 0x008f}, {0x868a, 0x0070}, {0x868b, 0x00bd}, 2889{0x868c, 0x0089}, {0x868d, 0x007f}, {0x868e, 0x00b6}, 2890{0x868f, 0x008f}, {0x8690, 0x007f}, {0x8691, 0x0081}, 2891{0x8692, 0x000f}, {0x8693, 0x0026}, {0x8694, 0x0003}, 2892{0x8695, 0x007e}, {0x8696, 0x0087}, {0x8697, 0x0047}, 2893{0x8698, 0x00b6}, {0x8699, 0x0012}, {0x869a, 0x0009}, 2894{0x869b, 0x0084}, {0x869c, 0x0003}, {0x869d, 0x0081}, 2895{0x869e, 0x0003}, {0x869f, 0x0027}, {0x86a0, 0x0006}, 2896{0x86a1, 0x007c}, {0x86a2, 0x0012}, {0x86a3, 0x0009}, 2897{0x86a4, 0x007e}, {0x86a5, 0x0085}, {0x86a6, 0x00fe}, 2898{0x86a7, 0x00b6}, {0x86a8, 0x0012}, {0x86a9, 0x0006}, 2899{0x86aa, 0x0084}, {0x86ab, 0x0007}, {0x86ac, 0x0081}, 2900{0x86ad, 0x0007}, {0x86ae, 0x0027}, {0x86af, 0x0008}, 2901{0x86b0, 0x008b}, {0x86b1, 0x0001}, {0x86b2, 0x00b7}, 2902{0x86b3, 0x0012}, {0x86b4, 0x0006}, {0x86b5, 0x007e}, 2903{0x86b6, 0x0086}, {0x86b7, 0x00d5}, {0x86b8, 0x00b6}, 2904{0x86b9, 0x008f}, {0x86ba, 0x0082}, {0x86bb, 0x0026}, 2905{0x86bc, 0x000a}, {0x86bd, 0x007c}, {0x86be, 0x008f}, 2906{0x86bf, 0x0082}, {0x86c0, 0x004f}, {0x86c1, 0x00b7}, 2907{0x86c2, 0x0012}, {0x86c3, 0x0006}, {0x86c4, 0x007e}, 2908{0x86c5, 0x0085}, {0x86c6, 0x00c0}, {0x86c7, 0x00b6}, 2909{0x86c8, 0x0012}, {0x86c9, 0x0006}, {0x86ca, 0x0084}, 2910{0x86cb, 0x003f}, {0x86cc, 0x0081}, {0x86cd, 0x003f}, 2911{0x86ce, 0x0027}, {0x86cf, 0x0010}, {0x86d0, 0x008b}, 2912{0x86d1, 0x0008}, {0x86d2, 0x00b7}, {0x86d3, 0x0012}, 2913{0x86d4, 0x0006}, {0x86d5, 0x00b6}, {0x86d6, 0x0012}, 2914{0x86d7, 0x0009}, {0x86d8, 0x0084}, {0x86d9, 0x00fc}, 2915{0x86da, 0x00b7}, {0x86db, 0x0012}, {0x86dc, 0x0009}, 2916{0x86dd, 0x007e}, {0x86de, 0x0085}, {0x86df, 0x00fe}, 2917{0x86e0, 0x00ce}, {0x86e1, 0x008f}, {0x86e2, 0x0070}, 2918{0x86e3, 0x0018}, {0x86e4, 0x00ce}, {0x86e5, 0x008f}, 2919{0x86e6, 0x0084}, {0x86e7, 0x00c6}, {0x86e8, 0x000c}, 2920{0x86e9, 0x00bd}, {0x86ea, 0x0089}, {0x86eb, 0x006f}, 2921{0x86ec, 0x00ce}, {0x86ed, 0x008f}, {0x86ee, 0x0084}, 2922{0x86ef, 0x0018}, {0x86f0, 0x00ce}, {0x86f1, 0x008f}, 2923{0x86f2, 0x0070}, {0x86f3, 0x00c6}, {0x86f4, 0x000c}, 2924{0x86f5, 0x00bd}, {0x86f6, 0x0089}, {0x86f7, 0x006f}, 2925{0x86f8, 0x00d6}, {0x86f9, 0x0083}, {0x86fa, 0x00c1}, 2926{0x86fb, 0x004f}, {0x86fc, 0x002d}, {0x86fd, 0x0003}, 2927{0x86fe, 0x007e}, {0x86ff, 0x0087}, {0x8700, 0x0040}, 2928{0x8701, 0x00b6}, {0x8702, 0x008f}, {0x8703, 0x007f}, 2929{0x8704, 0x0081}, {0x8705, 0x0007}, {0x8706, 0x0027}, 2930{0x8707, 0x000f}, {0x8708, 0x0081}, {0x8709, 0x000b}, 2931{0x870a, 0x0027}, {0x870b, 0x0015}, {0x870c, 0x0081}, 2932{0x870d, 0x000d}, {0x870e, 0x0027}, {0x870f, 0x001b}, 2933{0x8710, 0x0081}, {0x8711, 0x000e}, {0x8712, 0x0027}, 2934{0x8713, 0x0021}, {0x8714, 0x007e}, {0x8715, 0x0087}, 2935{0x8716, 0x0040}, {0x8717, 0x00f7}, {0x8718, 0x008f}, 2936{0x8719, 0x007b}, {0x871a, 0x0086}, {0x871b, 0x0002}, 2937{0x871c, 0x00b7}, {0x871d, 0x008f}, {0x871e, 0x007a}, 2938{0x871f, 0x0020}, {0x8720, 0x001c}, {0x8721, 0x00f7}, 2939{0x8722, 0x008f}, {0x8723, 0x0078}, {0x8724, 0x0086}, 2940{0x8725, 0x0002}, {0x8726, 0x00b7}, {0x8727, 0x008f}, 2941{0x8728, 0x0077}, {0x8729, 0x0020}, {0x872a, 0x0012}, 2942{0x872b, 0x00f7}, {0x872c, 0x008f}, {0x872d, 0x0075}, 2943{0x872e, 0x0086}, {0x872f, 0x0002}, {0x8730, 0x00b7}, 2944{0x8731, 0x008f}, {0x8732, 0x0074}, {0x8733, 0x0020}, 2945{0x8734, 0x0008}, {0x8735, 0x00f7}, {0x8736, 0x008f}, 2946{0x8737, 0x0072}, {0x8738, 0x0086}, {0x8739, 0x0002}, 2947{0x873a, 0x00b7}, {0x873b, 0x008f}, {0x873c, 0x0071}, 2948{0x873d, 0x007e}, {0x873e, 0x0087}, {0x873f, 0x0047}, 2949{0x8740, 0x0086}, {0x8741, 0x0004}, {0x8742, 0x0097}, 2950{0x8743, 0x0040}, {0x8744, 0x007e}, {0x8745, 0x0089}, 2951{0x8746, 0x006e}, {0x8747, 0x00ce}, {0x8748, 0x008f}, 2952{0x8749, 0x0072}, {0x874a, 0x00bd}, {0x874b, 0x0089}, 2953{0x874c, 0x00f7}, {0x874d, 0x00ce}, {0x874e, 0x008f}, 2954{0x874f, 0x0075}, {0x8750, 0x00bd}, {0x8751, 0x0089}, 2955{0x8752, 0x00f7}, {0x8753, 0x00ce}, {0x8754, 0x008f}, 2956{0x8755, 0x0078}, {0x8756, 0x00bd}, {0x8757, 0x0089}, 2957{0x8758, 0x00f7}, {0x8759, 0x00ce}, {0x875a, 0x008f}, 2958{0x875b, 0x007b}, {0x875c, 0x00bd}, {0x875d, 0x0089}, 2959{0x875e, 0x00f7}, {0x875f, 0x004f}, {0x8760, 0x00b7}, 2960{0x8761, 0x008f}, {0x8762, 0x007d}, {0x8763, 0x00b7}, 2961{0x8764, 0x008f}, {0x8765, 0x0081}, {0x8766, 0x00b6}, 2962{0x8767, 0x008f}, {0x8768, 0x0072}, {0x8769, 0x0027}, 2963{0x876a, 0x0047}, {0x876b, 0x007c}, {0x876c, 0x008f}, 2964{0x876d, 0x007d}, {0x876e, 0x00b6}, {0x876f, 0x008f}, 2965{0x8770, 0x0075}, {0x8771, 0x0027}, {0x8772, 0x003f}, 2966{0x8773, 0x007c}, {0x8774, 0x008f}, {0x8775, 0x007d}, 2967{0x8776, 0x00b6}, {0x8777, 0x008f}, {0x8778, 0x0078}, 2968{0x8779, 0x0027}, {0x877a, 0x0037}, {0x877b, 0x007c}, 2969{0x877c, 0x008f}, {0x877d, 0x007d}, {0x877e, 0x00b6}, 2970{0x877f, 0x008f}, {0x8780, 0x007b}, {0x8781, 0x0027}, 2971{0x8782, 0x002f}, {0x8783, 0x007f}, {0x8784, 0x008f}, 2972{0x8785, 0x007d}, {0x8786, 0x007c}, {0x8787, 0x008f}, 2973{0x8788, 0x0081}, {0x8789, 0x007a}, {0x878a, 0x008f}, 2974{0x878b, 0x0072}, {0x878c, 0x0027}, {0x878d, 0x001b}, 2975{0x878e, 0x007c}, {0x878f, 0x008f}, {0x8790, 0x007d}, 2976{0x8791, 0x007a}, {0x8792, 0x008f}, {0x8793, 0x0075}, 2977{0x8794, 0x0027}, {0x8795, 0x0016}, {0x8796, 0x007c}, 2978{0x8797, 0x008f}, {0x8798, 0x007d}, {0x8799, 0x007a}, 2979{0x879a, 0x008f}, {0x879b, 0x0078}, {0x879c, 0x0027}, 2980{0x879d, 0x0011}, {0x879e, 0x007c}, {0x879f, 0x008f}, 2981{0x87a0, 0x007d}, {0x87a1, 0x007a}, {0x87a2, 0x008f}, 2982{0x87a3, 0x007b}, {0x87a4, 0x0027}, {0x87a5, 0x000c}, 2983{0x87a6, 0x007e}, {0x87a7, 0x0087}, {0x87a8, 0x0083}, 2984{0x87a9, 0x007a}, {0x87aa, 0x008f}, {0x87ab, 0x0075}, 2985{0x87ac, 0x007a}, {0x87ad, 0x008f}, {0x87ae, 0x0078}, 2986{0x87af, 0x007a}, {0x87b0, 0x008f}, {0x87b1, 0x007b}, 2987{0x87b2, 0x00ce}, {0x87b3, 0x00c1}, {0x87b4, 0x00fc}, 2988{0x87b5, 0x00f6}, {0x87b6, 0x008f}, {0x87b7, 0x007d}, 2989{0x87b8, 0x003a}, {0x87b9, 0x00a6}, {0x87ba, 0x0000}, 2990{0x87bb, 0x00b7}, {0x87bc, 0x0012}, {0x87bd, 0x0070}, 2991{0x87be, 0x00b6}, {0x87bf, 0x008f}, {0x87c0, 0x0072}, 2992{0x87c1, 0x0026}, {0x87c2, 0x0003}, {0x87c3, 0x007e}, 2993{0x87c4, 0x0087}, {0x87c5, 0x00fa}, {0x87c6, 0x00b6}, 2994{0x87c7, 0x008f}, {0x87c8, 0x0075}, {0x87c9, 0x0026}, 2995{0x87ca, 0x000a}, {0x87cb, 0x0018}, {0x87cc, 0x00ce}, 2996{0x87cd, 0x008f}, {0x87ce, 0x0073}, {0x87cf, 0x00bd}, 2997{0x87d0, 0x0089}, {0x87d1, 0x00d5}, {0x87d2, 0x007e}, 2998{0x87d3, 0x0087}, {0x87d4, 0x00fa}, {0x87d5, 0x00b6}, 2999{0x87d6, 0x008f}, {0x87d7, 0x0078}, {0x87d8, 0x0026}, 3000{0x87d9, 0x000a}, {0x87da, 0x0018}, {0x87db, 0x00ce}, 3001{0x87dc, 0x008f}, {0x87dd, 0x0076}, {0x87de, 0x00bd}, 3002{0x87df, 0x0089}, {0x87e0, 0x00d5}, {0x87e1, 0x007e}, 3003{0x87e2, 0x0087}, {0x87e3, 0x00fa}, {0x87e4, 0x00b6}, 3004{0x87e5, 0x008f}, {0x87e6, 0x007b}, {0x87e7, 0x0026}, 3005{0x87e8, 0x000a}, {0x87e9, 0x0018}, {0x87ea, 0x00ce}, 3006{0x87eb, 0x008f}, {0x87ec, 0x0079}, {0x87ed, 0x00bd}, 3007{0x87ee, 0x0089}, {0x87ef, 0x00d5}, {0x87f0, 0x007e}, 3008{0x87f1, 0x0087}, {0x87f2, 0x00fa}, {0x87f3, 0x0086}, 3009{0x87f4, 0x0005}, {0x87f5, 0x0097}, {0x87f6, 0x0040}, 3010{0x87f7, 0x007e}, {0x87f8, 0x0089}, {0x87f9, 0x0000}, 3011{0x87fa, 0x00b6}, {0x87fb, 0x008f}, {0x87fc, 0x0075}, 3012{0x87fd, 0x0081}, {0x87fe, 0x0007}, {0x87ff, 0x002e}, 3013{0x8800, 0x00f2}, {0x8801, 0x00f6}, {0x8802, 0x0012}, 3014{0x8803, 0x0006}, {0x8804, 0x00c4}, {0x8805, 0x00f8}, 3015{0x8806, 0x001b}, {0x8807, 0x00b7}, {0x8808, 0x0012}, 3016{0x8809, 0x0006}, {0x880a, 0x00b6}, {0x880b, 0x008f}, 3017{0x880c, 0x0078}, {0x880d, 0x0081}, {0x880e, 0x0007}, 3018{0x880f, 0x002e}, {0x8810, 0x00e2}, {0x8811, 0x0048}, 3019{0x8812, 0x0048}, {0x8813, 0x0048}, {0x8814, 0x00f6}, 3020{0x8815, 0x0012}, {0x8816, 0x0006}, {0x8817, 0x00c4}, 3021{0x8818, 0x00c7}, {0x8819, 0x001b}, {0x881a, 0x00b7}, 3022{0x881b, 0x0012}, {0x881c, 0x0006}, {0x881d, 0x00b6}, 3023{0x881e, 0x008f}, {0x881f, 0x007b}, {0x8820, 0x0081}, 3024{0x8821, 0x0007}, {0x8822, 0x002e}, {0x8823, 0x00cf}, 3025{0x8824, 0x00f6}, {0x8825, 0x0012}, {0x8826, 0x0005}, 3026{0x8827, 0x00c4}, {0x8828, 0x00f8}, {0x8829, 0x001b}, 3027{0x882a, 0x00b7}, {0x882b, 0x0012}, {0x882c, 0x0005}, 3028{0x882d, 0x0086}, {0x882e, 0x0000}, {0x882f, 0x00f6}, 3029{0x8830, 0x008f}, {0x8831, 0x0071}, {0x8832, 0x00bd}, 3030{0x8833, 0x0089}, {0x8834, 0x0094}, {0x8835, 0x0086}, 3031{0x8836, 0x0001}, {0x8837, 0x00f6}, {0x8838, 0x008f}, 3032{0x8839, 0x0074}, {0x883a, 0x00bd}, {0x883b, 0x0089}, 3033{0x883c, 0x0094}, {0x883d, 0x0086}, {0x883e, 0x0002}, 3034{0x883f, 0x00f6}, {0x8840, 0x008f}, {0x8841, 0x0077}, 3035{0x8842, 0x00bd}, {0x8843, 0x0089}, {0x8844, 0x0094}, 3036{0x8845, 0x0086}, {0x8846, 0x0003}, {0x8847, 0x00f6}, 3037{0x8848, 0x008f}, {0x8849, 0x007a}, {0x884a, 0x00bd}, 3038{0x884b, 0x0089}, {0x884c, 0x0094}, {0x884d, 0x00ce}, 3039{0x884e, 0x008f}, {0x884f, 0x0070}, {0x8850, 0x00a6}, 3040{0x8851, 0x0001}, {0x8852, 0x0081}, {0x8853, 0x0001}, 3041{0x8854, 0x0027}, {0x8855, 0x0007}, {0x8856, 0x0081}, 3042{0x8857, 0x0003}, {0x8858, 0x0027}, {0x8859, 0x0003}, 3043{0x885a, 0x007e}, {0x885b, 0x0088}, {0x885c, 0x0066}, 3044{0x885d, 0x00a6}, {0x885e, 0x0000}, {0x885f, 0x00b8}, 3045{0x8860, 0x008f}, {0x8861, 0x0081}, {0x8862, 0x0084}, 3046{0x8863, 0x0001}, {0x8864, 0x0026}, {0x8865, 0x000b}, 3047{0x8866, 0x008c}, {0x8867, 0x008f}, {0x8868, 0x0079}, 3048{0x8869, 0x002c}, {0x886a, 0x000e}, {0x886b, 0x0008}, 3049{0x886c, 0x0008}, {0x886d, 0x0008}, {0x886e, 0x007e}, 3050{0x886f, 0x0088}, {0x8870, 0x0050}, {0x8871, 0x00b6}, 3051{0x8872, 0x0012}, {0x8873, 0x0004}, {0x8874, 0x008a}, 3052{0x8875, 0x0040}, {0x8876, 0x00b7}, {0x8877, 0x0012}, 3053{0x8878, 0x0004}, {0x8879, 0x00b6}, {0x887a, 0x0012}, 3054{0x887b, 0x0004}, {0x887c, 0x0084}, {0x887d, 0x00fb}, 3055{0x887e, 0x0084}, {0x887f, 0x00ef}, {0x8880, 0x00b7}, 3056{0x8881, 0x0012}, {0x8882, 0x0004}, {0x8883, 0x00b6}, 3057{0x8884, 0x0012}, {0x8885, 0x0007}, {0x8886, 0x0036}, 3058{0x8887, 0x00b6}, {0x8888, 0x008f}, {0x8889, 0x007c}, 3059{0x888a, 0x0048}, {0x888b, 0x0048}, {0x888c, 0x00b7}, 3060{0x888d, 0x0012}, {0x888e, 0x0007}, {0x888f, 0x0086}, 3061{0x8890, 0x0001}, {0x8891, 0x00ba}, {0x8892, 0x0012}, 3062{0x8893, 0x0004}, {0x8894, 0x00b7}, {0x8895, 0x0012}, 3063{0x8896, 0x0004}, {0x8897, 0x0001}, {0x8898, 0x0001}, 3064{0x8899, 0x0001}, {0x889a, 0x0001}, {0x889b, 0x0001}, 3065{0x889c, 0x0001}, {0x889d, 0x0086}, {0x889e, 0x00fe}, 3066{0x889f, 0x00b4}, {0x88a0, 0x0012}, {0x88a1, 0x0004}, 3067{0x88a2, 0x00b7}, {0x88a3, 0x0012}, {0x88a4, 0x0004}, 3068{0x88a5, 0x0086}, {0x88a6, 0x0002}, {0x88a7, 0x00ba}, 3069{0x88a8, 0x0012}, {0x88a9, 0x0004}, {0x88aa, 0x00b7}, 3070{0x88ab, 0x0012}, {0x88ac, 0x0004}, {0x88ad, 0x0086}, 3071{0x88ae, 0x00fd}, {0x88af, 0x00b4}, {0x88b0, 0x0012}, 3072{0x88b1, 0x0004}, {0x88b2, 0x00b7}, {0x88b3, 0x0012}, 3073{0x88b4, 0x0004}, {0x88b5, 0x0032}, {0x88b6, 0x00b7}, 3074{0x88b7, 0x0012}, {0x88b8, 0x0007}, {0x88b9, 0x00b6}, 3075{0x88ba, 0x0012}, {0x88bb, 0x0000}, {0x88bc, 0x0084}, 3076{0x88bd, 0x0008}, {0x88be, 0x0081}, {0x88bf, 0x0008}, 3077{0x88c0, 0x0027}, {0x88c1, 0x000f}, {0x88c2, 0x007c}, 3078{0x88c3, 0x0082}, {0x88c4, 0x0008}, {0x88c5, 0x0026}, 3079{0x88c6, 0x0007}, {0x88c7, 0x0086}, {0x88c8, 0x0076}, 3080{0x88c9, 0x0097}, {0x88ca, 0x0040}, {0x88cb, 0x007e}, 3081{0x88cc, 0x0089}, {0x88cd, 0x006e}, {0x88ce, 0x007e}, 3082{0x88cf, 0x0086}, {0x88d0, 0x00ec}, {0x88d1, 0x00b6}, 3083{0x88d2, 0x008f}, {0x88d3, 0x007f}, {0x88d4, 0x0081}, 3084{0x88d5, 0x000f}, {0x88d6, 0x0027}, {0x88d7, 0x003c}, 3085{0x88d8, 0x00bd}, {0x88d9, 0x00e6}, {0x88da, 0x00c7}, 3086{0x88db, 0x00b7}, {0x88dc, 0x0012}, {0x88dd, 0x000d}, 3087{0x88de, 0x00bd}, {0x88df, 0x00e6}, {0x88e0, 0x00cb}, 3088{0x88e1, 0x00b6}, {0x88e2, 0x0012}, {0x88e3, 0x0004}, 3089{0x88e4, 0x008a}, {0x88e5, 0x0020}, {0x88e6, 0x00b7}, 3090{0x88e7, 0x0012}, {0x88e8, 0x0004}, {0x88e9, 0x00ce}, 3091{0x88ea, 0x00ff}, {0x88eb, 0x00ff}, {0x88ec, 0x00b6}, 3092{0x88ed, 0x0012}, {0x88ee, 0x0000}, {0x88ef, 0x0081}, 3093{0x88f0, 0x000c}, {0x88f1, 0x0026}, {0x88f2, 0x0005}, 3094{0x88f3, 0x0009}, {0x88f4, 0x0026}, {0x88f5, 0x00f6}, 3095{0x88f6, 0x0027}, {0x88f7, 0x001c}, {0x88f8, 0x00b6}, 3096{0x88f9, 0x0012}, {0x88fa, 0x0004}, {0x88fb, 0x0084}, 3097{0x88fc, 0x00df}, {0x88fd, 0x00b7}, {0x88fe, 0x0012}, 3098{0x88ff, 0x0004}, {0x8900, 0x0096}, {0x8901, 0x0083}, 3099{0x8902, 0x0081}, {0x8903, 0x0007}, {0x8904, 0x002c}, 3100{0x8905, 0x0005}, {0x8906, 0x007c}, {0x8907, 0x0000}, 3101{0x8908, 0x0083}, {0x8909, 0x0020}, {0x890a, 0x0006}, 3102{0x890b, 0x0096}, {0x890c, 0x0083}, {0x890d, 0x008b}, 3103{0x890e, 0x0008}, {0x890f, 0x0097}, {0x8910, 0x0083}, 3104{0x8911, 0x007e}, {0x8912, 0x0085}, {0x8913, 0x0041}, 3105{0x8914, 0x007f}, {0x8915, 0x008f}, {0x8916, 0x007e}, 3106{0x8917, 0x0086}, {0x8918, 0x0080}, {0x8919, 0x00b7}, 3107{0x891a, 0x0012}, {0x891b, 0x000c}, {0x891c, 0x0086}, 3108{0x891d, 0x0001}, {0x891e, 0x00b7}, {0x891f, 0x008f}, 3109{0x8920, 0x007d}, {0x8921, 0x00b6}, {0x8922, 0x0012}, 3110{0x8923, 0x000c}, {0x8924, 0x0084}, {0x8925, 0x007f}, 3111{0x8926, 0x00b7}, {0x8927, 0x0012}, {0x8928, 0x000c}, 3112{0x8929, 0x008a}, {0x892a, 0x0080}, {0x892b, 0x00b7}, 3113{0x892c, 0x0012}, {0x892d, 0x000c}, {0x892e, 0x0086}, 3114{0x892f, 0x000a}, {0x8930, 0x00bd}, {0x8931, 0x008a}, 3115{0x8932, 0x0006}, {0x8933, 0x00b6}, {0x8934, 0x0012}, 3116{0x8935, 0x000a}, {0x8936, 0x002a}, {0x8937, 0x0009}, 3117{0x8938, 0x00b6}, {0x8939, 0x0012}, {0x893a, 0x000c}, 3118{0x893b, 0x00ba}, {0x893c, 0x008f}, {0x893d, 0x007d}, 3119{0x893e, 0x00b7}, {0x893f, 0x0012}, {0x8940, 0x000c}, 3120{0x8941, 0x00b6}, {0x8942, 0x008f}, {0x8943, 0x007e}, 3121{0x8944, 0x0081}, {0x8945, 0x0060}, {0x8946, 0x0027}, 3122{0x8947, 0x001a}, {0x8948, 0x008b}, {0x8949, 0x0020}, 3123{0x894a, 0x00b7}, {0x894b, 0x008f}, {0x894c, 0x007e}, 3124{0x894d, 0x00b6}, {0x894e, 0x0012}, {0x894f, 0x000c}, 3125{0x8950, 0x0084}, {0x8951, 0x009f}, {0x8952, 0x00ba}, 3126{0x8953, 0x008f}, {0x8954, 0x007e}, {0x8955, 0x00b7}, 3127{0x8956, 0x0012}, {0x8957, 0x000c}, {0x8958, 0x00b6}, 3128{0x8959, 0x008f}, {0x895a, 0x007d}, {0x895b, 0x0048}, 3129{0x895c, 0x00b7}, {0x895d, 0x008f}, {0x895e, 0x007d}, 3130{0x895f, 0x007e}, {0x8960, 0x0089}, {0x8961, 0x0021}, 3131{0x8962, 0x00b6}, {0x8963, 0x0012}, {0x8964, 0x0004}, 3132{0x8965, 0x008a}, {0x8966, 0x0020}, {0x8967, 0x00b7}, 3133{0x8968, 0x0012}, {0x8969, 0x0004}, {0x896a, 0x00bd}, 3134{0x896b, 0x008a}, {0x896c, 0x000a}, {0x896d, 0x004f}, 3135{0x896e, 0x0039}, {0x896f, 0x00a6}, {0x8970, 0x0000}, 3136{0x8971, 0x0018}, {0x8972, 0x00a7}, {0x8973, 0x0000}, 3137{0x8974, 0x0008}, {0x8975, 0x0018}, {0x8976, 0x0008}, 3138{0x8977, 0x005a}, {0x8978, 0x0026}, {0x8979, 0x00f5}, 3139{0x897a, 0x0039}, {0x897b, 0x0036}, {0x897c, 0x006c}, 3140{0x897d, 0x0000}, {0x897e, 0x0032}, {0x897f, 0x00ba}, 3141{0x8980, 0x008f}, {0x8981, 0x007f}, {0x8982, 0x00b7}, 3142{0x8983, 0x008f}, {0x8984, 0x007f}, {0x8985, 0x00b6}, 3143{0x8986, 0x0012}, {0x8987, 0x0009}, {0x8988, 0x0084}, 3144{0x8989, 0x0003}, {0x898a, 0x00a7}, {0x898b, 0x0001}, 3145{0x898c, 0x00b6}, {0x898d, 0x0012}, {0x898e, 0x0006}, 3146{0x898f, 0x0084}, {0x8990, 0x003f}, {0x8991, 0x00a7}, 3147{0x8992, 0x0002}, {0x8993, 0x0039}, {0x8994, 0x0036}, 3148{0x8995, 0x0086}, {0x8996, 0x0003}, {0x8997, 0x00b7}, 3149{0x8998, 0x008f}, {0x8999, 0x0080}, {0x899a, 0x0032}, 3150{0x899b, 0x00c1}, {0x899c, 0x0000}, {0x899d, 0x0026}, 3151{0x899e, 0x0006}, {0x899f, 0x00b7}, {0x89a0, 0x008f}, 3152{0x89a1, 0x007c}, {0x89a2, 0x007e}, {0x89a3, 0x0089}, 3153{0x89a4, 0x00c9}, {0x89a5, 0x00c1}, {0x89a6, 0x0001}, 3154{0x89a7, 0x0027}, {0x89a8, 0x0018}, {0x89a9, 0x00c1}, 3155{0x89aa, 0x0002}, {0x89ab, 0x0027}, {0x89ac, 0x000c}, 3156{0x89ad, 0x00c1}, {0x89ae, 0x0003}, {0x89af, 0x0027}, 3157{0x89b0, 0x0000}, {0x89b1, 0x00f6}, {0x89b2, 0x008f}, 3158{0x89b3, 0x0080}, {0x89b4, 0x0005}, {0x89b5, 0x0005}, 3159{0x89b6, 0x00f7}, {0x89b7, 0x008f}, {0x89b8, 0x0080}, 3160{0x89b9, 0x00f6}, {0x89ba, 0x008f}, {0x89bb, 0x0080}, 3161{0x89bc, 0x0005}, {0x89bd, 0x0005}, {0x89be, 0x00f7}, 3162{0x89bf, 0x008f}, {0x89c0, 0x0080}, {0x89c1, 0x00f6}, 3163{0x89c2, 0x008f}, {0x89c3, 0x0080}, {0x89c4, 0x0005}, 3164{0x89c5, 0x0005}, {0x89c6, 0x00f7}, {0x89c7, 0x008f}, 3165{0x89c8, 0x0080}, {0x89c9, 0x00f6}, {0x89ca, 0x008f}, 3166{0x89cb, 0x0080}, {0x89cc, 0x0053}, {0x89cd, 0x00f4}, 3167{0x89ce, 0x0012}, {0x89cf, 0x0007}, {0x89d0, 0x001b}, 3168{0x89d1, 0x00b7}, {0x89d2, 0x0012}, {0x89d3, 0x0007}, 3169{0x89d4, 0x0039}, {0x89d5, 0x00ce}, {0x89d6, 0x008f}, 3170{0x89d7, 0x0070}, {0x89d8, 0x00a6}, {0x89d9, 0x0000}, 3171{0x89da, 0x0018}, {0x89db, 0x00e6}, {0x89dc, 0x0000}, 3172{0x89dd, 0x0018}, {0x89de, 0x00a7}, {0x89df, 0x0000}, 3173{0x89e0, 0x00e7}, {0x89e1, 0x0000}, {0x89e2, 0x00a6}, 3174{0x89e3, 0x0001}, {0x89e4, 0x0018}, {0x89e5, 0x00e6}, 3175{0x89e6, 0x0001}, {0x89e7, 0x0018}, {0x89e8, 0x00a7}, 3176{0x89e9, 0x0001}, {0x89ea, 0x00e7}, {0x89eb, 0x0001}, 3177{0x89ec, 0x00a6}, {0x89ed, 0x0002}, {0x89ee, 0x0018}, 3178{0x89ef, 0x00e6}, {0x89f0, 0x0002}, {0x89f1, 0x0018}, 3179{0x89f2, 0x00a7}, {0x89f3, 0x0002}, {0x89f4, 0x00e7}, 3180{0x89f5, 0x0002}, {0x89f6, 0x0039}, {0x89f7, 0x00a6}, 3181{0x89f8, 0x0000}, {0x89f9, 0x0084}, {0x89fa, 0x0007}, 3182{0x89fb, 0x00e6}, {0x89fc, 0x0000}, {0x89fd, 0x00c4}, 3183{0x89fe, 0x0038}, {0x89ff, 0x0054}, {0x8a00, 0x0054}, 3184{0x8a01, 0x0054}, {0x8a02, 0x001b}, {0x8a03, 0x00a7}, 3185{0x8a04, 0x0000}, {0x8a05, 0x0039}, {0x8a06, 0x004a}, 3186{0x8a07, 0x0026}, {0x8a08, 0x00fd}, {0x8a09, 0x0039}, 3187{0x8a0a, 0x0096}, {0x8a0b, 0x0022}, {0x8a0c, 0x0084}, 3188{0x8a0d, 0x000f}, {0x8a0e, 0x0097}, {0x8a0f, 0x0022}, 3189{0x8a10, 0x0086}, {0x8a11, 0x0001}, {0x8a12, 0x00b7}, 3190{0x8a13, 0x008f}, {0x8a14, 0x0070}, {0x8a15, 0x00b6}, 3191{0x8a16, 0x0012}, {0x8a17, 0x0007}, {0x8a18, 0x00b7}, 3192{0x8a19, 0x008f}, {0x8a1a, 0x0071}, {0x8a1b, 0x00f6}, 3193{0x8a1c, 0x0012}, {0x8a1d, 0x000c}, {0x8a1e, 0x00c4}, 3194{0x8a1f, 0x000f}, {0x8a20, 0x00c8}, {0x8a21, 0x000f}, 3195{0x8a22, 0x00f7}, {0x8a23, 0x008f}, {0x8a24, 0x0072}, 3196{0x8a25, 0x00f6}, {0x8a26, 0x008f}, {0x8a27, 0x0072}, 3197{0x8a28, 0x00b6}, {0x8a29, 0x008f}, {0x8a2a, 0x0071}, 3198{0x8a2b, 0x0084}, {0x8a2c, 0x0003}, {0x8a2d, 0x0027}, 3199{0x8a2e, 0x0014}, {0x8a2f, 0x0081}, {0x8a30, 0x0001}, 3200{0x8a31, 0x0027}, {0x8a32, 0x001c}, {0x8a33, 0x0081}, 3201{0x8a34, 0x0002}, {0x8a35, 0x0027}, {0x8a36, 0x0024}, 3202{0x8a37, 0x00f4}, {0x8a38, 0x008f}, {0x8a39, 0x0070}, 3203{0x8a3a, 0x0027}, {0x8a3b, 0x002a}, {0x8a3c, 0x0096}, 3204{0x8a3d, 0x0022}, {0x8a3e, 0x008a}, {0x8a3f, 0x0080}, 3205{0x8a40, 0x007e}, {0x8a41, 0x008a}, {0x8a42, 0x0064}, 3206{0x8a43, 0x00f4}, {0x8a44, 0x008f}, {0x8a45, 0x0070}, 3207{0x8a46, 0x0027}, {0x8a47, 0x001e}, {0x8a48, 0x0096}, 3208{0x8a49, 0x0022}, {0x8a4a, 0x008a}, {0x8a4b, 0x0010}, 3209{0x8a4c, 0x007e}, {0x8a4d, 0x008a}, {0x8a4e, 0x0064}, 3210{0x8a4f, 0x00f4}, {0x8a50, 0x008f}, {0x8a51, 0x0070}, 3211{0x8a52, 0x0027}, {0x8a53, 0x0012}, {0x8a54, 0x0096}, 3212{0x8a55, 0x0022}, {0x8a56, 0x008a}, {0x8a57, 0x0020}, 3213{0x8a58, 0x007e}, {0x8a59, 0x008a}, {0x8a5a, 0x0064}, 3214{0x8a5b, 0x00f4}, {0x8a5c, 0x008f}, {0x8a5d, 0x0070}, 3215{0x8a5e, 0x0027}, {0x8a5f, 0x0006}, {0x8a60, 0x0096}, 3216{0x8a61, 0x0022}, {0x8a62, 0x008a}, {0x8a63, 0x0040}, 3217{0x8a64, 0x0097}, {0x8a65, 0x0022}, {0x8a66, 0x0074}, 3218{0x8a67, 0x008f}, {0x8a68, 0x0071}, {0x8a69, 0x0074}, 3219{0x8a6a, 0x008f}, {0x8a6b, 0x0071}, {0x8a6c, 0x0078}, 3220{0x8a6d, 0x008f}, {0x8a6e, 0x0070}, {0x8a6f, 0x00b6}, 3221{0x8a70, 0x008f}, {0x8a71, 0x0070}, {0x8a72, 0x0085}, 3222{0x8a73, 0x0010}, {0x8a74, 0x0027}, {0x8a75, 0x00af}, 3223{0x8a76, 0x00d6}, {0x8a77, 0x0022}, {0x8a78, 0x00c4}, 3224{0x8a79, 0x0010}, {0x8a7a, 0x0058}, {0x8a7b, 0x00b6}, 3225{0x8a7c, 0x0012}, {0x8a7d, 0x0070}, {0x8a7e, 0x0081}, 3226{0x8a7f, 0x00e4}, {0x8a80, 0x0027}, {0x8a81, 0x0036}, 3227{0x8a82, 0x0081}, {0x8a83, 0x00e1}, {0x8a84, 0x0026}, 3228{0x8a85, 0x000c}, {0x8a86, 0x0096}, {0x8a87, 0x0022}, 3229{0x8a88, 0x0084}, {0x8a89, 0x0020}, {0x8a8a, 0x0044}, 3230{0x8a8b, 0x001b}, {0x8a8c, 0x00d6}, {0x8a8d, 0x0022}, 3231{0x8a8e, 0x00c4}, {0x8a8f, 0x00cf}, {0x8a90, 0x0020}, 3232{0x8a91, 0x0023}, {0x8a92, 0x0058}, {0x8a93, 0x0081}, 3233{0x8a94, 0x00c6}, {0x8a95, 0x0026}, {0x8a96, 0x000d}, 3234{0x8a97, 0x0096}, {0x8a98, 0x0022}, {0x8a99, 0x0084}, 3235{0x8a9a, 0x0040}, {0x8a9b, 0x0044}, {0x8a9c, 0x0044}, 3236{0x8a9d, 0x001b}, {0x8a9e, 0x00d6}, {0x8a9f, 0x0022}, 3237{0x8aa0, 0x00c4}, {0x8aa1, 0x00af}, {0x8aa2, 0x0020}, 3238{0x8aa3, 0x0011}, {0x8aa4, 0x0058}, {0x8aa5, 0x0081}, 3239{0x8aa6, 0x0027}, {0x8aa7, 0x0026}, {0x8aa8, 0x000f}, 3240{0x8aa9, 0x0096}, {0x8aaa, 0x0022}, {0x8aab, 0x0084}, 3241{0x8aac, 0x0080}, {0x8aad, 0x0044}, {0x8aae, 0x0044}, 3242{0x8aaf, 0x0044}, {0x8ab0, 0x001b}, {0x8ab1, 0x00d6}, 3243{0x8ab2, 0x0022}, {0x8ab3, 0x00c4}, {0x8ab4, 0x006f}, 3244{0x8ab5, 0x001b}, {0x8ab6, 0x0097}, {0x8ab7, 0x0022}, 3245{0x8ab8, 0x0039}, {0x8ab9, 0x0027}, {0x8aba, 0x000c}, 3246{0x8abb, 0x007c}, {0x8abc, 0x0082}, {0x8abd, 0x0006}, 3247{0x8abe, 0x00bd}, {0x8abf, 0x00d9}, {0x8ac0, 0x00ed}, 3248{0x8ac1, 0x00b6}, {0x8ac2, 0x0082}, {0x8ac3, 0x0007}, 3249{0x8ac4, 0x007e}, {0x8ac5, 0x008a}, {0x8ac6, 0x00b9}, 3250{0x8ac7, 0x007f}, {0x8ac8, 0x0082}, {0x8ac9, 0x0006}, 3251{0x8aca, 0x0039}, { 0x0, 0x0 } 3252}; 3253 3254 3255/* phy types */ 3256#define CAS_PHY_UNKNOWN 0x00 3257#define CAS_PHY_SERDES 0x01 3258#define CAS_PHY_MII_MDIO0 0x02 3259#define CAS_PHY_MII_MDIO1 0x04 3260#define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1)) 3261 3262/* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE 3263 * is the actual size. the default index for the various rings is 3264 * 8. NOTE: there a bunch of alignment constraints for the rings. to 3265 * deal with that, i just allocate rings to create the desired 3266 * alignment. here are the constraints: 3267 * RX DESC and COMP rings must be 8KB aligned 3268 * TX DESC must be 2KB aligned. 3269 * if you change the numbers, be cognizant of how the alignment will change 3270 * in INIT_BLOCK as well. 3271 */ 3272 3273#define DESC_RING_I_TO_S(x) (32*(1 << (x))) 3274#define COMP_RING_I_TO_S(x) (128*(1 << (x))) 3275#define TX_DESC_RING_INDEX 4 /* 512 = 8k */ 3276#define RX_DESC_RING_INDEX 4 /* 512 = 8k */ 3277#define RX_COMP_RING_INDEX 4 /* 2048 = 64k: should be 4x rx ring size */ 3278 3279#if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0) 3280#error TX_DESC_RING_INDEX must be between 0 and 8 3281#endif 3282 3283#if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0) 3284#error RX_DESC_RING_INDEX must be between 0 and 8 3285#endif 3286 3287#if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0) 3288#error RX_COMP_RING_INDEX must be between 0 and 8 3289#endif 3290 3291#define N_TX_RINGS MAX_TX_RINGS /* for QoS */ 3292#define N_TX_RINGS_MASK MAX_TX_RINGS_MASK 3293#define N_RX_DESC_RINGS MAX_RX_DESC_RINGS /* 1 for ipsec */ 3294#define N_RX_COMP_RINGS 0x1 /* for mult. PCI interrupts */ 3295 3296/* number of flows that can go through re-assembly */ 3297#define N_RX_FLOWS 64 3298 3299#define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX) 3300#define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX) 3301#define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX) 3302#define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX 3303#define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX 3304#define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX 3305#define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE 3306#define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE 3307#define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE 3308 3309/* convert values */ 3310#define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK)) 3311#define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT)) 3312#define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \ 3313 TX_CFG_DESC_RINGN_SHIFT(y)) & \ 3314 TX_CFG_DESC_RINGN_MASK(y)) 3315 3316/* min is 2k, but we can't do jumbo frames unless it's at least 8k */ 3317#define CAS_MIN_PAGE_SHIFT 11 /* 2048 */ 3318#define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */ 3319#define CAS_MAX_PAGE_SHIFT 14 /* 16384 */ 3320 3321#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in 3322 bytes. 0 - 9256 */ 3323#define TX_DESC_BUFLEN_SHIFT 0 3324#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. # 3325 of bytes to be 3326 skipped before 3327 csum calc begins. 3328 value must be 3329 even */ 3330#define TX_DESC_CSUM_START_SHIFT 15 3331#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff. 3332 byte offset w/in 3333 the pkt for the 3334 1st csum byte. 3335 must be > 8 */ 3336#define TX_DESC_CSUM_STUFF_SHIFT 21 3337#define TX_DESC_CSUM_EN 0x0000000020000000ULL /* enable checksum */ 3338#define TX_DESC_EOF 0x0000000040000000ULL /* end of frame */ 3339#define TX_DESC_SOF 0x0000000080000000ULL /* start of frame */ 3340#define TX_DESC_INTME 0x0000000100000000ULL /* interrupt me */ 3341#define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only. 3342 CRC will not be 3343 inserted into 3344 outgoing frame. */ 3345struct cas_tx_desc { 3346 u64 control; 3347 u64 buffer; 3348}; 3349 3350/* descriptor ring for free buffers contains page-sized buffers. the index 3351 * value is not used by the hw in any way. it's just stored and returned in 3352 * the completion ring. 3353 */ 3354struct cas_rx_desc { 3355 u64 index; 3356 u64 buffer; 3357}; 3358 3359/* received packets are put on the completion ring. */ 3360/* word 1 */ 3361#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL 3362#define RX_COMP1_DATA_SIZE_SHIFT 13 3363#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL 3364#define RX_COMP1_DATA_OFF_SHIFT 27 3365#define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL 3366#define RX_COMP1_DATA_INDEX_SHIFT 41 3367#define RX_COMP1_SKIP_MASK 0x0180000000000000ULL 3368#define RX_COMP1_SKIP_SHIFT 55 3369#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL 3370#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL 3371#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL 3372#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL 3373#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL 3374#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL 3375#define RX_COMP1_TYPE_SHIFT 62 3376 3377/* word 2 */ 3378#define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL 3379#define RX_COMP2_NEXT_INDEX_SHIFT 21 3380#define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL 3381#define RX_COMP2_HDR_SIZE_SHIFT 35 3382#define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL 3383#define RX_COMP2_HDR_OFF_SHIFT 44 3384#define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL 3385#define RX_COMP2_HDR_INDEX_SHIFT 50 3386 3387/* word 3 */ 3388#define RX_COMP3_SMALL_PKT 0x0000000000000001ULL 3389#define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL 3390#define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL 3391#define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL 3392#define RX_COMP3_CSUM_START_SHIFT 12 3393#define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL 3394#define RX_COMP3_FLOWID_SHIFT 19 3395#define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL 3396#define RX_COMP3_OPCODE_SHIFT 25 3397#define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL 3398#define RX_COMP3_NO_ASSIST 0x0000000020000000ULL 3399#define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL 3400#define RX_COMP3_LOAD_BAL_SHIFT 35 3401#define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL /* cas+ */ 3402#define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL /* cas */ 3403#define RX_COMP3_L3_HEAD_OFF_SHIFT 41 3404#define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL /* cas+ */ 3405#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42 3406#define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL 3407#define RX_COMP3_SAP_SHIFT 48 3408 3409/* word 4 */ 3410#define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL 3411#define RX_COMP4_TCP_CSUM_SHIFT 0 3412#define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL 3413#define RX_COMP4_PKT_LEN_SHIFT 16 3414#define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL 3415#define RX_COMP4_PERFECT_MATCH_SHIFT 30 3416#define RX_COMP4_ZERO 0x0000080000000000ULL 3417#define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL 3418#define RX_COMP4_HASH_VAL_SHIFT 44 3419#define RX_COMP4_HASH_PASS 0x1000000000000000ULL 3420#define RX_COMP4_BAD 0x4000000000000000ULL 3421#define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL 3422 3423/* we encode the following: ring/index/release. only 14 bits 3424 * are usable. 3425 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and 3426 * MAX_RX_DESC_RINGS. */ 3427#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL 3428#define RX_INDEX_NUM_SHIFT 0 3429#define RX_INDEX_RING_MASK 0x0000000000001000ULL 3430#define RX_INDEX_RING_SHIFT 12 3431#define RX_INDEX_RELEASE 0x0000000000002000ULL 3432 3433struct cas_rx_comp { 3434 u64 word1; 3435 u64 word2; 3436 u64 word3; 3437 u64 word4; 3438}; 3439 3440enum link_state { 3441 link_down = 0, /* No link, will retry */ 3442 link_aneg, /* Autoneg in progress */ 3443 link_force_try, /* Try Forced link speed */ 3444 link_force_ret, /* Forced mode worked, retrying autoneg */ 3445 link_force_ok, /* Stay in forced mode */ 3446 link_up /* Link is up */ 3447}; 3448 3449typedef struct cas_page { 3450 struct list_head list; 3451 struct page *buffer; 3452 dma_addr_t dma_addr; 3453 int used; 3454} cas_page_t; 3455 3456 3457/* some alignment constraints: 3458 * TX DESC, RX DESC, and RX COMP must each be 8K aligned. 3459 * TX COMPWB must be 8-byte aligned. 3460 * to accomplish this, here's what we do: 3461 * 3462 * INIT_BLOCK_RX_COMP = 64k (already aligned) 3463 * INIT_BLOCK_RX_DESC = 8k 3464 * INIT_BLOCK_TX = 8k 3465 * INIT_BLOCK_RX1_DESC = 8k 3466 * TX COMPWB 3467 */ 3468#define INIT_BLOCK_TX (TX_DESC_RING_SIZE) 3469#define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE) 3470#define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE) 3471 3472struct cas_init_block { 3473 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP]; 3474 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC]; 3475 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX]; 3476 u64 tx_compwb; 3477}; 3478 3479/* tiny buffers to deal with target abort issue. we allocate a bit 3480 * over so that we don't have target abort issues with these buffers 3481 * as well. 3482 */ 3483#define TX_TINY_BUF_LEN 0x100 3484#define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN) 3485 3486struct cas_tiny_count { 3487 int nbufs; 3488 int used; 3489}; 3490 3491struct cas { 3492 spinlock_t lock; /* for most bits */ 3493 spinlock_t tx_lock[N_TX_RINGS]; /* tx bits */ 3494 spinlock_t stat_lock[N_TX_RINGS + 1]; /* for stat gathering */ 3495 spinlock_t rx_inuse_lock; /* rx inuse list */ 3496 spinlock_t rx_spare_lock; /* rx spare list */ 3497 3498 void __iomem *regs; 3499 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS]; 3500 int rx_old[N_RX_DESC_RINGS]; 3501 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS]; 3502 int rx_last[N_RX_DESC_RINGS]; 3503 3504 /* Set when chip is actually in operational state 3505 * (ie. not power managed) */ 3506 int hw_running; 3507 int opened; 3508 struct mutex pm_mutex; /* open/close/suspend/resume */ 3509 3510 struct cas_init_block *init_block; 3511 struct cas_tx_desc *init_txds[MAX_TX_RINGS]; 3512 struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS]; 3513 struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS]; 3514 3515 /* we use sk_buffs for tx and pages for rx. the rx skbuffs 3516 * are there for flow re-assembly. */ 3517 struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE]; 3518 struct sk_buff_head rx_flows[N_RX_FLOWS]; 3519 cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE]; 3520 struct list_head rx_spare_list, rx_inuse_list; 3521 int rx_spares_needed; 3522 3523 /* for small packets when copying would be quicker than 3524 mapping */ 3525 struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE]; 3526 u8 *tx_tiny_bufs[N_TX_RINGS]; 3527 3528 u32 msg_enable; 3529 3530 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */ 3531 struct net_device_stats net_stats[N_TX_RINGS + 1]; 3532 3533 u32 pci_cfg[64 >> 2]; 3534 u8 pci_revision; 3535 3536 int phy_type; 3537 int phy_addr; 3538 u32 phy_id; 3539#define CAS_FLAG_1000MB_CAP 0x00000001 3540#define CAS_FLAG_REG_PLUS 0x00000002 3541#define CAS_FLAG_TARGET_ABORT 0x00000004 3542#define CAS_FLAG_SATURN 0x00000008 3543#define CAS_FLAG_RXD_POST_MASK 0x000000F0 3544#define CAS_FLAG_RXD_POST_SHIFT 4 3545#define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \ 3546 CAS_FLAG_RXD_POST_MASK) 3547#define CAS_FLAG_ENTROPY_DEV 0x00000100 3548#define CAS_FLAG_NO_HW_CSUM 0x00000200 3549 u32 cas_flags; 3550 int packet_min; /* minimum packet size */ 3551 int tx_fifo_size; 3552 int rx_fifo_size; 3553 int rx_pause_off; 3554 int rx_pause_on; 3555 int crc_size; /* 4 if half-duplex */ 3556 3557 int pci_irq_INTC; 3558 int min_frame_size; 3559 3560 /* page size allocation */ 3561 int page_size; 3562 int page_order; 3563 int mtu_stride; 3564 3565 u32 mac_rx_cfg; 3566 3567 /* Autoneg & PHY control */ 3568 int link_cntl; 3569 int link_fcntl; 3570 enum link_state lstate; 3571 struct timer_list link_timer; 3572 int timer_ticks; 3573 struct work_struct reset_task; 3574 atomic_t reset_task_pending; 3575 atomic_t reset_task_pending_mtu; 3576 atomic_t reset_task_pending_spare; 3577 atomic_t reset_task_pending_all; 3578 3579#ifdef CONFIG_CASSINI_QGE_DEBUG 3580 atomic_t interrupt_seen; /* 1 if any interrupts are getting through */ 3581#endif 3582 3583#define LINK_TRANSITION_UNKNOWN 0 3584#define LINK_TRANSITION_ON_FAILURE 1 3585#define LINK_TRANSITION_STILL_FAILED 2 3586#define LINK_TRANSITION_LINK_UP 3 3587#define LINK_TRANSITION_LINK_CONFIG 4 3588#define LINK_TRANSITION_LINK_DOWN 5 3589#define LINK_TRANSITION_REQUESTED_RESET 6 3590 int link_transition; 3591 int link_transition_jiffies_valid; 3592 unsigned long link_transition_jiffies; 3593 3594 /* Tuning */ 3595 u8 orig_cacheline_size; /* value when loaded */ 3596#define CAS_PREF_CACHELINE_SIZE 0x20 /* Minimum desired */ 3597 3598 /* Diagnostic counters and state. */ 3599 int casreg_len; /* reg-space size for dumping */ 3600 u64 pause_entered; 3601 u16 pause_last_time_recvd; 3602 3603 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS]; 3604 struct pci_dev *pdev; 3605 struct net_device *dev; 3606}; 3607 3608#define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1)) 3609#define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1)) 3610#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1)) 3611 3612#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \ 3613 (TX_DESC_RINGN_SIZE(r) - (x) + (y))) 3614 3615#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \ 3616 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \ 3617 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1) 3618 3619#define CAS_ALIGN(addr, align) \ 3620 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1)) 3621 3622#define RX_FIFO_SIZE 16384 3623#define EXPANSION_ROM_SIZE 65536 3624 3625#define CAS_MC_EXACT_MATCH_SIZE 15 3626#define CAS_MC_HASH_SIZE 256 3627#define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \ 3628 CAS_MC_HASH_SIZE) 3629 3630#define TX_TARGET_ABORT_LEN 0x20 3631#define RX_SWIVEL_OFF_VAL 0x2 3632#define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1) 3633#define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1) 3634#define RX_BLANK_INTR_PKT_VAL 0x05 3635#define RX_BLANK_INTR_TIME_VAL 0x0F 3636#define HP_TCP_THRESH_VAL 1530 /* reduce to enable reassembly */ 3637 3638#define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1) 3639#define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2) 3640 3641#endif /* _CASSINI_H */ 3642