1/* 2 * drivers/mtd/nand/au1550nd.c 3 * 4 * Copyright (C) 2004 Embedded Edge, LLC 5 * 6 * $Id: au1550nd.c,v 1.1.1.1 2007/08/03 18:52:44 Exp $ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14#include <linux/slab.h> 15#include <linux/init.h> 16#include <linux/module.h> 17#include <linux/interrupt.h> 18#include <linux/mtd/mtd.h> 19#include <linux/mtd/nand.h> 20#include <linux/mtd/partitions.h> 21#include <linux/version.h> 22#include <asm/io.h> 23 24#include <asm/mach-au1x00/au1xxx.h> 25 26/* 27 * MTD structure for NAND controller 28 */ 29static struct mtd_info *au1550_mtd = NULL; 30static void __iomem *p_nand; 31static int nand_width = 1; /* default x8 */ 32static void (*au1550_write_byte)(struct mtd_info *, u_char); 33 34/* 35 * Define partitions for flash device 36 */ 37static const struct mtd_partition partition_info[] = { 38 { 39 .name = "NAND FS 0", 40 .offset = 0, 41 .size = 8 * 1024 * 1024}, 42 { 43 .name = "NAND FS 1", 44 .offset = MTDPART_OFS_APPEND, 45 .size = MTDPART_SIZ_FULL} 46}; 47 48/** 49 * au_read_byte - read one byte from the chip 50 * @mtd: MTD device structure 51 * 52 * read function for 8bit buswith 53 */ 54static u_char au_read_byte(struct mtd_info *mtd) 55{ 56 struct nand_chip *this = mtd->priv; 57 u_char ret = readb(this->IO_ADDR_R); 58 au_sync(); 59 return ret; 60} 61 62/** 63 * au_write_byte - write one byte to the chip 64 * @mtd: MTD device structure 65 * @byte: pointer to data byte to write 66 * 67 * write function for 8it buswith 68 */ 69static void au_write_byte(struct mtd_info *mtd, u_char byte) 70{ 71 struct nand_chip *this = mtd->priv; 72 writeb(byte, this->IO_ADDR_W); 73 au_sync(); 74} 75 76/** 77 * au_read_byte16 - read one byte endianess aware from the chip 78 * @mtd: MTD device structure 79 * 80 * read function for 16bit buswith with 81 * endianess conversion 82 */ 83static u_char au_read_byte16(struct mtd_info *mtd) 84{ 85 struct nand_chip *this = mtd->priv; 86 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); 87 au_sync(); 88 return ret; 89} 90 91/** 92 * au_write_byte16 - write one byte endianess aware to the chip 93 * @mtd: MTD device structure 94 * @byte: pointer to data byte to write 95 * 96 * write function for 16bit buswith with 97 * endianess conversion 98 */ 99static void au_write_byte16(struct mtd_info *mtd, u_char byte) 100{ 101 struct nand_chip *this = mtd->priv; 102 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); 103 au_sync(); 104} 105 106/** 107 * au_read_word - read one word from the chip 108 * @mtd: MTD device structure 109 * 110 * read function for 16bit buswith without 111 * endianess conversion 112 */ 113static u16 au_read_word(struct mtd_info *mtd) 114{ 115 struct nand_chip *this = mtd->priv; 116 u16 ret = readw(this->IO_ADDR_R); 117 au_sync(); 118 return ret; 119} 120 121/** 122 * au_write_buf - write buffer to chip 123 * @mtd: MTD device structure 124 * @buf: data buffer 125 * @len: number of bytes to write 126 * 127 * write function for 8bit buswith 128 */ 129static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 130{ 131 int i; 132 struct nand_chip *this = mtd->priv; 133 134 for (i = 0; i < len; i++) { 135 writeb(buf[i], this->IO_ADDR_W); 136 au_sync(); 137 } 138} 139 140/** 141 * au_read_buf - read chip data into buffer 142 * @mtd: MTD device structure 143 * @buf: buffer to store date 144 * @len: number of bytes to read 145 * 146 * read function for 8bit buswith 147 */ 148static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) 149{ 150 int i; 151 struct nand_chip *this = mtd->priv; 152 153 for (i = 0; i < len; i++) { 154 buf[i] = readb(this->IO_ADDR_R); 155 au_sync(); 156 } 157} 158 159/** 160 * au_verify_buf - Verify chip data against buffer 161 * @mtd: MTD device structure 162 * @buf: buffer containing the data to compare 163 * @len: number of bytes to compare 164 * 165 * verify function for 8bit buswith 166 */ 167static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) 168{ 169 int i; 170 struct nand_chip *this = mtd->priv; 171 172 for (i = 0; i < len; i++) { 173 if (buf[i] != readb(this->IO_ADDR_R)) 174 return -EFAULT; 175 au_sync(); 176 } 177 178 return 0; 179} 180 181/** 182 * au_write_buf16 - write buffer to chip 183 * @mtd: MTD device structure 184 * @buf: data buffer 185 * @len: number of bytes to write 186 * 187 * write function for 16bit buswith 188 */ 189static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) 190{ 191 int i; 192 struct nand_chip *this = mtd->priv; 193 u16 *p = (u16 *) buf; 194 len >>= 1; 195 196 for (i = 0; i < len; i++) { 197 writew(p[i], this->IO_ADDR_W); 198 au_sync(); 199 } 200 201} 202 203/** 204 * au_read_buf16 - read chip data into buffer 205 * @mtd: MTD device structure 206 * @buf: buffer to store date 207 * @len: number of bytes to read 208 * 209 * read function for 16bit buswith 210 */ 211static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) 212{ 213 int i; 214 struct nand_chip *this = mtd->priv; 215 u16 *p = (u16 *) buf; 216 len >>= 1; 217 218 for (i = 0; i < len; i++) { 219 p[i] = readw(this->IO_ADDR_R); 220 au_sync(); 221 } 222} 223 224/** 225 * au_verify_buf16 - Verify chip data against buffer 226 * @mtd: MTD device structure 227 * @buf: buffer containing the data to compare 228 * @len: number of bytes to compare 229 * 230 * verify function for 16bit buswith 231 */ 232static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) 233{ 234 int i; 235 struct nand_chip *this = mtd->priv; 236 u16 *p = (u16 *) buf; 237 len >>= 1; 238 239 for (i = 0; i < len; i++) { 240 if (p[i] != readw(this->IO_ADDR_R)) 241 return -EFAULT; 242 au_sync(); 243 } 244 return 0; 245} 246 247/* Select the chip by setting nCE to low */ 248#define NAND_CTL_SETNCE 1 249/* Deselect the chip by setting nCE to high */ 250#define NAND_CTL_CLRNCE 2 251/* Select the command latch by setting CLE to high */ 252#define NAND_CTL_SETCLE 3 253/* Deselect the command latch by setting CLE to low */ 254#define NAND_CTL_CLRCLE 4 255/* Select the address latch by setting ALE to high */ 256#define NAND_CTL_SETALE 5 257/* Deselect the address latch by setting ALE to low */ 258#define NAND_CTL_CLRALE 6 259 260static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) 261{ 262 register struct nand_chip *this = mtd->priv; 263 264 switch (cmd) { 265 266 case NAND_CTL_SETCLE: 267 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD; 268 break; 269 270 case NAND_CTL_CLRCLE: 271 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 272 break; 273 274 case NAND_CTL_SETALE: 275 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR; 276 break; 277 278 case NAND_CTL_CLRALE: 279 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA; 280 udelay(1); 281 break; 282 283 case NAND_CTL_SETNCE: 284 /* assert (force assert) chip enable */ 285 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL); 286 break; 287 288 case NAND_CTL_CLRNCE: 289 /* deassert chip enable */ 290 au_writel(0, MEM_STNDCTL); 291 break; 292 } 293 294 this->IO_ADDR_R = this->IO_ADDR_W; 295 296 /* Drain the writebuffer */ 297 au_sync(); 298} 299 300int au1550_device_ready(struct mtd_info *mtd) 301{ 302 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0; 303 au_sync(); 304 return ret; 305} 306 307/** 308 * au1550_select_chip - control -CE line 309 * Forbid driving -CE manually permitting the NAND controller to do this. 310 * Keeping -CE asserted during the whole sector reads interferes with the 311 * NOR flash and PCMCIA drivers as it causes contention on the static bus. 312 * We only have to hold -CE low for the NAND read commands since the flash 313 * chip needs it to be asserted during chip not ready time but the NAND 314 * controller keeps it released. 315 * 316 * @mtd: MTD device structure 317 * @chip: chipnumber to select, -1 for deselect 318 */ 319static void au1550_select_chip(struct mtd_info *mtd, int chip) 320{ 321} 322 323/** 324 * au1550_command - Send command to NAND device 325 * @mtd: MTD device structure 326 * @command: the command to be sent 327 * @column: the column address for this command, -1 if none 328 * @page_addr: the page address for this command, -1 if none 329 */ 330static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) 331{ 332 register struct nand_chip *this = mtd->priv; 333 int ce_override = 0, i; 334 ulong flags; 335 336 /* Begin command latch cycle */ 337 au1550_hwcontrol(mtd, NAND_CTL_SETCLE); 338 /* 339 * Write out the command to the device. 340 */ 341 if (command == NAND_CMD_SEQIN) { 342 int readcmd; 343 344 if (column >= mtd->writesize) { 345 /* OOB area */ 346 column -= mtd->writesize; 347 readcmd = NAND_CMD_READOOB; 348 } else if (column < 256) { 349 /* First 256 bytes --> READ0 */ 350 readcmd = NAND_CMD_READ0; 351 } else { 352 column -= 256; 353 readcmd = NAND_CMD_READ1; 354 } 355 au1550_write_byte(mtd, readcmd); 356 } 357 au1550_write_byte(mtd, command); 358 359 /* Set ALE and clear CLE to start address cycle */ 360 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); 361 362 if (column != -1 || page_addr != -1) { 363 au1550_hwcontrol(mtd, NAND_CTL_SETALE); 364 365 /* Serially input address */ 366 if (column != -1) { 367 /* Adjust columns for 16 bit buswidth */ 368 if (this->options & NAND_BUSWIDTH_16) 369 column >>= 1; 370 au1550_write_byte(mtd, column); 371 } 372 if (page_addr != -1) { 373 au1550_write_byte(mtd, (u8)(page_addr & 0xff)); 374 375 if (command == NAND_CMD_READ0 || 376 command == NAND_CMD_READ1 || 377 command == NAND_CMD_READOOB) { 378 /* 379 * NAND controller will release -CE after 380 * the last address byte is written, so we'll 381 * have to forcibly assert it. No interrupts 382 * are allowed while we do this as we don't 383 * want the NOR flash or PCMCIA drivers to 384 * steal our precious bytes of data... 385 */ 386 ce_override = 1; 387 local_irq_save(flags); 388 au1550_hwcontrol(mtd, NAND_CTL_SETNCE); 389 } 390 391 au1550_write_byte(mtd, (u8)(page_addr >> 8)); 392 393 /* One more address cycle for devices > 32MiB */ 394 if (this->chipsize > (32 << 20)) 395 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f)); 396 } 397 /* Latch in address */ 398 au1550_hwcontrol(mtd, NAND_CTL_CLRALE); 399 } 400 401 /* 402 * Program and erase have their own busy handlers. 403 * Status and sequential in need no delay. 404 */ 405 switch (command) { 406 407 case NAND_CMD_PAGEPROG: 408 case NAND_CMD_ERASE1: 409 case NAND_CMD_ERASE2: 410 case NAND_CMD_SEQIN: 411 case NAND_CMD_STATUS: 412 return; 413 414 case NAND_CMD_RESET: 415 break; 416 417 case NAND_CMD_READ0: 418 case NAND_CMD_READ1: 419 case NAND_CMD_READOOB: 420 /* Check if we're really driving -CE low (just in case) */ 421 if (unlikely(!ce_override)) 422 break; 423 424 /* Apply a short delay always to ensure that we do wait tWB. */ 425 ndelay(100); 426 /* Wait for a chip to become ready... */ 427 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) 428 udelay(1); 429 430 /* Release -CE and re-enable interrupts. */ 431 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); 432 local_irq_restore(flags); 433 return; 434 } 435 /* Apply this short delay always to ensure that we do wait tWB. */ 436 ndelay(100); 437 438 while(!this->dev_ready(mtd)); 439} 440 441 442/* 443 * Main initialization routine 444 */ 445static int __init au1xxx_nand_init(void) 446{ 447 struct nand_chip *this; 448 u16 boot_swapboot = 0; /* default value */ 449 int retval; 450 u32 mem_staddr; 451 u32 nand_phys; 452 453 /* Allocate memory for MTD device structure and private data */ 454 au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); 455 if (!au1550_mtd) { 456 printk("Unable to allocate NAND MTD dev structure.\n"); 457 return -ENOMEM; 458 } 459 460 /* Get pointer to private data */ 461 this = (struct nand_chip *)(&au1550_mtd[1]); 462 463 /* Initialize structures */ 464 memset(au1550_mtd, 0, sizeof(struct mtd_info)); 465 memset(this, 0, sizeof(struct nand_chip)); 466 467 /* Link the private data with the MTD structure */ 468 au1550_mtd->priv = this; 469 au1550_mtd->owner = THIS_MODULE; 470 471 472 /* MEM_STNDCTL: disable ints, disable nand boot */ 473 au_writel(0, MEM_STNDCTL); 474 475#ifdef CONFIG_MIPS_PB1550 476 /* set gpio206 high */ 477 au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR); 478 479 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1); 480 switch (boot_swapboot) { 481 case 0: 482 case 2: 483 case 8: 484 case 0xC: 485 case 0xD: 486 /* x16 NAND Flash */ 487 nand_width = 0; 488 break; 489 case 1: 490 case 9: 491 case 3: 492 case 0xE: 493 case 0xF: 494 /* x8 NAND Flash */ 495 nand_width = 1; 496 break; 497 default: 498 printk("Pb1550 NAND: bad boot:swap\n"); 499 retval = -EINVAL; 500 goto outmem; 501 } 502#endif 503 504 /* Configure chip-select; normally done by boot code, e.g. YAMON */ 505#ifdef NAND_STCFG 506 if (NAND_CS == 0) { 507 au_writel(NAND_STCFG, MEM_STCFG0); 508 au_writel(NAND_STTIME, MEM_STTIME0); 509 au_writel(NAND_STADDR, MEM_STADDR0); 510 } 511 if (NAND_CS == 1) { 512 au_writel(NAND_STCFG, MEM_STCFG1); 513 au_writel(NAND_STTIME, MEM_STTIME1); 514 au_writel(NAND_STADDR, MEM_STADDR1); 515 } 516 if (NAND_CS == 2) { 517 au_writel(NAND_STCFG, MEM_STCFG2); 518 au_writel(NAND_STTIME, MEM_STTIME2); 519 au_writel(NAND_STADDR, MEM_STADDR2); 520 } 521 if (NAND_CS == 3) { 522 au_writel(NAND_STCFG, MEM_STCFG3); 523 au_writel(NAND_STTIME, MEM_STTIME3); 524 au_writel(NAND_STADDR, MEM_STADDR3); 525 } 526#endif 527 528 /* Locate NAND chip-select in order to determine NAND phys address */ 529 mem_staddr = 0x00000000; 530 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0)) 531 mem_staddr = au_readl(MEM_STADDR0); 532 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1)) 533 mem_staddr = au_readl(MEM_STADDR1); 534 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2)) 535 mem_staddr = au_readl(MEM_STADDR2); 536 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3)) 537 mem_staddr = au_readl(MEM_STADDR3); 538 539 if (mem_staddr == 0x00000000) { 540 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n"); 541 kfree(au1550_mtd); 542 return 1; 543 } 544 nand_phys = (mem_staddr << 4) & 0xFFFC0000; 545 546 p_nand = (void __iomem *)ioremap(nand_phys, 0x1000); 547 548 /* make controller and MTD agree */ 549 if (NAND_CS == 0) 550 nand_width = au_readl(MEM_STCFG0) & (1 << 22); 551 if (NAND_CS == 1) 552 nand_width = au_readl(MEM_STCFG1) & (1 << 22); 553 if (NAND_CS == 2) 554 nand_width = au_readl(MEM_STCFG2) & (1 << 22); 555 if (NAND_CS == 3) 556 nand_width = au_readl(MEM_STCFG3) & (1 << 22); 557 558 /* Set address of hardware control function */ 559 this->dev_ready = au1550_device_ready; 560 this->select_chip = au1550_select_chip; 561 this->cmdfunc = au1550_command; 562 563 /* 30 us command delay time */ 564 this->chip_delay = 30; 565 this->ecc.mode = NAND_ECC_SOFT; 566 567 this->options = NAND_NO_AUTOINCR; 568 569 if (!nand_width) 570 this->options |= NAND_BUSWIDTH_16; 571 572 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte; 573 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte; 574 this->read_word = au_read_word; 575 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf; 576 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf; 577 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf; 578 579 /* Scan to find existence of the device */ 580 if (nand_scan(au1550_mtd, 1)) { 581 retval = -ENXIO; 582 goto outio; 583 } 584 585 /* Register the partitions */ 586 add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info)); 587 588 return 0; 589 590 outio: 591 iounmap((void *)p_nand); 592 593 outmem: 594 kfree(au1550_mtd); 595 return retval; 596} 597 598module_init(au1xxx_nand_init); 599 600/* 601 * Clean up routine 602 */ 603static void __exit au1550_cleanup(void) 604{ 605 struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1]; 606 607 /* Release resources, unregister device */ 608 nand_release(au1550_mtd); 609 610 /* Free the MTD device structure */ 611 kfree(au1550_mtd); 612 613 /* Unmap */ 614 iounmap((void *)p_nand); 615} 616 617module_exit(au1550_cleanup); 618 619MODULE_LICENSE("GPL"); 620MODULE_AUTHOR("Embedded Edge, LLC"); 621MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); 622