1/*
2 * amd76xrom.c
3 *
4 * Normal mappings of chips in physical memory
5 * $Id: amd76xrom.c,v 1.1.1.1 2007/08/03 18:52:43 Exp $
6 */
7
8#include <linux/module.h>
9#include <linux/types.h>
10#include <linux/version.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <asm/io.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/map.h>
16#include <linux/mtd/cfi.h>
17#include <linux/mtd/flashchip.h>
18#include <linux/pci.h>
19#include <linux/pci_ids.h>
20#include <linux/list.h>
21
22
23#define xstr(s) str(s)
24#define str(s) #s
25#define MOD_NAME xstr(KBUILD_BASENAME)
26
27#define ADDRESS_NAME_LEN 18
28
29#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */
30
31struct amd76xrom_window {
32	void __iomem *virt;
33	unsigned long phys;
34	unsigned long size;
35	struct list_head maps;
36	struct resource rsrc;
37	struct pci_dev *pdev;
38};
39
40struct amd76xrom_map_info {
41	struct list_head list;
42	struct map_info map;
43	struct mtd_info *mtd;
44	struct resource rsrc;
45	char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
46};
47
48/* The 2 bits controlling the window size are often set to allow reading
49 * the BIOS, but too small to allow writing, since the lock registers are
50 * 4MiB lower in the address space than the data.
51 *
52 * This is intended to prevent flashing the bios, perhaps accidentally.
53 *
54 * This parameter allows the normal driver to over-ride the BIOS settings.
55 *
56 * The bits are 6 and 7.  If both bits are set, it is a 5MiB window.
57 * If only the 7 Bit is set, it is a 4MiB window.  Otherwise, a
58 * 64KiB window.
59 *
60 */
61static uint win_size_bits;
62module_param(win_size_bits, uint, 0);
63MODULE_PARM_DESC(win_size_bits, "ROM window size bits override for 0x43 byte, normally set by BIOS.");
64
65static struct amd76xrom_window amd76xrom_window = {
66	.maps = LIST_HEAD_INIT(amd76xrom_window.maps),
67};
68
69static void amd76xrom_cleanup(struct amd76xrom_window *window)
70{
71	struct amd76xrom_map_info *map, *scratch;
72	u8 byte;
73
74	if (window->pdev) {
75		/* Disable writes through the rom window */
76		pci_read_config_byte(window->pdev, 0x40, &byte);
77		pci_write_config_byte(window->pdev, 0x40, byte & ~1);
78		pci_dev_put(window->pdev);
79	}
80
81	/* Free all of the mtd devices */
82	list_for_each_entry_safe(map, scratch, &window->maps, list) {
83		if (map->rsrc.parent) {
84			release_resource(&map->rsrc);
85		}
86		del_mtd_device(map->mtd);
87		map_destroy(map->mtd);
88		list_del(&map->list);
89		kfree(map);
90	}
91	if (window->rsrc.parent)
92		release_resource(&window->rsrc);
93
94	if (window->virt) {
95		iounmap(window->virt);
96		window->virt = NULL;
97		window->phys = 0;
98		window->size = 0;
99		window->pdev = NULL;
100	}
101}
102
103
104static int __devinit amd76xrom_init_one (struct pci_dev *pdev,
105	const struct pci_device_id *ent)
106{
107	static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
108	u8 byte;
109	struct amd76xrom_window *window = &amd76xrom_window;
110	struct amd76xrom_map_info *map = NULL;
111	unsigned long map_top;
112
113	/* Remember the pci dev I find the window in - already have a ref */
114	window->pdev = pdev;
115
116	/* Enable the selected rom window.  This is often incorrectly
117	 * set up by the BIOS, and the 4MiB offset for the lock registers
118	 * requires the full 5MiB of window space.
119	 *
120	 * This 'write, then read' approach leaves the bits for
121	 * other uses of the hardware info.
122	 */
123	pci_read_config_byte(pdev, 0x43, &byte);
124	pci_write_config_byte(pdev, 0x43, byte | win_size_bits );
125
126	/* Assume the rom window is properly setup, and find it's size */
127	pci_read_config_byte(pdev, 0x43, &byte);
128	if ((byte & ((1<<7)|(1<<6))) == ((1<<7)|(1<<6))) {
129		window->phys = 0xffb00000; /* 5MiB */
130	}
131	else if ((byte & (1<<7)) == (1<<7)) {
132		window->phys = 0xffc00000; /* 4MiB */
133	}
134	else {
135		window->phys = 0xffff0000; /* 64KiB */
136	}
137	window->size = 0xffffffffUL - window->phys + 1UL;
138
139	/*
140	 * Try to reserve the window mem region.  If this fails then
141	 * it is likely due to a fragment of the window being
142	 * "reseved" by the BIOS.  In the case that the
143	 * request_mem_region() fails then once the rom size is
144	 * discovered we will try to reserve the unreserved fragment.
145	 */
146	window->rsrc.name = MOD_NAME;
147	window->rsrc.start = window->phys;
148	window->rsrc.end   = window->phys + window->size - 1;
149	window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
150	if (request_resource(&iomem_resource, &window->rsrc)) {
151		window->rsrc.parent = NULL;
152		printk(KERN_ERR MOD_NAME
153			" %s(): Unable to register resource"
154			" 0x%.16llx-0x%.16llx - kernel bug?\n",
155			__func__,
156			(unsigned long long)window->rsrc.start,
157			(unsigned long long)window->rsrc.end);
158	}
159
160
161	/* Enable writes through the rom window */
162	pci_read_config_byte(pdev, 0x40, &byte);
163	pci_write_config_byte(pdev, 0x40, byte | 1);
164
165
166	/* For write accesses caches are useless */
167	window->virt = ioremap_nocache(window->phys, window->size);
168	if (!window->virt) {
169		printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
170			window->phys, window->size);
171		goto out;
172	}
173
174	/* Get the first address to look for an rom chip at */
175	map_top = window->phys;
176	/* The probe sequence run over the firmware hub lock
177	 * registers sets them to 0x7 (no access).
178	 * Probe at most the last 4M of the address space.
179	 */
180	if (map_top < 0xffc00000) {
181		map_top = 0xffc00000;
182	}
183	/* Loop  through and look for rom chips */
184	while((map_top - 1) < 0xffffffffUL) {
185		struct cfi_private *cfi;
186		unsigned long offset;
187		int i;
188
189		if (!map) {
190			map = kmalloc(sizeof(*map), GFP_KERNEL);
191		}
192		if (!map) {
193			printk(KERN_ERR MOD_NAME ": kmalloc failed");
194			goto out;
195		}
196		memset(map, 0, sizeof(*map));
197		INIT_LIST_HEAD(&map->list);
198		map->map.name = map->map_name;
199		map->map.phys = map_top;
200		offset = map_top - window->phys;
201		map->map.virt = (void __iomem *)
202			(((unsigned long)(window->virt)) + offset);
203		map->map.size = 0xffffffffUL - map_top + 1UL;
204		/* Set the name of the map to the address I am trying */
205		sprintf(map->map_name, "%s @%08Lx",
206			MOD_NAME, (unsigned long long)map->map.phys);
207
208		/* There is no generic VPP support */
209		for(map->map.bankwidth = 32; map->map.bankwidth;
210			map->map.bankwidth >>= 1)
211		{
212			char **probe_type;
213			/* Skip bankwidths that are not supported */
214			if (!map_bankwidth_supported(map->map.bankwidth))
215				continue;
216
217			/* Setup the map methods */
218			simple_map_init(&map->map);
219
220			/* Try all of the probe methods */
221			probe_type = rom_probe_types;
222			for(; *probe_type; probe_type++) {
223				map->mtd = do_map_probe(*probe_type, &map->map);
224				if (map->mtd)
225					goto found;
226			}
227		}
228		map_top += ROM_PROBE_STEP_SIZE;
229		continue;
230	found:
231		/* Trim the size if we are larger than the map */
232		if (map->mtd->size > map->map.size) {
233			printk(KERN_WARNING MOD_NAME
234				" rom(%u) larger than window(%lu). fixing...\n",
235				map->mtd->size, map->map.size);
236			map->mtd->size = map->map.size;
237		}
238		if (window->rsrc.parent) {
239			/*
240			 * Registering the MTD device in iomem may not be possible
241			 * if there is a BIOS "reserved" and BUSY range.  If this
242			 * fails then continue anyway.
243			 */
244			map->rsrc.name  = map->map_name;
245			map->rsrc.start = map->map.phys;
246			map->rsrc.end   = map->map.phys + map->mtd->size - 1;
247			map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
248			if (request_resource(&window->rsrc, &map->rsrc)) {
249				printk(KERN_ERR MOD_NAME
250					": cannot reserve MTD resource\n");
251				map->rsrc.parent = NULL;
252			}
253		}
254
255		/* Make the whole region visible in the map */
256		map->map.virt = window->virt;
257		map->map.phys = window->phys;
258		cfi = map->map.fldrv_priv;
259		for(i = 0; i < cfi->numchips; i++) {
260			cfi->chips[i].start += offset;
261		}
262
263		/* Now that the mtd devices is complete claim and export it */
264		map->mtd->owner = THIS_MODULE;
265		if (add_mtd_device(map->mtd)) {
266			map_destroy(map->mtd);
267			map->mtd = NULL;
268			goto out;
269		}
270
271
272		/* Calculate the new value of map_top */
273		map_top += map->mtd->size;
274
275		/* File away the map structure */
276		list_add(&map->list, &window->maps);
277		map = NULL;
278	}
279
280 out:
281	/* Free any left over map structures */
282	kfree(map);
283	/* See if I have any map structures */
284	if (list_empty(&window->maps)) {
285		amd76xrom_cleanup(window);
286		return -ENODEV;
287	}
288	return 0;
289}
290
291
292static void __devexit amd76xrom_remove_one (struct pci_dev *pdev)
293{
294	struct amd76xrom_window *window = &amd76xrom_window;
295
296	amd76xrom_cleanup(window);
297}
298
299static struct pci_device_id amd76xrom_pci_tbl[] = {
300	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410,
301		PCI_ANY_ID, PCI_ANY_ID, },
302	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7440,
303		PCI_ANY_ID, PCI_ANY_ID, },
304	{ PCI_VENDOR_ID_AMD, 0x7468 }, /* amd8111 support */
305	{ 0, }
306};
307
308MODULE_DEVICE_TABLE(pci, amd76xrom_pci_tbl);
309
310
311static int __init init_amd76xrom(void)
312{
313	struct pci_dev *pdev;
314	struct pci_device_id *id;
315	pdev = NULL;
316	for(id = amd76xrom_pci_tbl; id->vendor; id++) {
317		pdev = pci_get_device(id->vendor, id->device, NULL);
318		if (pdev) {
319			break;
320		}
321	}
322	if (pdev) {
323		return amd76xrom_init_one(pdev, &amd76xrom_pci_tbl[0]);
324	}
325	return -ENXIO;
326}
327
328static void __exit cleanup_amd76xrom(void)
329{
330	amd76xrom_remove_one(amd76xrom_window.pdev);
331}
332
333module_init(init_amd76xrom);
334module_exit(cleanup_amd76xrom);
335
336MODULE_LICENSE("GPL");
337MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");
338MODULE_DESCRIPTION("MTD map driver for BIOS chips on the AMD76X southbridge");
339