1/* saa711x - Philips SAA711x video decoder register specifications 2 * 3 * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@infradead.org> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#define R_00_CHIP_VERSION 0x00 17/* Video Decoder */ 18 /* Video Decoder - Frontend part */ 19#define R_01_INC_DELAY 0x01 20#define R_02_INPUT_CNTL_1 0x02 21#define R_03_INPUT_CNTL_2 0x03 22#define R_04_INPUT_CNTL_3 0x04 23#define R_05_INPUT_CNTL_4 0x05 24 /* Video Decoder - Decoder part */ 25#define R_06_H_SYNC_START 0x06 26#define R_07_H_SYNC_STOP 0x07 27#define R_08_SYNC_CNTL 0x08 28#define R_09_LUMA_CNTL 0x09 29#define R_0A_LUMA_BRIGHT_CNTL 0x0a 30#define R_0B_LUMA_CONTRAST_CNTL 0x0b 31#define R_0C_CHROMA_SAT_CNTL 0x0c 32#define R_0D_CHROMA_HUE_CNTL 0x0d 33#define R_0E_CHROMA_CNTL_1 0x0e 34#define R_0F_CHROMA_GAIN_CNTL 0x0f 35#define R_10_CHROMA_CNTL_2 0x10 36#define R_11_MODE_DELAY_CNTL 0x11 37#define R_12_RT_SIGNAL_CNTL 0x12 38#define R_13_RT_X_PORT_OUT_CNTL 0x13 39#define R_14_ANAL_ADC_COMPAT_CNTL 0x14 40#define R_15_VGATE_START_FID_CHG 0x15 41#define R_16_VGATE_STOP 0x16 42#define R_17_MISC_VGATE_CONF_AND_MSB 0x17 43#define R_18_RAW_DATA_GAIN_CNTL 0x18 44#define R_19_RAW_DATA_OFF_CNTL 0x19 45#define R_1A_COLOR_KILL_LVL_CNTL 0x1a 46#define R_1B_MISC_TVVCRDET 0x1b 47#define R_1C_ENHAN_COMB_CTRL1 0x1c 48#define R_1D_ENHAN_COMB_CTRL2 0x1d 49#define R_1E_STATUS_BYTE_1_VD_DEC 0x1e 50#define R_1F_STATUS_BYTE_2_VD_DEC 0x1f 51 52/* Component processing and interrupt masking part */ 53#define R_23_INPUT_CNTL_5 0x23 54#define R_24_INPUT_CNTL_6 0x24 55#define R_25_INPUT_CNTL_7 0x25 56#define R_29_COMP_DELAY 0x29 57#define R_2A_COMP_BRIGHT_CNTL 0x2a 58#define R_2B_COMP_CONTRAST_CNTL 0x2b 59#define R_2C_COMP_SAT_CNTL 0x2c 60#define R_2D_INTERRUPT_MASK_1 0x2d 61#define R_2E_INTERRUPT_MASK_2 0x2e 62#define R_2F_INTERRUPT_MASK_3 0x2f 63 64/* Audio clock generator part */ 65#define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30 66#define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34 67#define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38 68#define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39 69#define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a 70 71/* General purpose VBI data slicer part */ 72#define R_40_SLICER_CNTL_1 0x40 73#define R_41_LCR_BASE 0x41 74#define R_58_PROGRAM_FRAMING_CODE 0x58 75#define R_59_H_OFF_FOR_SLICER 0x59 76#define R_5A_V_OFF_FOR_SLICER 0x5a 77#define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b 78#define R_5D_DID 0x5d 79#define R_5E_SDID 0x5e 80#define R_60_SLICER_STATUS_BYTE_0 0x60 81#define R_61_SLICER_STATUS_BYTE_1 0x61 82#define R_62_SLICER_STATUS_BYTE_2 0x62 83 84/* X port, I port and the scaler part */ 85 /* Task independent global settings */ 86#define R_80_GLOBAL_CNTL_1 0x80 87#define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81 88#define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83 89#define R_84_I_PORT_SIGNAL_DEF 0x84 90#define R_85_I_PORT_SIGNAL_POLAR 0x85 91#define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86 92#define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87 93#define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88 94#define R_8F_STATUS_INFO_SCALER 0x8f 95 /* Task A definition */ 96 /* Basic settings and acquisition window definition */ 97#define R_90_A_TASK_HANDLING_CNTL 0x90 98#define R_91_A_X_PORT_FORMATS_AND_CONF 0x91 99#define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92 100#define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93 101#define R_94_A_HORIZ_INPUT_WINDOW_START 0x94 102#define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95 103#define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96 104#define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97 105#define R_98_A_VERT_INPUT_WINDOW_START 0x98 106#define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99 107#define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a 108#define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b 109#define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c 110#define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d 111#define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e 112#define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f 113 /* FIR filtering and prescaling */ 114#define R_A0_A_HORIZ_PRESCALING 0xa0 115#define R_A1_A_ACCUMULATION_LENGTH 0xa1 116#define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2 117#define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4 118#define R_A5_A_LUMA_CONTRAST_CNTL 0xa5 119#define R_A6_A_CHROMA_SATURATION_CNTL 0xa6 120 /* Horizontal phase scaling */ 121#define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8 122#define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9 123#define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa 124#define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac 125#define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad 126#define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae 127#define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf 128 /* Vertical scaling */ 129#define R_B0_A_VERT_LUMA_SCALING_INC 0xb0 130#define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1 131#define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2 132#define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3 133#define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4 134#define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8 135#define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9 136#define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba 137#define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb 138#define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc 139#define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd 140#define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe 141#define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf 142 /* Task B definition */ 143 /* Basic settings and acquisition window definition */ 144#define R_C0_B_TASK_HANDLING_CNTL 0xc0 145#define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1 146#define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2 147#define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3 148#define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4 149#define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5 150#define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6 151#define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7 152#define R_C8_B_VERT_INPUT_WINDOW_START 0xc8 153#define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9 154#define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca 155#define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb 156#define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc 157#define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd 158#define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce 159#define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf 160 /* FIR filtering and prescaling */ 161#define R_D0_B_HORIZ_PRESCALING 0xd0 162#define R_D1_B_ACCUMULATION_LENGTH 0xd1 163#define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2 164#define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4 165#define R_D5_B_LUMA_CONTRAST_CNTL 0xd5 166#define R_D6_B_CHROMA_SATURATION_CNTL 0xd6 167 /* Horizontal phase scaling */ 168#define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8 169#define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9 170#define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda 171#define R_DC_B_HORIZ_CHROMA_SCALING 0xdc 172#define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd 173#define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde 174 /* Vertical scaling */ 175#define R_E0_B_VERT_LUMA_SCALING_INC 0xe0 176#define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1 177#define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2 178#define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3 179#define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4 180#define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8 181#define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9 182#define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea 183#define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb 184#define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec 185#define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed 186#define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee 187#define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef 188 189/* second PLL (PLL2) and Pulsegenerator Programming */ 190#define R_F0_LFCO_PER_LINE 0xf0 191#define R_F1_P_I_PARAM_SELECT 0xf1 192#define R_F2_NOMINAL_PLL2_DTO 0xf2 193#define R_F3_PLL_INCREMENT 0xf3 194#define R_F4_PLL2_STATUS 0xf4 195#define R_F5_PULSGEN_LINE_LENGTH 0xf5 196#define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6 197#define R_F7_PULSE_A_POS_MSB 0xf7 198#define R_F8_PULSE_B_POS 0xf8 199#define R_F9_PULSE_B_POS_MSB 0xf9 200#define R_FA_PULSE_C_POS 0xfa 201#define R_FB_PULSE_C_POS_MSB 0xfb 202#define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff 203