1/* 2 * linux/drivers/ide/pci/trm290.c Version 1.02 Mar. 18, 2000 3 * 4 * Copyright (c) 1997-1998 Mark Lord 5 * May be copied or modified under the terms of the GNU General Public License 6 * 7 * June 22, 2004 - get rid of check_region 8 * - Jesper Juhl 9 * 10 */ 11 12/* 13 * This module provides support for the bus-master IDE DMA function 14 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards, 15 * including a "Precision Instruments" board. The TRM290 pre-dates 16 * the sff-8038 standard (ide-dma.c) by a few months, and differs 17 * significantly enough to warrant separate routines for some functions, 18 * while re-using others from ide-dma.c. 19 * 20 * EXPERIMENTAL! It works for me (a sample of one). 21 * 22 * Works reliably for me in DMA mode (READs only), 23 * DMA WRITEs are disabled by default (see #define below); 24 * 25 * DMA is not enabled automatically for this chipset, 26 * but can be turned on manually (with "hdparm -d1") at run time. 27 * 28 * I need volunteers with "spare" drives for further testing 29 * and development, and maybe to help figure out the peculiarities. 30 * Even knowing the registers (below), some things behave strangely. 31 */ 32 33#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */ 34 35/* 36 * TRM-290 PCI-IDE2 Bus Master Chip 37 * ================================ 38 * The configuration registers are addressed in normal I/O port space 39 * and are used as follows: 40 * 41 * trm290_base depends on jumper settings, and is probed for by ide-dma.c 42 * 43 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only) 44 * bit7 must always be written as "1" 45 * bits6-2 undefined 46 * bit1 1=legacy_compatible_mode, 0=native_pci_mode 47 * bit0 1=test_mode, 0=normal(default) 48 * 49 * trm290_base+2 when READ: status register (byte, read-only) 50 * bits7-2 undefined 51 * bit1 channel0 busmaster interrupt status 0=none, 1=asserted 52 * bit0 channel0 interrupt status 0=none, 1=asserted 53 * 54 * trm290_base+3 Interrupt mask register 55 * bits7-5 undefined 56 * bit4 legacy_header: 1=present, 0=absent 57 * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only) 58 * bit2 channel1 interrupt status 0=none, 1=asserted (read only) 59 * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default) 60 * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default) 61 * 62 * trm290_base+1 "CPR" Config Pointer Register (byte) 63 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR 64 * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state 65 * bit5 0=enabled master burst access (default), 1=disable (write only) 66 * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast 67 * bit3 0=primary IDE channel, 1=secondary IDE channel 68 * bits2-0 register index for accesses through CDR port 69 * 70 * trm290_base+0 "CDR" Config Data Register (word) 71 * two sets of seven config registers, 72 * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6), 73 * each index defined below: 74 * 75 * Index-0 Base address register for command block (word) 76 * defaults: 0x1f0 for primary, 0x170 for secondary 77 * 78 * Index-1 general config register (byte) 79 * bit7 1=DMA enable, 0=DMA disable 80 * bit6 1=activate IDE_RESET, 0=no action (default) 81 * bit5 1=enable IORDY, 0=disable IORDY (default) 82 * bit4 0=16-bit data port(default), 1=8-bit (XT) data port 83 * bit3 interrupt polarity: 1=active_low, 0=active_high(default) 84 * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only) 85 * bit1 bus_master_mode(?): 1=enable, 0=disable(default) 86 * bit0 enable_io_ports: 1=enable(default), 0=disable 87 * 88 * Index-2 read-ahead counter preload bits 0-7 (byte, write only) 89 * bits7-0 bits7-0 of readahead count 90 * 91 * Index-3 read-ahead config register (byte, write only) 92 * bit7 1=enable_readahead, 0=disable_readahead(default) 93 * bit6 1=clear_FIFO, 0=no_action 94 * bit5 undefined 95 * bit4 mode4 timing control: 1=enable, 0=disable(default) 96 * bit3 undefined 97 * bit2 undefined 98 * bits1-0 bits9-8 of read-ahead count 99 * 100 * Index-4 base address register for control block (word) 101 * defaults: 0x3f6 for primary, 0x376 for secondary 102 * 103 * Index-5 data port timings (shared by both drives) (byte) 104 * standard PCI "clk" (clock) counts, default value = 0xf5 105 * 106 * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk 107 * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk, 108 * 011=4clk, 100=5clk, 101=6clk, 109 * 110=8clk, 111=12clk 110 * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk, 111 * 011=5clk, 100=6clk, 101=8clk, 112 * 110=12clk, 111=16clk 113 * 114 * Index-6 command/control port timings (shared by both drives) (byte) 115 * same layout as Index-5, default value = 0xde 116 * 117 * Suggested CDR programming for PIO mode0 (600ns): 118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary 119 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary 120 * 121 * Suggested CDR programming for PIO mode3 (180ns): 122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary 123 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary 124 * 125 * Suggested CDR programming for PIO mode4 (120ns): 126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary 127 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary 128 * 129 */ 130 131#include <linux/types.h> 132#include <linux/module.h> 133#include <linux/kernel.h> 134#include <linux/mm.h> 135#include <linux/ioport.h> 136#include <linux/interrupt.h> 137#include <linux/blkdev.h> 138#include <linux/init.h> 139#include <linux/hdreg.h> 140#include <linux/pci.h> 141#include <linux/delay.h> 142#include <linux/ide.h> 143 144#include <asm/io.h> 145 146static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma) 147{ 148 ide_hwif_t *hwif = HWIF(drive); 149 u16 reg = 0; 150 unsigned long flags; 151 152 /* select PIO or DMA */ 153 reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82); 154 155 local_irq_save(flags); 156 157 if (reg != hwif->select_data) { 158 hwif->select_data = reg; 159 /* set PIO/DMA */ 160 outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); 161 outw(reg & 0xff, hwif->config_data); 162 } 163 164 /* enable IRQ if not probing */ 165 if (drive->present) { 166 reg = inw(hwif->config_data + 3); 167 reg &= 0x13; 168 reg &= ~(1 << hwif->channel); 169 outw(reg, hwif->config_data + 3); 170 } 171 172 local_irq_restore(flags); 173} 174 175static void trm290_selectproc (ide_drive_t *drive) 176{ 177 trm290_prepare_drive(drive, drive->using_dma); 178} 179 180static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) 181{ 182 BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */ 183 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL); 184 /* issue cmd to drive */ 185 outb(command, IDE_COMMAND_REG); 186} 187 188static int trm290_ide_dma_setup(ide_drive_t *drive) 189{ 190 ide_hwif_t *hwif = drive->hwif; 191 struct request *rq = hwif->hwgroup->rq; 192 unsigned int count, rw; 193 194 if (rq_data_dir(rq)) { 195#ifdef TRM290_NO_DMA_WRITES 196 /* always use PIO for writes */ 197 trm290_prepare_drive(drive, 0); /* select PIO xfer */ 198 return 1; 199#endif 200 rw = 1; 201 } else 202 rw = 2; 203 204 if (!(count = ide_build_dmatable(drive, rq))) { 205 /* try PIO instead of DMA */ 206 trm290_prepare_drive(drive, 0); /* select PIO xfer */ 207 return 1; 208 } 209 /* select DMA xfer */ 210 trm290_prepare_drive(drive, 1); 211 outl(hwif->dmatable_dma | rw, hwif->dma_command); 212 drive->waiting_for_dma = 1; 213 /* start DMA */ 214 outw((count * 2) - 1, hwif->dma_status); 215 return 0; 216} 217 218static void trm290_ide_dma_start(ide_drive_t *drive) 219{ 220} 221 222static int trm290_ide_dma_end (ide_drive_t *drive) 223{ 224 ide_hwif_t *hwif = HWIF(drive); 225 u16 status = 0; 226 227 drive->waiting_for_dma = 0; 228 /* purge DMA mappings */ 229 ide_destroy_dmatable(drive); 230 status = inw(hwif->dma_status); 231 return (status != 0x00ff); 232} 233 234static int trm290_ide_dma_test_irq (ide_drive_t *drive) 235{ 236 ide_hwif_t *hwif = HWIF(drive); 237 u16 status = 0; 238 239 status = inw(hwif->dma_status); 240 return (status == 0x00ff); 241} 242 243/* 244 * Invoked from ide-dma.c at boot time. 245 */ 246static void __devinit init_hwif_trm290(ide_hwif_t *hwif) 247{ 248 unsigned int cfgbase = 0; 249 unsigned long flags; 250 u8 reg = 0; 251 struct pci_dev *dev = hwif->pci_dev; 252 253 hwif->no_lba48 = 1; 254 hwif->chipset = ide_trm290; 255 cfgbase = pci_resource_start(dev, 4); 256 if ((dev->class & 5) && cfgbase) { 257 hwif->config_data = cfgbase; 258 printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n", 259 hwif->config_data); 260 } else { 261 hwif->config_data = 0x3df0; 262 printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n", 263 hwif->config_data); 264 } 265 266 local_irq_save(flags); 267 /* put config reg into first byte of hwif->select_data */ 268 outb(0x51 | (hwif->channel << 3), hwif->config_data + 1); 269 /* select PIO as default */ 270 hwif->select_data = 0x21; 271 outb(hwif->select_data, hwif->config_data); 272 /* get IRQ info */ 273 reg = inb(hwif->config_data + 3); 274 /* mask IRQs for both ports */ 275 reg = (reg & 0x10) | 0x03; 276 outb(reg, hwif->config_data + 3); 277 local_irq_restore(flags); 278 279 if ((reg & 0x10)) 280 /* legacy mode */ 281 hwif->irq = hwif->channel ? 15 : 14; 282 else if (!hwif->irq && hwif->mate && hwif->mate->irq) 283 /* sharing IRQ with mate */ 284 hwif->irq = hwif->mate->irq; 285 286 ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3); 287 288 hwif->dma_setup = &trm290_ide_dma_setup; 289 hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd; 290 hwif->dma_start = &trm290_ide_dma_start; 291 hwif->ide_dma_end = &trm290_ide_dma_end; 292 hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq; 293 294 hwif->selectproc = &trm290_selectproc; 295 hwif->autodma = 0; /* play it safe for now */ 296 hwif->drives[0].autodma = hwif->autodma; 297 hwif->drives[1].autodma = hwif->autodma; 298 { 299 /* 300 * My trm290-based card doesn't seem to work with all possible values 301 * for the control basereg, so this kludge ensures that we use only 302 * values that are known to work. Ugh. -ml 303 */ 304 u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4; 305 static u16 next_offset = 0; 306 u8 old_mask; 307 308 outb(0x54 | (hwif->channel << 3), hwif->config_data + 1); 309 old = inw(hwif->config_data); 310 old &= ~1; 311 old_mask = inb(old + 2); 312 if (old != compat && old_mask == 0xff) { 313 /* leave lower 10 bits untouched */ 314 compat += (next_offset += 0x400); 315 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2; 316 outw(compat | 1, hwif->config_data); 317 new = inw(hwif->config_data); 318 printk(KERN_INFO "%s: control basereg workaround: " 319 "old=0x%04x, new=0x%04x\n", 320 hwif->name, old, new & ~1); 321 } 322 } 323} 324 325static ide_pci_device_t trm290_chipset __devinitdata = { 326 .name = "TRM290", 327 .init_hwif = init_hwif_trm290, 328 .channels = 2, 329 .autodma = NOAUTODMA, 330 .bootable = ON_BOARD, 331}; 332 333static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id) 334{ 335 return ide_setup_pci_device(dev, &trm290_chipset); 336} 337 338static struct pci_device_id trm290_pci_tbl[] = { 339 { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 340 { 0, }, 341}; 342MODULE_DEVICE_TABLE(pci, trm290_pci_tbl); 343 344static struct pci_driver driver = { 345 .name = "TRM290_IDE", 346 .id_table = trm290_pci_tbl, 347 .probe = trm290_init_one, 348}; 349 350static int __init trm290_ide_init(void) 351{ 352 return ide_pci_register_driver(&driver); 353} 354 355module_init(trm290_ide_init); 356 357MODULE_AUTHOR("Mark Lord"); 358MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE"); 359MODULE_LICENSE("GPL"); 360