1/* 2 * RocketPort device driver for Linux 3 * 4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000. 5 * 6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of the 11 * License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23/* 24 * Kernel Synchronization: 25 * 26 * This driver has 2 kernel control paths - exception handlers (calls into the driver 27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts 28 * are not used. 29 * 30 * Critical data: 31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of 32 * serial port state information and the xmit_buf circular buffer. Protected by 33 * a per port spinlock. 34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there 35 * is data to be transmitted. Protected by atomic bit operations. 36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations. 37 * 38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against 39 * simultaneous access to the same port by more than one process. 40 */ 41 42/****** Defines ******/ 43#ifdef PCI_NUM_RESOURCES 44#define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start) 45#else 46#define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r]) 47#endif 48 49#define ROCKET_PARANOIA_CHECK 50#define ROCKET_DISABLE_SIMUSAGE 51 52#undef ROCKET_SOFT_FLOW 53#undef ROCKET_DEBUG_OPEN 54#undef ROCKET_DEBUG_INTR 55#undef ROCKET_DEBUG_WRITE 56#undef ROCKET_DEBUG_FLOW 57#undef ROCKET_DEBUG_THROTTLE 58#undef ROCKET_DEBUG_WAIT_UNTIL_SENT 59#undef ROCKET_DEBUG_RECEIVE 60#undef ROCKET_DEBUG_HANGUP 61#undef REV_PCI_ORDER 62#undef ROCKET_DEBUG_IO 63 64#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */ 65 66/****** Kernel includes ******/ 67 68#include <linux/module.h> 69#include <linux/errno.h> 70#include <linux/major.h> 71#include <linux/kernel.h> 72#include <linux/signal.h> 73#include <linux/slab.h> 74#include <linux/mm.h> 75#include <linux/sched.h> 76#include <linux/timer.h> 77#include <linux/interrupt.h> 78#include <linux/tty.h> 79#include <linux/tty_driver.h> 80#include <linux/tty_flip.h> 81#include <linux/string.h> 82#include <linux/fcntl.h> 83#include <linux/ptrace.h> 84#include <linux/mutex.h> 85#include <linux/ioport.h> 86#include <linux/delay.h> 87#include <linux/wait.h> 88#include <linux/pci.h> 89#include <asm/uaccess.h> 90#include <asm/atomic.h> 91#include <linux/bitops.h> 92#include <linux/spinlock.h> 93#include <linux/init.h> 94 95/****** RocketPort includes ******/ 96 97#include "rocket_int.h" 98#include "rocket.h" 99 100#define ROCKET_VERSION "2.09" 101#define ROCKET_DATE "12-June-2003" 102 103/****** RocketPort Local Variables ******/ 104 105static void rp_do_poll(unsigned long dummy); 106 107static struct tty_driver *rocket_driver; 108 109static struct rocket_version driver_version = { 110 ROCKET_VERSION, ROCKET_DATE 111}; 112 113static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */ 114static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */ 115 /* eg. Bit 0 indicates port 0 has xmit data, ... */ 116static atomic_t rp_num_ports_open; /* Number of serial ports open */ 117static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0); 118 119static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */ 120static unsigned long board2; 121static unsigned long board3; 122static unsigned long board4; 123static unsigned long controller; 124static int support_low_speed; 125static unsigned long modem1; 126static unsigned long modem2; 127static unsigned long modem3; 128static unsigned long modem4; 129static unsigned long pc104_1[8]; 130static unsigned long pc104_2[8]; 131static unsigned long pc104_3[8]; 132static unsigned long pc104_4[8]; 133static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 }; 134 135static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */ 136static unsigned long rcktpt_io_addr[NUM_BOARDS]; 137static int rcktpt_type[NUM_BOARDS]; 138static int is_PCI[NUM_BOARDS]; 139static rocketModel_t rocketModel[NUM_BOARDS]; 140static int max_board; 141 142/* 143 * The following arrays define the interrupt bits corresponding to each AIOP. 144 * These bits are different between the ISA and regular PCI boards and the 145 * Universal PCI boards. 146 */ 147 148static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = { 149 AIOP_INTR_BIT_0, 150 AIOP_INTR_BIT_1, 151 AIOP_INTR_BIT_2, 152 AIOP_INTR_BIT_3 153}; 154 155static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = { 156 UPCI_AIOP_INTR_BIT_0, 157 UPCI_AIOP_INTR_BIT_1, 158 UPCI_AIOP_INTR_BIT_2, 159 UPCI_AIOP_INTR_BIT_3 160}; 161 162static Byte_t RData[RDATASIZE] = { 163 0x00, 0x09, 0xf6, 0x82, 164 0x02, 0x09, 0x86, 0xfb, 165 0x04, 0x09, 0x00, 0x0a, 166 0x06, 0x09, 0x01, 0x0a, 167 0x08, 0x09, 0x8a, 0x13, 168 0x0a, 0x09, 0xc5, 0x11, 169 0x0c, 0x09, 0x86, 0x85, 170 0x0e, 0x09, 0x20, 0x0a, 171 0x10, 0x09, 0x21, 0x0a, 172 0x12, 0x09, 0x41, 0xff, 173 0x14, 0x09, 0x82, 0x00, 174 0x16, 0x09, 0x82, 0x7b, 175 0x18, 0x09, 0x8a, 0x7d, 176 0x1a, 0x09, 0x88, 0x81, 177 0x1c, 0x09, 0x86, 0x7a, 178 0x1e, 0x09, 0x84, 0x81, 179 0x20, 0x09, 0x82, 0x7c, 180 0x22, 0x09, 0x0a, 0x0a 181}; 182 183static Byte_t RRegData[RREGDATASIZE] = { 184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */ 185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */ 186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */ 187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */ 188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */ 189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */ 190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */ 191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */ 192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */ 193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */ 194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */ 195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */ 196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */ 197}; 198 199static CONTROLLER_T sController[CTL_SIZE] = { 200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, 201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}, 202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, 203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}, 204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, 205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}, 206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, 207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}} 208}; 209 210static Byte_t sBitMapClrTbl[8] = { 211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f 212}; 213 214static Byte_t sBitMapSetTbl[8] = { 215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 216}; 217 218static int sClockPrescale = 0x14; 219 220/* 221 * Line number is the ttySIx number (x), the Minor number. We 222 * assign them sequentially, starting at zero. The following 223 * array keeps track of the line number assigned to a given board/aiop/channel. 224 */ 225static unsigned char lineNumbers[MAX_RP_PORTS]; 226static unsigned long nextLineNumber; 227 228/***** RocketPort Static Prototypes *********/ 229static int __init init_ISA(int i); 230static void rp_wait_until_sent(struct tty_struct *tty, int timeout); 231static void rp_flush_buffer(struct tty_struct *tty); 232static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model); 233static unsigned char GetLineNumber(int ctrl, int aiop, int ch); 234static unsigned char SetLineNumber(int ctrl, int aiop, int ch); 235static void rp_start(struct tty_struct *tty); 236static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, 237 int ChanNum); 238static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode); 239static void sFlushRxFIFO(CHANNEL_T * ChP); 240static void sFlushTxFIFO(CHANNEL_T * ChP); 241static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags); 242static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags); 243static void sModemReset(CONTROLLER_T * CtlP, int chan, int on); 244static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on); 245static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data); 246static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum, 247 ByteIO_t * AiopIOList, int AiopIOListSize, 248 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency, 249 int PeriodicOnly, int altChanRingIndicator, 250 int UPCIRingInd); 251static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO, 252 ByteIO_t * AiopIOList, int AiopIOListSize, 253 int IRQNum, Byte_t Frequency, int PeriodicOnly); 254static int sReadAiopID(ByteIO_t io); 255static int sReadAiopNumChan(WordIO_t io); 256 257MODULE_AUTHOR("Theodore Ts'o"); 258MODULE_DESCRIPTION("Comtrol RocketPort driver"); 259module_param(board1, ulong, 0); 260MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1"); 261module_param(board2, ulong, 0); 262MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2"); 263module_param(board3, ulong, 0); 264MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3"); 265module_param(board4, ulong, 0); 266MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4"); 267module_param(controller, ulong, 0); 268MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller"); 269module_param(support_low_speed, bool, 0); 270MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud"); 271module_param(modem1, ulong, 0); 272MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem"); 273module_param(modem2, ulong, 0); 274MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem"); 275module_param(modem3, ulong, 0); 276MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem"); 277module_param(modem4, ulong, 0); 278MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem"); 279module_param_array(pc104_1, ulong, NULL, 0); 280MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,..."); 281module_param_array(pc104_2, ulong, NULL, 0); 282MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,..."); 283module_param_array(pc104_3, ulong, NULL, 0); 284MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,..."); 285module_param_array(pc104_4, ulong, NULL, 0); 286MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,..."); 287 288static int rp_init(void); 289static void rp_cleanup_module(void); 290 291module_init(rp_init); 292module_exit(rp_cleanup_module); 293 294 295MODULE_LICENSE("Dual BSD/GPL"); 296 297/*************************************************************************/ 298/* Module code starts here */ 299 300static inline int rocket_paranoia_check(struct r_port *info, 301 const char *routine) 302{ 303#ifdef ROCKET_PARANOIA_CHECK 304 if (!info) 305 return 1; 306 if (info->magic != RPORT_MAGIC) { 307 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n", 308 routine); 309 return 1; 310 } 311#endif 312 return 0; 313} 314 315 316/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals 317 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the 318 * tty layer. 319 */ 320static void rp_do_receive(struct r_port *info, 321 struct tty_struct *tty, 322 CHANNEL_t * cp, unsigned int ChanStatus) 323{ 324 unsigned int CharNStat; 325 int ToRecv, wRecv, space; 326 unsigned char *cbuf; 327 328 ToRecv = sGetRxCnt(cp); 329#ifdef ROCKET_DEBUG_INTR 330 printk(KERN_INFO "rp_do_receive(%d)...", ToRecv); 331#endif 332 if (ToRecv == 0) 333 return; 334 335 /* 336 * if status indicates there are errored characters in the 337 * FIFO, then enter status mode (a word in FIFO holds 338 * character and status). 339 */ 340 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) { 341 if (!(ChanStatus & STATMODE)) { 342#ifdef ROCKET_DEBUG_RECEIVE 343 printk(KERN_INFO "Entering STATMODE..."); 344#endif 345 ChanStatus |= STATMODE; 346 sEnRxStatusMode(cp); 347 } 348 } 349 350 /* 351 * if we previously entered status mode, then read down the 352 * FIFO one word at a time, pulling apart the character and 353 * the status. Update error counters depending on status 354 */ 355 if (ChanStatus & STATMODE) { 356#ifdef ROCKET_DEBUG_RECEIVE 357 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask, 358 info->read_status_mask); 359#endif 360 while (ToRecv) { 361 char flag; 362 363 CharNStat = sInW(sGetTxRxDataIO(cp)); 364#ifdef ROCKET_DEBUG_RECEIVE 365 printk(KERN_INFO "%x...", CharNStat); 366#endif 367 if (CharNStat & STMBREAKH) 368 CharNStat &= ~(STMFRAMEH | STMPARITYH); 369 if (CharNStat & info->ignore_status_mask) { 370 ToRecv--; 371 continue; 372 } 373 CharNStat &= info->read_status_mask; 374 if (CharNStat & STMBREAKH) 375 flag = TTY_BREAK; 376 else if (CharNStat & STMPARITYH) 377 flag = TTY_PARITY; 378 else if (CharNStat & STMFRAMEH) 379 flag = TTY_FRAME; 380 else if (CharNStat & STMRCVROVRH) 381 flag = TTY_OVERRUN; 382 else 383 flag = TTY_NORMAL; 384 tty_insert_flip_char(tty, CharNStat & 0xff, flag); 385 ToRecv--; 386 } 387 388 /* 389 * after we've emptied the FIFO in status mode, turn 390 * status mode back off 391 */ 392 if (sGetRxCnt(cp) == 0) { 393#ifdef ROCKET_DEBUG_RECEIVE 394 printk(KERN_INFO "Status mode off.\n"); 395#endif 396 sDisRxStatusMode(cp); 397 } 398 } else { 399 /* 400 * we aren't in status mode, so read down the FIFO two 401 * characters at time by doing repeated word IO 402 * transfer. 403 */ 404 space = tty_prepare_flip_string(tty, &cbuf, ToRecv); 405 if (space < ToRecv) { 406#ifdef ROCKET_DEBUG_RECEIVE 407 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space); 408#endif 409 if (space <= 0) 410 return; 411 ToRecv = space; 412 } 413 wRecv = ToRecv >> 1; 414 if (wRecv) 415 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv); 416 if (ToRecv & 1) 417 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp)); 418 } 419 /* Push the data up to the tty layer */ 420 tty_flip_buffer_push(tty); 421} 422 423/* 424 * Serial port transmit data function. Called from the timer polling loop as a 425 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready 426 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is 427 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks. 428 */ 429static void rp_do_transmit(struct r_port *info) 430{ 431 int c; 432 CHANNEL_t *cp = &info->channel; 433 struct tty_struct *tty; 434 unsigned long flags; 435 436#ifdef ROCKET_DEBUG_INTR 437 printk(KERN_INFO "rp_do_transmit "); 438#endif 439 if (!info) 440 return; 441 if (!info->tty) { 442 printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n"); 443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 444 return; 445 } 446 447 spin_lock_irqsave(&info->slock, flags); 448 tty = info->tty; 449 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp); 450 451 /* Loop sending data to FIFO until done or FIFO full */ 452 while (1) { 453 if (tty->stopped || tty->hw_stopped) 454 break; 455 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail)); 456 if (c <= 0 || info->xmit_fifo_room <= 0) 457 break; 458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2); 459 if (c & 1) 460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]); 461 info->xmit_tail += c; 462 info->xmit_tail &= XMIT_BUF_SIZE - 1; 463 info->xmit_cnt -= c; 464 info->xmit_fifo_room -= c; 465#ifdef ROCKET_DEBUG_INTR 466 printk(KERN_INFO "tx %d chars...", c); 467#endif 468 } 469 470 if (info->xmit_cnt == 0) 471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 472 473 if (info->xmit_cnt < WAKEUP_CHARS) { 474 tty_wakeup(tty); 475#ifdef ROCKETPORT_HAVE_POLL_WAIT 476 wake_up_interruptible(&tty->poll_wait); 477#endif 478 } 479 480 spin_unlock_irqrestore(&info->slock, flags); 481 482#ifdef ROCKET_DEBUG_INTR 483 printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head, 484 info->xmit_tail, info->xmit_fifo_room); 485#endif 486} 487 488/* 489 * Called when a serial port signals it has read data in it's RX FIFO. 490 * It checks what interrupts are pending and services them, including 491 * receiving serial data. 492 */ 493static void rp_handle_port(struct r_port *info) 494{ 495 CHANNEL_t *cp; 496 struct tty_struct *tty; 497 unsigned int IntMask, ChanStatus; 498 499 if (!info) 500 return; 501 502 if ((info->flags & ROCKET_INITIALIZED) == 0) { 503 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n"); 504 return; 505 } 506 if (!info->tty) { 507 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n"); 508 return; 509 } 510 cp = &info->channel; 511 tty = info->tty; 512 513 IntMask = sGetChanIntID(cp) & info->intmask; 514#ifdef ROCKET_DEBUG_INTR 515 printk(KERN_INFO "rp_interrupt %02x...", IntMask); 516#endif 517 ChanStatus = sGetChanStatus(cp); 518 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */ 519 rp_do_receive(info, tty, cp, ChanStatus); 520 } 521 if (IntMask & DELTA_CD) { /* CD change */ 522#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || \ 523 defined(ROCKET_DEBUG_HANGUP)) 524 printk(KERN_INFO "ttyR%d CD now %s...", info->line, 525 (ChanStatus & CD_ACT) ? "on" : "off"); 526#endif 527 if (!(ChanStatus & CD_ACT) && info->cd_status) { 528#ifdef ROCKET_DEBUG_HANGUP 529 printk(KERN_INFO "CD drop, calling hangup.\n"); 530#endif 531 tty_hangup(tty); 532 } 533 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0; 534 wake_up_interruptible(&info->open_wait); 535 } 536#ifdef ROCKET_DEBUG_INTR 537 if (IntMask & DELTA_CTS) { /* CTS change */ 538 printk(KERN_INFO "CTS change...\n"); 539 } 540 if (IntMask & DELTA_DSR) { /* DSR change */ 541 printk(KERN_INFO "DSR change...\n"); 542 } 543#endif 544} 545 546/* 547 * The top level polling routine. Repeats every 1/100 HZ (10ms). 548 */ 549static void rp_do_poll(unsigned long dummy) 550{ 551 CONTROLLER_t *ctlp; 552 int ctrl, aiop, ch, line, i; 553 unsigned int xmitmask; 554 unsigned int CtlMask; 555 unsigned char AiopMask; 556 Word_t bit; 557 558 /* Walk through all the boards (ctrl's) */ 559 for (ctrl = 0; ctrl < max_board; ctrl++) { 560 if (rcktpt_io_addr[ctrl] <= 0) 561 continue; 562 563 /* Get a ptr to the board's control struct */ 564 ctlp = sCtlNumToCtlPtr(ctrl); 565 566 /* Get the interupt status from the board */ 567#ifdef CONFIG_PCI 568 if (ctlp->BusType == isPCI) 569 CtlMask = sPCIGetControllerIntStatus(ctlp); 570 else 571#endif 572 CtlMask = sGetControllerIntStatus(ctlp); 573 574 /* Check if any AIOP read bits are set */ 575 for (aiop = 0; CtlMask; aiop++) { 576 bit = ctlp->AiopIntrBits[aiop]; 577 if (CtlMask & bit) { 578 CtlMask &= ~bit; 579 AiopMask = sGetAiopIntStatus(ctlp, aiop); 580 581 /* Check if any port read bits are set */ 582 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) { 583 if (AiopMask & 1) { 584 585 /* Get the line number (/dev/ttyRx number). */ 586 /* Read the data from the port. */ 587 line = GetLineNumber(ctrl, aiop, ch); 588 rp_handle_port(rp_table[line]); 589 } 590 } 591 } 592 } 593 594 xmitmask = xmit_flags[ctrl]; 595 596 /* 597 * xmit_flags contains bit-significant flags, indicating there is data 598 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port 599 * 1, ... (32 total possible). The variable i has the aiop and ch 600 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc). 601 */ 602 if (xmitmask) { 603 for (i = 0; i < rocketModel[ctrl].numPorts; i++) { 604 if (xmitmask & (1 << i)) { 605 aiop = (i & 0x18) >> 3; 606 ch = i & 0x07; 607 line = GetLineNumber(ctrl, aiop, ch); 608 rp_do_transmit(rp_table[line]); 609 } 610 } 611 } 612 } 613 614 /* 615 * Reset the timer so we get called at the next clock tick (10ms). 616 */ 617 if (atomic_read(&rp_num_ports_open)) 618 mod_timer(&rocket_timer, jiffies + POLL_PERIOD); 619} 620 621/* 622 * Initializes the r_port structure for a port, as well as enabling the port on 623 * the board. 624 * Inputs: board, aiop, chan numbers 625 */ 626static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev) 627{ 628 unsigned rocketMode; 629 struct r_port *info; 630 int line; 631 CONTROLLER_T *ctlp; 632 633 /* Get the next available line number */ 634 line = SetLineNumber(board, aiop, chan); 635 636 ctlp = sCtlNumToCtlPtr(board); 637 638 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */ 639 info = kmalloc(sizeof (struct r_port), GFP_KERNEL); 640 if (!info) { 641 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line); 642 return; 643 } 644 memset(info, 0, sizeof (struct r_port)); 645 646 info->magic = RPORT_MAGIC; 647 info->line = line; 648 info->ctlp = ctlp; 649 info->board = board; 650 info->aiop = aiop; 651 info->chan = chan; 652 info->closing_wait = 3000; 653 info->close_delay = 50; 654 init_waitqueue_head(&info->open_wait); 655 init_waitqueue_head(&info->close_wait); 656 info->flags &= ~ROCKET_MODE_MASK; 657 switch (pc104[board][line]) { 658 case 422: 659 info->flags |= ROCKET_MODE_RS422; 660 break; 661 case 485: 662 info->flags |= ROCKET_MODE_RS485; 663 break; 664 case 232: 665 default: 666 info->flags |= ROCKET_MODE_RS232; 667 break; 668 } 669 670 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR; 671 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) { 672 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan); 673 kfree(info); 674 return; 675 } 676 677 rocketMode = info->flags & ROCKET_MODE_MASK; 678 679 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485)) 680 sEnRTSToggle(&info->channel); 681 else 682 sDisRTSToggle(&info->channel); 683 684 if (ctlp->boardType == ROCKET_TYPE_PC104) { 685 switch (rocketMode) { 686 case ROCKET_MODE_RS485: 687 sSetInterfaceMode(&info->channel, InterfaceModeRS485); 688 break; 689 case ROCKET_MODE_RS422: 690 sSetInterfaceMode(&info->channel, InterfaceModeRS422); 691 break; 692 case ROCKET_MODE_RS232: 693 default: 694 if (info->flags & ROCKET_RTS_TOGGLE) 695 sSetInterfaceMode(&info->channel, InterfaceModeRS232T); 696 else 697 sSetInterfaceMode(&info->channel, InterfaceModeRS232); 698 break; 699 } 700 } 701 spin_lock_init(&info->slock); 702 mutex_init(&info->write_mtx); 703 rp_table[line] = info; 704 if (pci_dev) 705 tty_register_device(rocket_driver, line, &pci_dev->dev); 706} 707 708/* 709 * Configures a rocketport port according to its termio settings. Called from 710 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected. 711 */ 712static void configure_r_port(struct r_port *info, 713 struct ktermios *old_termios) 714{ 715 unsigned cflag; 716 unsigned long flags; 717 unsigned rocketMode; 718 int bits, baud, divisor; 719 CHANNEL_t *cp; 720 721 if (!info->tty || !info->tty->termios) 722 return; 723 cp = &info->channel; 724 cflag = info->tty->termios->c_cflag; 725 726 /* Byte size and parity */ 727 if ((cflag & CSIZE) == CS8) { 728 sSetData8(cp); 729 bits = 10; 730 } else { 731 sSetData7(cp); 732 bits = 9; 733 } 734 if (cflag & CSTOPB) { 735 sSetStop2(cp); 736 bits++; 737 } else { 738 sSetStop1(cp); 739 } 740 741 if (cflag & PARENB) { 742 sEnParity(cp); 743 bits++; 744 if (cflag & PARODD) { 745 sSetOddParity(cp); 746 } else { 747 sSetEvenParity(cp); 748 } 749 } else { 750 sDisParity(cp); 751 } 752 753 /* baud rate */ 754 baud = tty_get_baud_rate(info->tty); 755 if (!baud) 756 baud = 9600; 757 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1; 758 if ((divisor >= 8192 || divisor < 0) && old_termios) { 759 info->tty->termios->c_cflag &= ~CBAUD; 760 info->tty->termios->c_cflag |= 761 (old_termios->c_cflag & CBAUD); 762 baud = tty_get_baud_rate(info->tty); 763 if (!baud) 764 baud = 9600; 765 divisor = (rp_baud_base[info->board] / baud) - 1; 766 } 767 if (divisor >= 8192 || divisor < 0) { 768 baud = 9600; 769 divisor = (rp_baud_base[info->board] / baud) - 1; 770 } 771 info->cps = baud / bits; 772 sSetBaud(cp, divisor); 773 774 if (cflag & CRTSCTS) { 775 info->intmask |= DELTA_CTS; 776 sEnCTSFlowCtl(cp); 777 } else { 778 info->intmask &= ~DELTA_CTS; 779 sDisCTSFlowCtl(cp); 780 } 781 if (cflag & CLOCAL) { 782 info->intmask &= ~DELTA_CD; 783 } else { 784 spin_lock_irqsave(&info->slock, flags); 785 if (sGetChanStatus(cp) & CD_ACT) 786 info->cd_status = 1; 787 else 788 info->cd_status = 0; 789 info->intmask |= DELTA_CD; 790 spin_unlock_irqrestore(&info->slock, flags); 791 } 792 793 /* 794 * Handle software flow control in the board 795 */ 796#ifdef ROCKET_SOFT_FLOW 797 if (I_IXON(info->tty)) { 798 sEnTxSoftFlowCtl(cp); 799 if (I_IXANY(info->tty)) { 800 sEnIXANY(cp); 801 } else { 802 sDisIXANY(cp); 803 } 804 sSetTxXONChar(cp, START_CHAR(info->tty)); 805 sSetTxXOFFChar(cp, STOP_CHAR(info->tty)); 806 } else { 807 sDisTxSoftFlowCtl(cp); 808 sDisIXANY(cp); 809 sClrTxXOFF(cp); 810 } 811#endif 812 813 /* 814 * Set up ignore/read mask words 815 */ 816 info->read_status_mask = STMRCVROVRH | 0xFF; 817 if (I_INPCK(info->tty)) 818 info->read_status_mask |= STMFRAMEH | STMPARITYH; 819 if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) 820 info->read_status_mask |= STMBREAKH; 821 822 /* 823 * Characters to ignore 824 */ 825 info->ignore_status_mask = 0; 826 if (I_IGNPAR(info->tty)) 827 info->ignore_status_mask |= STMFRAMEH | STMPARITYH; 828 if (I_IGNBRK(info->tty)) { 829 info->ignore_status_mask |= STMBREAKH; 830 /* 831 * If we're ignoring parity and break indicators, 832 * ignore overruns too. (For real raw support). 833 */ 834 if (I_IGNPAR(info->tty)) 835 info->ignore_status_mask |= STMRCVROVRH; 836 } 837 838 rocketMode = info->flags & ROCKET_MODE_MASK; 839 840 if ((info->flags & ROCKET_RTS_TOGGLE) 841 || (rocketMode == ROCKET_MODE_RS485)) 842 sEnRTSToggle(cp); 843 else 844 sDisRTSToggle(cp); 845 846 sSetRTS(&info->channel); 847 848 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) { 849 switch (rocketMode) { 850 case ROCKET_MODE_RS485: 851 sSetInterfaceMode(cp, InterfaceModeRS485); 852 break; 853 case ROCKET_MODE_RS422: 854 sSetInterfaceMode(cp, InterfaceModeRS422); 855 break; 856 case ROCKET_MODE_RS232: 857 default: 858 if (info->flags & ROCKET_RTS_TOGGLE) 859 sSetInterfaceMode(cp, InterfaceModeRS232T); 860 else 861 sSetInterfaceMode(cp, InterfaceModeRS232); 862 break; 863 } 864 } 865} 866 867/* info->count is considered critical, protected by spinlocks. */ 868static int block_til_ready(struct tty_struct *tty, struct file *filp, 869 struct r_port *info) 870{ 871 DECLARE_WAITQUEUE(wait, current); 872 int retval; 873 int do_clocal = 0, extra_count = 0; 874 unsigned long flags; 875 876 /* 877 * If the device is in the middle of being closed, then block 878 * until it's done, and then try again. 879 */ 880 if (tty_hung_up_p(filp)) 881 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); 882 if (info->flags & ROCKET_CLOSING) { 883 interruptible_sleep_on(&info->close_wait); 884 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); 885 } 886 887 /* 888 * If non-blocking mode is set, or the port is not enabled, 889 * then make the check up front and then exit. 890 */ 891 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) { 892 info->flags |= ROCKET_NORMAL_ACTIVE; 893 return 0; 894 } 895 if (tty->termios->c_cflag & CLOCAL) 896 do_clocal = 1; 897 898 /* 899 * Block waiting for the carrier detect and the line to become free. While we are in 900 * this loop, info->count is dropped by one, so that rp_close() knows when to free things. 901 * We restore it upon exit, either normal or abnormal. 902 */ 903 retval = 0; 904 add_wait_queue(&info->open_wait, &wait); 905#ifdef ROCKET_DEBUG_OPEN 906 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count); 907#endif 908 spin_lock_irqsave(&info->slock, flags); 909 910#ifdef ROCKET_DISABLE_SIMUSAGE 911 info->flags |= ROCKET_NORMAL_ACTIVE; 912#else 913 if (!tty_hung_up_p(filp)) { 914 extra_count = 1; 915 info->count--; 916 } 917#endif 918 info->blocked_open++; 919 920 spin_unlock_irqrestore(&info->slock, flags); 921 922 while (1) { 923 if (tty->termios->c_cflag & CBAUD) { 924 sSetDTR(&info->channel); 925 sSetRTS(&info->channel); 926 } 927 set_current_state(TASK_INTERRUPTIBLE); 928 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) { 929 if (info->flags & ROCKET_HUP_NOTIFY) 930 retval = -EAGAIN; 931 else 932 retval = -ERESTARTSYS; 933 break; 934 } 935 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT))) 936 break; 937 if (signal_pending(current)) { 938 retval = -ERESTARTSYS; 939 break; 940 } 941#ifdef ROCKET_DEBUG_OPEN 942 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n", 943 info->line, info->count, info->flags); 944#endif 945 schedule(); /* Don't hold spinlock here, will hang PC */ 946 } 947 __set_current_state(TASK_RUNNING); 948 remove_wait_queue(&info->open_wait, &wait); 949 950 spin_lock_irqsave(&info->slock, flags); 951 952 if (extra_count) 953 info->count++; 954 info->blocked_open--; 955 956 spin_unlock_irqrestore(&info->slock, flags); 957 958#ifdef ROCKET_DEBUG_OPEN 959 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n", 960 info->line, info->count); 961#endif 962 if (retval) 963 return retval; 964 info->flags |= ROCKET_NORMAL_ACTIVE; 965 return 0; 966} 967 968/* 969 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in 970 * port's r_port struct. Initializes the port hardware. 971 */ 972static int rp_open(struct tty_struct *tty, struct file *filp) 973{ 974 struct r_port *info; 975 int line = 0, retval; 976 CHANNEL_t *cp; 977 unsigned long page; 978 979 line = TTY_GET_LINE(tty); 980 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL)) 981 return -ENXIO; 982 983 page = __get_free_page(GFP_KERNEL); 984 if (!page) 985 return -ENOMEM; 986 987 if (info->flags & ROCKET_CLOSING) { 988 interruptible_sleep_on(&info->close_wait); 989 free_page(page); 990 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); 991 } 992 993 /* 994 * We must not sleep from here until the port is marked fully in use. 995 */ 996 if (info->xmit_buf) 997 free_page(page); 998 else 999 info->xmit_buf = (unsigned char *) page; 1000 1001 tty->driver_data = info; 1002 info->tty = tty; 1003 1004 if (info->count++ == 0) { 1005 atomic_inc(&rp_num_ports_open); 1006 1007#ifdef ROCKET_DEBUG_OPEN 1008 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open)); 1009#endif 1010 } 1011#ifdef ROCKET_DEBUG_OPEN 1012 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count); 1013#endif 1014 1015 /* 1016 * Info->count is now 1; so it's safe to sleep now. 1017 */ 1018 if ((info->flags & ROCKET_INITIALIZED) == 0) { 1019 cp = &info->channel; 1020 sSetRxTrigger(cp, TRIG_1); 1021 if (sGetChanStatus(cp) & CD_ACT) 1022 info->cd_status = 1; 1023 else 1024 info->cd_status = 0; 1025 sDisRxStatusMode(cp); 1026 sFlushRxFIFO(cp); 1027 sFlushTxFIFO(cp); 1028 1029 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN)); 1030 sSetRxTrigger(cp, TRIG_1); 1031 1032 sGetChanStatus(cp); 1033 sDisRxStatusMode(cp); 1034 sClrTxXOFF(cp); 1035 1036 sDisCTSFlowCtl(cp); 1037 sDisTxSoftFlowCtl(cp); 1038 1039 sEnRxFIFO(cp); 1040 sEnTransmit(cp); 1041 1042 info->flags |= ROCKET_INITIALIZED; 1043 1044 /* 1045 * Set up the tty->alt_speed kludge 1046 */ 1047 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI) 1048 info->tty->alt_speed = 57600; 1049 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI) 1050 info->tty->alt_speed = 115200; 1051 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI) 1052 info->tty->alt_speed = 230400; 1053 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP) 1054 info->tty->alt_speed = 460800; 1055 1056 configure_r_port(info, NULL); 1057 if (tty->termios->c_cflag & CBAUD) { 1058 sSetDTR(cp); 1059 sSetRTS(cp); 1060 } 1061 } 1062 /* Starts (or resets) the maint polling loop */ 1063 mod_timer(&rocket_timer, jiffies + POLL_PERIOD); 1064 1065 retval = block_til_ready(tty, filp, info); 1066 if (retval) { 1067#ifdef ROCKET_DEBUG_OPEN 1068 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval); 1069#endif 1070 return retval; 1071 } 1072 return 0; 1073} 1074 1075/* 1076 * Exception handler that closes a serial port. info->count is considered critical. 1077 */ 1078static void rp_close(struct tty_struct *tty, struct file *filp) 1079{ 1080 struct r_port *info = (struct r_port *) tty->driver_data; 1081 unsigned long flags; 1082 int timeout; 1083 CHANNEL_t *cp; 1084 1085 if (rocket_paranoia_check(info, "rp_close")) 1086 return; 1087 1088#ifdef ROCKET_DEBUG_OPEN 1089 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count); 1090#endif 1091 1092 if (tty_hung_up_p(filp)) 1093 return; 1094 spin_lock_irqsave(&info->slock, flags); 1095 1096 if ((tty->count == 1) && (info->count != 1)) { 1097 /* 1098 * Uh, oh. tty->count is 1, which means that the tty 1099 * structure will be freed. Info->count should always 1100 * be one in these conditions. If it's greater than 1101 * one, we've got real problems, since it means the 1102 * serial port won't be shutdown. 1103 */ 1104 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, " 1105 "info->count is %d\n", info->count); 1106 info->count = 1; 1107 } 1108 if (--info->count < 0) { 1109 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n", 1110 info->line, info->count); 1111 info->count = 0; 1112 } 1113 if (info->count) { 1114 spin_unlock_irqrestore(&info->slock, flags); 1115 return; 1116 } 1117 info->flags |= ROCKET_CLOSING; 1118 spin_unlock_irqrestore(&info->slock, flags); 1119 1120 cp = &info->channel; 1121 1122 /* 1123 * Notify the line discpline to only process XON/XOFF characters 1124 */ 1125 tty->closing = 1; 1126 1127 /* 1128 * If transmission was throttled by the application request, 1129 * just flush the xmit buffer. 1130 */ 1131 if (tty->flow_stopped) 1132 rp_flush_buffer(tty); 1133 1134 /* 1135 * Wait for the transmit buffer to clear 1136 */ 1137 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE) 1138 tty_wait_until_sent(tty, info->closing_wait); 1139 /* 1140 * Before we drop DTR, make sure the UART transmitter 1141 * has completely drained; this is especially 1142 * important if there is a transmit FIFO! 1143 */ 1144 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps; 1145 if (timeout == 0) 1146 timeout = 1; 1147 rp_wait_until_sent(tty, timeout); 1148 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 1149 1150 sDisTransmit(cp); 1151 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN)); 1152 sDisCTSFlowCtl(cp); 1153 sDisTxSoftFlowCtl(cp); 1154 sClrTxXOFF(cp); 1155 sFlushRxFIFO(cp); 1156 sFlushTxFIFO(cp); 1157 sClrRTS(cp); 1158 if (C_HUPCL(tty)) 1159 sClrDTR(cp); 1160 1161 if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty)) 1162 TTY_DRIVER_FLUSH_BUFFER(tty); 1163 1164 tty_ldisc_flush(tty); 1165 1166 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 1167 1168 if (info->blocked_open) { 1169 if (info->close_delay) { 1170 msleep_interruptible(jiffies_to_msecs(info->close_delay)); 1171 } 1172 wake_up_interruptible(&info->open_wait); 1173 } else { 1174 if (info->xmit_buf) { 1175 free_page((unsigned long) info->xmit_buf); 1176 info->xmit_buf = NULL; 1177 } 1178 } 1179 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE); 1180 tty->closing = 0; 1181 wake_up_interruptible(&info->close_wait); 1182 atomic_dec(&rp_num_ports_open); 1183 1184#ifdef ROCKET_DEBUG_OPEN 1185 printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open)); 1186 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line); 1187#endif 1188 1189} 1190 1191static void rp_set_termios(struct tty_struct *tty, 1192 struct ktermios *old_termios) 1193{ 1194 struct r_port *info = (struct r_port *) tty->driver_data; 1195 CHANNEL_t *cp; 1196 unsigned cflag; 1197 1198 if (rocket_paranoia_check(info, "rp_set_termios")) 1199 return; 1200 1201 cflag = tty->termios->c_cflag; 1202 1203 if (cflag == old_termios->c_cflag) 1204 return; 1205 1206 /* 1207 * This driver doesn't support CS5 or CS6 1208 */ 1209 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6)) 1210 tty->termios->c_cflag = 1211 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE)); 1212 1213 configure_r_port(info, old_termios); 1214 1215 cp = &info->channel; 1216 1217 /* Handle transition to B0 status */ 1218 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) { 1219 sClrDTR(cp); 1220 sClrRTS(cp); 1221 } 1222 1223 /* Handle transition away from B0 status */ 1224 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) { 1225 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS)) 1226 sSetRTS(cp); 1227 sSetDTR(cp); 1228 } 1229 1230 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) { 1231 tty->hw_stopped = 0; 1232 rp_start(tty); 1233 } 1234} 1235 1236static void rp_break(struct tty_struct *tty, int break_state) 1237{ 1238 struct r_port *info = (struct r_port *) tty->driver_data; 1239 unsigned long flags; 1240 1241 if (rocket_paranoia_check(info, "rp_break")) 1242 return; 1243 1244 spin_lock_irqsave(&info->slock, flags); 1245 if (break_state == -1) 1246 sSendBreak(&info->channel); 1247 else 1248 sClrBreak(&info->channel); 1249 spin_unlock_irqrestore(&info->slock, flags); 1250} 1251 1252/* 1253 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for 1254 * the UPCI boards was added, it was decided to make this a function because 1255 * the macro was getting too complicated. All cases except the first one 1256 * (UPCIRingInd) are taken directly from the original macro. 1257 */ 1258static int sGetChanRI(CHANNEL_T * ChP) 1259{ 1260 CONTROLLER_t *CtlP = ChP->CtlP; 1261 int ChanNum = ChP->ChanNum; 1262 int RingInd = 0; 1263 1264 if (CtlP->UPCIRingInd) 1265 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]); 1266 else if (CtlP->AltChanRingIndicator) 1267 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT; 1268 else if (CtlP->boardType == ROCKET_TYPE_PC104) 1269 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]); 1270 1271 return RingInd; 1272} 1273 1274/********************************************************************************************/ 1275/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */ 1276 1277/* 1278 * Returns the state of the serial modem control lines. These next 2 functions 1279 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs. 1280 */ 1281static int rp_tiocmget(struct tty_struct *tty, struct file *file) 1282{ 1283 struct r_port *info = (struct r_port *)tty->driver_data; 1284 unsigned int control, result, ChanStatus; 1285 1286 ChanStatus = sGetChanStatusLo(&info->channel); 1287 control = info->channel.TxControl[3]; 1288 result = ((control & SET_RTS) ? TIOCM_RTS : 0) | 1289 ((control & SET_DTR) ? TIOCM_DTR : 0) | 1290 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) | 1291 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) | 1292 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) | 1293 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0); 1294 1295 return result; 1296} 1297 1298/* 1299 * Sets the modem control lines 1300 */ 1301static int rp_tiocmset(struct tty_struct *tty, struct file *file, 1302 unsigned int set, unsigned int clear) 1303{ 1304 struct r_port *info = (struct r_port *)tty->driver_data; 1305 1306 if (set & TIOCM_RTS) 1307 info->channel.TxControl[3] |= SET_RTS; 1308 if (set & TIOCM_DTR) 1309 info->channel.TxControl[3] |= SET_DTR; 1310 if (clear & TIOCM_RTS) 1311 info->channel.TxControl[3] &= ~SET_RTS; 1312 if (clear & TIOCM_DTR) 1313 info->channel.TxControl[3] &= ~SET_DTR; 1314 1315 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0])); 1316 return 0; 1317} 1318 1319static int get_config(struct r_port *info, struct rocket_config __user *retinfo) 1320{ 1321 struct rocket_config tmp; 1322 1323 if (!retinfo) 1324 return -EFAULT; 1325 memset(&tmp, 0, sizeof (tmp)); 1326 tmp.line = info->line; 1327 tmp.flags = info->flags; 1328 tmp.close_delay = info->close_delay; 1329 tmp.closing_wait = info->closing_wait; 1330 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3]; 1331 1332 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo))) 1333 return -EFAULT; 1334 return 0; 1335} 1336 1337static int set_config(struct r_port *info, struct rocket_config __user *new_info) 1338{ 1339 struct rocket_config new_serial; 1340 1341 if (copy_from_user(&new_serial, new_info, sizeof (new_serial))) 1342 return -EFAULT; 1343 1344 if (!capable(CAP_SYS_ADMIN)) 1345 { 1346 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) 1347 return -EPERM; 1348 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK)); 1349 configure_r_port(info, NULL); 1350 return 0; 1351 } 1352 1353 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS)); 1354 info->close_delay = new_serial.close_delay; 1355 info->closing_wait = new_serial.closing_wait; 1356 1357 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI) 1358 info->tty->alt_speed = 57600; 1359 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI) 1360 info->tty->alt_speed = 115200; 1361 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI) 1362 info->tty->alt_speed = 230400; 1363 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP) 1364 info->tty->alt_speed = 460800; 1365 1366 configure_r_port(info, NULL); 1367 return 0; 1368} 1369 1370/* 1371 * This function fills in a rocket_ports struct with information 1372 * about what boards/ports are in the system. This info is passed 1373 * to user space. See setrocket.c where the info is used to create 1374 * the /dev/ttyRx ports. 1375 */ 1376static int get_ports(struct r_port *info, struct rocket_ports __user *retports) 1377{ 1378 struct rocket_ports tmp; 1379 int board; 1380 1381 if (!retports) 1382 return -EFAULT; 1383 memset(&tmp, 0, sizeof (tmp)); 1384 tmp.tty_major = rocket_driver->major; 1385 1386 for (board = 0; board < 4; board++) { 1387 tmp.rocketModel[board].model = rocketModel[board].model; 1388 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString); 1389 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts; 1390 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2; 1391 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber; 1392 } 1393 if (copy_to_user(retports, &tmp, sizeof (*retports))) 1394 return -EFAULT; 1395 return 0; 1396} 1397 1398static int reset_rm2(struct r_port *info, void __user *arg) 1399{ 1400 int reset; 1401 1402 if (copy_from_user(&reset, arg, sizeof (int))) 1403 return -EFAULT; 1404 if (reset) 1405 reset = 1; 1406 1407 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII && 1408 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII) 1409 return -EINVAL; 1410 1411 if (info->ctlp->BusType == isISA) 1412 sModemReset(info->ctlp, info->chan, reset); 1413 else 1414 sPCIModemReset(info->ctlp, info->chan, reset); 1415 1416 return 0; 1417} 1418 1419static int get_version(struct r_port *info, struct rocket_version __user *retvers) 1420{ 1421 if (copy_to_user(retvers, &driver_version, sizeof (*retvers))) 1422 return -EFAULT; 1423 return 0; 1424} 1425 1426/* IOCTL call handler into the driver */ 1427static int rp_ioctl(struct tty_struct *tty, struct file *file, 1428 unsigned int cmd, unsigned long arg) 1429{ 1430 struct r_port *info = (struct r_port *) tty->driver_data; 1431 void __user *argp = (void __user *)arg; 1432 1433 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl")) 1434 return -ENXIO; 1435 1436 switch (cmd) { 1437 case RCKP_GET_STRUCT: 1438 if (copy_to_user(argp, info, sizeof (struct r_port))) 1439 return -EFAULT; 1440 return 0; 1441 case RCKP_GET_CONFIG: 1442 return get_config(info, argp); 1443 case RCKP_SET_CONFIG: 1444 return set_config(info, argp); 1445 case RCKP_GET_PORTS: 1446 return get_ports(info, argp); 1447 case RCKP_RESET_RM2: 1448 return reset_rm2(info, argp); 1449 case RCKP_GET_VERSION: 1450 return get_version(info, argp); 1451 default: 1452 return -ENOIOCTLCMD; 1453 } 1454 return 0; 1455} 1456 1457static void rp_send_xchar(struct tty_struct *tty, char ch) 1458{ 1459 struct r_port *info = (struct r_port *) tty->driver_data; 1460 CHANNEL_t *cp; 1461 1462 if (rocket_paranoia_check(info, "rp_send_xchar")) 1463 return; 1464 1465 cp = &info->channel; 1466 if (sGetTxCnt(cp)) 1467 sWriteTxPrioByte(cp, ch); 1468 else 1469 sWriteTxByte(sGetTxRxDataIO(cp), ch); 1470} 1471 1472static void rp_throttle(struct tty_struct *tty) 1473{ 1474 struct r_port *info = (struct r_port *) tty->driver_data; 1475 CHANNEL_t *cp; 1476 1477#ifdef ROCKET_DEBUG_THROTTLE 1478 printk(KERN_INFO "throttle %s: %d....\n", tty->name, 1479 tty->ldisc.chars_in_buffer(tty)); 1480#endif 1481 1482 if (rocket_paranoia_check(info, "rp_throttle")) 1483 return; 1484 1485 cp = &info->channel; 1486 if (I_IXOFF(tty)) 1487 rp_send_xchar(tty, STOP_CHAR(tty)); 1488 1489 sClrRTS(&info->channel); 1490} 1491 1492static void rp_unthrottle(struct tty_struct *tty) 1493{ 1494 struct r_port *info = (struct r_port *) tty->driver_data; 1495 CHANNEL_t *cp; 1496#ifdef ROCKET_DEBUG_THROTTLE 1497 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name, 1498 tty->ldisc.chars_in_buffer(tty)); 1499#endif 1500 1501 if (rocket_paranoia_check(info, "rp_throttle")) 1502 return; 1503 1504 cp = &info->channel; 1505 if (I_IXOFF(tty)) 1506 rp_send_xchar(tty, START_CHAR(tty)); 1507 1508 sSetRTS(&info->channel); 1509} 1510 1511/* 1512 * ------------------------------------------------------------ 1513 * rp_stop() and rp_start() 1514 * 1515 * This routines are called before setting or resetting tty->stopped. 1516 * They enable or disable transmitter interrupts, as necessary. 1517 * ------------------------------------------------------------ 1518 */ 1519static void rp_stop(struct tty_struct *tty) 1520{ 1521 struct r_port *info = (struct r_port *) tty->driver_data; 1522 1523#ifdef ROCKET_DEBUG_FLOW 1524 printk(KERN_INFO "stop %s: %d %d....\n", tty->name, 1525 info->xmit_cnt, info->xmit_fifo_room); 1526#endif 1527 1528 if (rocket_paranoia_check(info, "rp_stop")) 1529 return; 1530 1531 if (sGetTxCnt(&info->channel)) 1532 sDisTransmit(&info->channel); 1533} 1534 1535static void rp_start(struct tty_struct *tty) 1536{ 1537 struct r_port *info = (struct r_port *) tty->driver_data; 1538 1539#ifdef ROCKET_DEBUG_FLOW 1540 printk(KERN_INFO "start %s: %d %d....\n", tty->name, 1541 info->xmit_cnt, info->xmit_fifo_room); 1542#endif 1543 1544 if (rocket_paranoia_check(info, "rp_stop")) 1545 return; 1546 1547 sEnTransmit(&info->channel); 1548 set_bit((info->aiop * 8) + info->chan, 1549 (void *) &xmit_flags[info->board]); 1550} 1551 1552/* 1553 * rp_wait_until_sent() --- wait until the transmitter is empty 1554 */ 1555static void rp_wait_until_sent(struct tty_struct *tty, int timeout) 1556{ 1557 struct r_port *info = (struct r_port *) tty->driver_data; 1558 CHANNEL_t *cp; 1559 unsigned long orig_jiffies; 1560 int check_time, exit_time; 1561 int txcnt; 1562 1563 if (rocket_paranoia_check(info, "rp_wait_until_sent")) 1564 return; 1565 1566 cp = &info->channel; 1567 1568 orig_jiffies = jiffies; 1569#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT 1570 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout, 1571 jiffies); 1572 printk(KERN_INFO "cps=%d...", info->cps); 1573#endif 1574 while (1) { 1575 txcnt = sGetTxCnt(cp); 1576 if (!txcnt) { 1577 if (sGetChanStatusLo(cp) & TXSHRMT) 1578 break; 1579 check_time = (HZ / info->cps) / 5; 1580 } else { 1581 check_time = HZ * txcnt / info->cps; 1582 } 1583 if (timeout) { 1584 exit_time = orig_jiffies + timeout - jiffies; 1585 if (exit_time <= 0) 1586 break; 1587 if (exit_time < check_time) 1588 check_time = exit_time; 1589 } 1590 if (check_time == 0) 1591 check_time = 1; 1592#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT 1593 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time); 1594#endif 1595 msleep_interruptible(jiffies_to_msecs(check_time)); 1596 if (signal_pending(current)) 1597 break; 1598 } 1599 __set_current_state(TASK_RUNNING); 1600#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT 1601 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies); 1602#endif 1603} 1604 1605/* 1606 * rp_hangup() --- called by tty_hangup() when a hangup is signaled. 1607 */ 1608static void rp_hangup(struct tty_struct *tty) 1609{ 1610 CHANNEL_t *cp; 1611 struct r_port *info = (struct r_port *) tty->driver_data; 1612 1613 if (rocket_paranoia_check(info, "rp_hangup")) 1614 return; 1615 1616#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP)) 1617 printk(KERN_INFO "rp_hangup of ttyR%d...", info->line); 1618#endif 1619 rp_flush_buffer(tty); 1620 if (info->flags & ROCKET_CLOSING) 1621 return; 1622 if (info->count) 1623 atomic_dec(&rp_num_ports_open); 1624 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 1625 1626 info->count = 0; 1627 info->flags &= ~ROCKET_NORMAL_ACTIVE; 1628 info->tty = NULL; 1629 1630 cp = &info->channel; 1631 sDisRxFIFO(cp); 1632 sDisTransmit(cp); 1633 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN)); 1634 sDisCTSFlowCtl(cp); 1635 sDisTxSoftFlowCtl(cp); 1636 sClrTxXOFF(cp); 1637 info->flags &= ~ROCKET_INITIALIZED; 1638 1639 wake_up_interruptible(&info->open_wait); 1640} 1641 1642/* 1643 * Exception handler - write char routine. The RocketPort driver uses a 1644 * double-buffering strategy, with the twist that if the in-memory CPU 1645 * buffer is empty, and there's space in the transmit FIFO, the 1646 * writing routines will write directly to transmit FIFO. 1647 * Write buffer and counters protected by spinlocks 1648 */ 1649static void rp_put_char(struct tty_struct *tty, unsigned char ch) 1650{ 1651 struct r_port *info = (struct r_port *) tty->driver_data; 1652 CHANNEL_t *cp; 1653 unsigned long flags; 1654 1655 if (rocket_paranoia_check(info, "rp_put_char")) 1656 return; 1657 1658 /* 1659 * Grab the port write mutex, locking out other processes that try to 1660 * write to this port 1661 */ 1662 mutex_lock(&info->write_mtx); 1663 1664#ifdef ROCKET_DEBUG_WRITE 1665 printk(KERN_INFO "rp_put_char %c...", ch); 1666#endif 1667 1668 spin_lock_irqsave(&info->slock, flags); 1669 cp = &info->channel; 1670 1671 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0) 1672 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp); 1673 1674 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) { 1675 info->xmit_buf[info->xmit_head++] = ch; 1676 info->xmit_head &= XMIT_BUF_SIZE - 1; 1677 info->xmit_cnt++; 1678 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 1679 } else { 1680 sOutB(sGetTxRxDataIO(cp), ch); 1681 info->xmit_fifo_room--; 1682 } 1683 spin_unlock_irqrestore(&info->slock, flags); 1684 mutex_unlock(&info->write_mtx); 1685} 1686 1687/* 1688 * Exception handler - write routine, called when user app writes to the device. 1689 * A per port write mutex is used to protect from another process writing to 1690 * this port at the same time. This other process could be running on the other CPU 1691 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out). 1692 * Spinlocks protect the info xmit members. 1693 */ 1694static int rp_write(struct tty_struct *tty, 1695 const unsigned char *buf, int count) 1696{ 1697 struct r_port *info = (struct r_port *) tty->driver_data; 1698 CHANNEL_t *cp; 1699 const unsigned char *b; 1700 int c, retval = 0; 1701 unsigned long flags; 1702 1703 if (count <= 0 || rocket_paranoia_check(info, "rp_write")) 1704 return 0; 1705 1706 mutex_lock_interruptible(&info->write_mtx); 1707 1708#ifdef ROCKET_DEBUG_WRITE 1709 printk(KERN_INFO "rp_write %d chars...", count); 1710#endif 1711 cp = &info->channel; 1712 1713 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count) 1714 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp); 1715 1716 /* 1717 * If the write queue for the port is empty, and there is FIFO space, stuff bytes 1718 * into FIFO. Use the write queue for temp storage. 1719 */ 1720 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) { 1721 c = min(count, info->xmit_fifo_room); 1722 b = buf; 1723 1724 /* Push data into FIFO, 2 bytes at a time */ 1725 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2); 1726 1727 /* If there is a byte remaining, write it */ 1728 if (c & 1) 1729 sOutB(sGetTxRxDataIO(cp), b[c - 1]); 1730 1731 retval += c; 1732 buf += c; 1733 count -= c; 1734 1735 spin_lock_irqsave(&info->slock, flags); 1736 info->xmit_fifo_room -= c; 1737 spin_unlock_irqrestore(&info->slock, flags); 1738 } 1739 1740 /* If count is zero, we wrote it all and are done */ 1741 if (!count) 1742 goto end; 1743 1744 /* Write remaining data into the port's xmit_buf */ 1745 while (1) { 1746 if (info->tty == 0) /* Seemingly obligatory check... */ 1747 goto end; 1748 1749 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head)); 1750 if (c <= 0) 1751 break; 1752 1753 b = buf; 1754 memcpy(info->xmit_buf + info->xmit_head, b, c); 1755 1756 spin_lock_irqsave(&info->slock, flags); 1757 info->xmit_head = 1758 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1); 1759 info->xmit_cnt += c; 1760 spin_unlock_irqrestore(&info->slock, flags); 1761 1762 buf += c; 1763 count -= c; 1764 retval += c; 1765 } 1766 1767 if ((retval > 0) && !tty->stopped && !tty->hw_stopped) 1768 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); 1769 1770end: 1771 if (info->xmit_cnt < WAKEUP_CHARS) { 1772 tty_wakeup(tty); 1773#ifdef ROCKETPORT_HAVE_POLL_WAIT 1774 wake_up_interruptible(&tty->poll_wait); 1775#endif 1776 } 1777 mutex_unlock(&info->write_mtx); 1778 return retval; 1779} 1780 1781/* 1782 * Return the number of characters that can be sent. We estimate 1783 * only using the in-memory transmit buffer only, and ignore the 1784 * potential space in the transmit FIFO. 1785 */ 1786static int rp_write_room(struct tty_struct *tty) 1787{ 1788 struct r_port *info = (struct r_port *) tty->driver_data; 1789 int ret; 1790 1791 if (rocket_paranoia_check(info, "rp_write_room")) 1792 return 0; 1793 1794 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1; 1795 if (ret < 0) 1796 ret = 0; 1797#ifdef ROCKET_DEBUG_WRITE 1798 printk(KERN_INFO "rp_write_room returns %d...", ret); 1799#endif 1800 return ret; 1801} 1802 1803/* 1804 * Return the number of characters in the buffer. Again, this only 1805 * counts those characters in the in-memory transmit buffer. 1806 */ 1807static int rp_chars_in_buffer(struct tty_struct *tty) 1808{ 1809 struct r_port *info = (struct r_port *) tty->driver_data; 1810 CHANNEL_t *cp; 1811 1812 if (rocket_paranoia_check(info, "rp_chars_in_buffer")) 1813 return 0; 1814 1815 cp = &info->channel; 1816 1817#ifdef ROCKET_DEBUG_WRITE 1818 printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt); 1819#endif 1820 return info->xmit_cnt; 1821} 1822 1823/* 1824 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the 1825 * r_port struct for the port. Note that spinlock are used to protect info members, 1826 * do not call this function if the spinlock is already held. 1827 */ 1828static void rp_flush_buffer(struct tty_struct *tty) 1829{ 1830 struct r_port *info = (struct r_port *) tty->driver_data; 1831 CHANNEL_t *cp; 1832 unsigned long flags; 1833 1834 if (rocket_paranoia_check(info, "rp_flush_buffer")) 1835 return; 1836 1837 spin_lock_irqsave(&info->slock, flags); 1838 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 1839 spin_unlock_irqrestore(&info->slock, flags); 1840 1841#ifdef ROCKETPORT_HAVE_POLL_WAIT 1842 wake_up_interruptible(&tty->poll_wait); 1843#endif 1844 tty_wakeup(tty); 1845 1846 cp = &info->channel; 1847 sFlushTxFIFO(cp); 1848} 1849 1850#ifdef CONFIG_PCI 1851 1852static struct pci_device_id __devinitdata rocket_pci_ids[] = { 1853 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) }, 1854 { } 1855}; 1856MODULE_DEVICE_TABLE(pci, rocket_pci_ids); 1857 1858/* 1859 * Called when a PCI card is found. Retrieves and stores model information, 1860 * init's aiopic and serial port hardware. 1861 * Inputs: i is the board number (0-n) 1862 */ 1863static __init int register_PCI(int i, struct pci_dev *dev) 1864{ 1865 int num_aiops, aiop, max_num_aiops, num_chan, chan; 1866 unsigned int aiopio[MAX_AIOPS_PER_BOARD]; 1867 char *str, *board_type; 1868 CONTROLLER_t *ctlp; 1869 1870 int fast_clock = 0; 1871 int altChanRingIndicator = 0; 1872 int ports_per_aiop = 8; 1873 int ret; 1874 unsigned int class_rev; 1875 WordIO_t ConfigIO = 0; 1876 ByteIO_t UPCIRingInd = 0; 1877 1878 if (!dev || pci_enable_device(dev)) 1879 return 0; 1880 1881 rcktpt_io_addr[i] = pci_resource_start(dev, 0); 1882 ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 1883 1884 if (ret) { 1885 printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n"); 1886 return 0; 1887 } 1888 1889 rcktpt_type[i] = ROCKET_TYPE_NORMAL; 1890 rocketModel[i].loadrm2 = 0; 1891 rocketModel[i].startingPortNumber = nextLineNumber; 1892 1893 /* Depending on the model, set up some config variables */ 1894 switch (dev->device) { 1895 case PCI_DEVICE_ID_RP4QUAD: 1896 str = "Quadcable"; 1897 max_num_aiops = 1; 1898 ports_per_aiop = 4; 1899 rocketModel[i].model = MODEL_RP4QUAD; 1900 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable"); 1901 rocketModel[i].numPorts = 4; 1902 break; 1903 case PCI_DEVICE_ID_RP8OCTA: 1904 str = "Octacable"; 1905 max_num_aiops = 1; 1906 rocketModel[i].model = MODEL_RP8OCTA; 1907 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable"); 1908 rocketModel[i].numPorts = 8; 1909 break; 1910 case PCI_DEVICE_ID_URP8OCTA: 1911 str = "Octacable"; 1912 max_num_aiops = 1; 1913 rocketModel[i].model = MODEL_UPCI_RP8OCTA; 1914 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable"); 1915 rocketModel[i].numPorts = 8; 1916 break; 1917 case PCI_DEVICE_ID_RP8INTF: 1918 str = "8"; 1919 max_num_aiops = 1; 1920 rocketModel[i].model = MODEL_RP8INTF; 1921 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F"); 1922 rocketModel[i].numPorts = 8; 1923 break; 1924 case PCI_DEVICE_ID_URP8INTF: 1925 str = "8"; 1926 max_num_aiops = 1; 1927 rocketModel[i].model = MODEL_UPCI_RP8INTF; 1928 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F"); 1929 rocketModel[i].numPorts = 8; 1930 break; 1931 case PCI_DEVICE_ID_RP8J: 1932 str = "8J"; 1933 max_num_aiops = 1; 1934 rocketModel[i].model = MODEL_RP8J; 1935 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors"); 1936 rocketModel[i].numPorts = 8; 1937 break; 1938 case PCI_DEVICE_ID_RP4J: 1939 str = "4J"; 1940 max_num_aiops = 1; 1941 ports_per_aiop = 4; 1942 rocketModel[i].model = MODEL_RP4J; 1943 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors"); 1944 rocketModel[i].numPorts = 4; 1945 break; 1946 case PCI_DEVICE_ID_RP8SNI: 1947 str = "8 (DB78 Custom)"; 1948 max_num_aiops = 1; 1949 rocketModel[i].model = MODEL_RP8SNI; 1950 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78"); 1951 rocketModel[i].numPorts = 8; 1952 break; 1953 case PCI_DEVICE_ID_RP16SNI: 1954 str = "16 (DB78 Custom)"; 1955 max_num_aiops = 2; 1956 rocketModel[i].model = MODEL_RP16SNI; 1957 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78"); 1958 rocketModel[i].numPorts = 16; 1959 break; 1960 case PCI_DEVICE_ID_RP16INTF: 1961 str = "16"; 1962 max_num_aiops = 2; 1963 rocketModel[i].model = MODEL_RP16INTF; 1964 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F"); 1965 rocketModel[i].numPorts = 16; 1966 break; 1967 case PCI_DEVICE_ID_URP16INTF: 1968 str = "16"; 1969 max_num_aiops = 2; 1970 rocketModel[i].model = MODEL_UPCI_RP16INTF; 1971 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F"); 1972 rocketModel[i].numPorts = 16; 1973 break; 1974 case PCI_DEVICE_ID_CRP16INTF: 1975 str = "16"; 1976 max_num_aiops = 2; 1977 rocketModel[i].model = MODEL_CPCI_RP16INTF; 1978 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F"); 1979 rocketModel[i].numPorts = 16; 1980 break; 1981 case PCI_DEVICE_ID_RP32INTF: 1982 str = "32"; 1983 max_num_aiops = 4; 1984 rocketModel[i].model = MODEL_RP32INTF; 1985 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F"); 1986 rocketModel[i].numPorts = 32; 1987 break; 1988 case PCI_DEVICE_ID_URP32INTF: 1989 str = "32"; 1990 max_num_aiops = 4; 1991 rocketModel[i].model = MODEL_UPCI_RP32INTF; 1992 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F"); 1993 rocketModel[i].numPorts = 32; 1994 break; 1995 case PCI_DEVICE_ID_RPP4: 1996 str = "Plus Quadcable"; 1997 max_num_aiops = 1; 1998 ports_per_aiop = 4; 1999 altChanRingIndicator++; 2000 fast_clock++; 2001 rocketModel[i].model = MODEL_RPP4; 2002 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port"); 2003 rocketModel[i].numPorts = 4; 2004 break; 2005 case PCI_DEVICE_ID_RPP8: 2006 str = "Plus Octacable"; 2007 max_num_aiops = 2; 2008 ports_per_aiop = 4; 2009 altChanRingIndicator++; 2010 fast_clock++; 2011 rocketModel[i].model = MODEL_RPP8; 2012 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port"); 2013 rocketModel[i].numPorts = 8; 2014 break; 2015 case PCI_DEVICE_ID_RP2_232: 2016 str = "Plus 2 (RS-232)"; 2017 max_num_aiops = 1; 2018 ports_per_aiop = 2; 2019 altChanRingIndicator++; 2020 fast_clock++; 2021 rocketModel[i].model = MODEL_RP2_232; 2022 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232"); 2023 rocketModel[i].numPorts = 2; 2024 break; 2025 case PCI_DEVICE_ID_RP2_422: 2026 str = "Plus 2 (RS-422)"; 2027 max_num_aiops = 1; 2028 ports_per_aiop = 2; 2029 altChanRingIndicator++; 2030 fast_clock++; 2031 rocketModel[i].model = MODEL_RP2_422; 2032 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422"); 2033 rocketModel[i].numPorts = 2; 2034 break; 2035 case PCI_DEVICE_ID_RP6M: 2036 2037 max_num_aiops = 1; 2038 ports_per_aiop = 6; 2039 str = "6-port"; 2040 2041 /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */ 2042 if ((class_rev & 0xFF) == 1) { 2043 rcktpt_type[i] = ROCKET_TYPE_MODEMII; 2044 rocketModel[i].loadrm2 = 1; 2045 } else { 2046 rcktpt_type[i] = ROCKET_TYPE_MODEM; 2047 } 2048 2049 rocketModel[i].model = MODEL_RP6M; 2050 strcpy(rocketModel[i].modelString, "RocketModem 6 port"); 2051 rocketModel[i].numPorts = 6; 2052 break; 2053 case PCI_DEVICE_ID_RP4M: 2054 max_num_aiops = 1; 2055 ports_per_aiop = 4; 2056 str = "4-port"; 2057 if ((class_rev & 0xFF) == 1) { 2058 rcktpt_type[i] = ROCKET_TYPE_MODEMII; 2059 rocketModel[i].loadrm2 = 1; 2060 } else { 2061 rcktpt_type[i] = ROCKET_TYPE_MODEM; 2062 } 2063 2064 rocketModel[i].model = MODEL_RP4M; 2065 strcpy(rocketModel[i].modelString, "RocketModem 4 port"); 2066 rocketModel[i].numPorts = 4; 2067 break; 2068 default: 2069 str = "(unknown/unsupported)"; 2070 max_num_aiops = 0; 2071 break; 2072 } 2073 2074 /* 2075 * Check for UPCI boards. 2076 */ 2077 2078 switch (dev->device) { 2079 case PCI_DEVICE_ID_URP32INTF: 2080 case PCI_DEVICE_ID_URP8INTF: 2081 case PCI_DEVICE_ID_URP16INTF: 2082 case PCI_DEVICE_ID_CRP16INTF: 2083 case PCI_DEVICE_ID_URP8OCTA: 2084 rcktpt_io_addr[i] = pci_resource_start(dev, 2); 2085 ConfigIO = pci_resource_start(dev, 1); 2086 if (dev->device == PCI_DEVICE_ID_URP8OCTA) { 2087 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND; 2088 2089 /* 2090 * Check for octa or quad cable. 2091 */ 2092 if (! 2093 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) & 2094 PCI_GPIO_CTRL_8PORT)) { 2095 str = "Quadcable"; 2096 ports_per_aiop = 4; 2097 rocketModel[i].numPorts = 4; 2098 } 2099 } 2100 break; 2101 case PCI_DEVICE_ID_UPCI_RM3_8PORT: 2102 str = "8 ports"; 2103 max_num_aiops = 1; 2104 rocketModel[i].model = MODEL_UPCI_RM3_8PORT; 2105 strcpy(rocketModel[i].modelString, "RocketModem III 8 port"); 2106 rocketModel[i].numPorts = 8; 2107 rcktpt_io_addr[i] = pci_resource_start(dev, 2); 2108 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND; 2109 ConfigIO = pci_resource_start(dev, 1); 2110 rcktpt_type[i] = ROCKET_TYPE_MODEMIII; 2111 break; 2112 case PCI_DEVICE_ID_UPCI_RM3_4PORT: 2113 str = "4 ports"; 2114 max_num_aiops = 1; 2115 rocketModel[i].model = MODEL_UPCI_RM3_4PORT; 2116 strcpy(rocketModel[i].modelString, "RocketModem III 4 port"); 2117 rocketModel[i].numPorts = 4; 2118 rcktpt_io_addr[i] = pci_resource_start(dev, 2); 2119 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND; 2120 ConfigIO = pci_resource_start(dev, 1); 2121 rcktpt_type[i] = ROCKET_TYPE_MODEMIII; 2122 break; 2123 default: 2124 break; 2125 } 2126 2127 switch (rcktpt_type[i]) { 2128 case ROCKET_TYPE_MODEM: 2129 board_type = "RocketModem"; 2130 break; 2131 case ROCKET_TYPE_MODEMII: 2132 board_type = "RocketModem II"; 2133 break; 2134 case ROCKET_TYPE_MODEMIII: 2135 board_type = "RocketModem III"; 2136 break; 2137 default: 2138 board_type = "RocketPort"; 2139 break; 2140 } 2141 2142 if (fast_clock) { 2143 sClockPrescale = 0x12; /* mod 2 (divide by 3) */ 2144 rp_baud_base[i] = 921600; 2145 } else { 2146 /* 2147 * If support_low_speed is set, use the slow clock 2148 * prescale, which supports 50 bps 2149 */ 2150 if (support_low_speed) { 2151 /* mod 9 (divide by 10) prescale */ 2152 sClockPrescale = 0x19; 2153 rp_baud_base[i] = 230400; 2154 } else { 2155 /* mod 4 (devide by 5) prescale */ 2156 sClockPrescale = 0x14; 2157 rp_baud_base[i] = 460800; 2158 } 2159 } 2160 2161 for (aiop = 0; aiop < max_num_aiops; aiop++) 2162 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40); 2163 ctlp = sCtlNumToCtlPtr(i); 2164 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd); 2165 for (aiop = 0; aiop < max_num_aiops; aiop++) 2166 ctlp->AiopNumChan[aiop] = ports_per_aiop; 2167 2168 printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, " 2169 "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev), 2170 rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString); 2171 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n", 2172 rocketModel[i].modelString, 2173 rocketModel[i].startingPortNumber, 2174 rocketModel[i].startingPortNumber + 2175 rocketModel[i].numPorts - 1); 2176 2177 if (num_aiops <= 0) { 2178 rcktpt_io_addr[i] = 0; 2179 return (0); 2180 } 2181 is_PCI[i] = 1; 2182 2183 /* Reset the AIOPIC, init the serial ports */ 2184 for (aiop = 0; aiop < num_aiops; aiop++) { 2185 sResetAiopByNum(ctlp, aiop); 2186 num_chan = ports_per_aiop; 2187 for (chan = 0; chan < num_chan; chan++) 2188 init_r_port(i, aiop, chan, dev); 2189 } 2190 2191 /* Rocket modems must be reset */ 2192 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || 2193 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) || 2194 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) { 2195 num_chan = ports_per_aiop; 2196 for (chan = 0; chan < num_chan; chan++) 2197 sPCIModemReset(ctlp, chan, 1); 2198 mdelay(500); 2199 for (chan = 0; chan < num_chan; chan++) 2200 sPCIModemReset(ctlp, chan, 0); 2201 mdelay(500); 2202 rmSpeakerReset(ctlp, rocketModel[i].model); 2203 } 2204 return (1); 2205} 2206 2207/* 2208 * Probes for PCI cards, inits them if found 2209 * Input: board_found = number of ISA boards already found, or the 2210 * starting board number 2211 * Returns: Number of PCI boards found 2212 */ 2213static int __init init_PCI(int boards_found) 2214{ 2215 struct pci_dev *dev = NULL; 2216 int count = 0; 2217 2218 /* Work through the PCI device list, pulling out ours */ 2219 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) { 2220 if (register_PCI(count + boards_found, dev)) 2221 count++; 2222 } 2223 return (count); 2224} 2225 2226#endif /* CONFIG_PCI */ 2227 2228/* 2229 * Probes for ISA cards 2230 * Input: i = the board number to look for 2231 * Returns: 1 if board found, 0 else 2232 */ 2233static int __init init_ISA(int i) 2234{ 2235 int num_aiops, num_chan = 0, total_num_chan = 0; 2236 int aiop, chan; 2237 unsigned int aiopio[MAX_AIOPS_PER_BOARD]; 2238 CONTROLLER_t *ctlp; 2239 char *type_string; 2240 2241 /* If io_addr is zero, no board configured */ 2242 if (rcktpt_io_addr[i] == 0) 2243 return (0); 2244 2245 /* Reserve the IO region */ 2246 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) { 2247 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]); 2248 rcktpt_io_addr[i] = 0; 2249 return (0); 2250 } 2251 2252 ctlp = sCtlNumToCtlPtr(i); 2253 2254 ctlp->boardType = rcktpt_type[i]; 2255 2256 switch (rcktpt_type[i]) { 2257 case ROCKET_TYPE_PC104: 2258 type_string = "(PC104)"; 2259 break; 2260 case ROCKET_TYPE_MODEM: 2261 type_string = "(RocketModem)"; 2262 break; 2263 case ROCKET_TYPE_MODEMII: 2264 type_string = "(RocketModem II)"; 2265 break; 2266 default: 2267 type_string = ""; 2268 break; 2269 } 2270 2271 /* 2272 * If support_low_speed is set, use the slow clock prescale, 2273 * which supports 50 bps 2274 */ 2275 if (support_low_speed) { 2276 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */ 2277 rp_baud_base[i] = 230400; 2278 } else { 2279 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */ 2280 rp_baud_base[i] = 460800; 2281 } 2282 2283 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++) 2284 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400); 2285 2286 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0); 2287 2288 if (ctlp->boardType == ROCKET_TYPE_PC104) { 2289 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */ 2290 sEnAiop(ctlp, 3); /* CSels used for other stuff */ 2291 } 2292 2293 /* If something went wrong initing the AIOP's release the ISA IO memory */ 2294 if (num_aiops <= 0) { 2295 release_region(rcktpt_io_addr[i], 64); 2296 rcktpt_io_addr[i] = 0; 2297 return (0); 2298 } 2299 2300 rocketModel[i].startingPortNumber = nextLineNumber; 2301 2302 for (aiop = 0; aiop < num_aiops; aiop++) { 2303 sResetAiopByNum(ctlp, aiop); 2304 sEnAiop(ctlp, aiop); 2305 num_chan = sGetAiopNumChan(ctlp, aiop); 2306 total_num_chan += num_chan; 2307 for (chan = 0; chan < num_chan; chan++) 2308 init_r_port(i, aiop, chan, NULL); 2309 } 2310 is_PCI[i] = 0; 2311 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) { 2312 num_chan = sGetAiopNumChan(ctlp, 0); 2313 total_num_chan = num_chan; 2314 for (chan = 0; chan < num_chan; chan++) 2315 sModemReset(ctlp, chan, 1); 2316 mdelay(500); 2317 for (chan = 0; chan < num_chan; chan++) 2318 sModemReset(ctlp, chan, 0); 2319 mdelay(500); 2320 strcpy(rocketModel[i].modelString, "RocketModem ISA"); 2321 } else { 2322 strcpy(rocketModel[i].modelString, "RocketPort ISA"); 2323 } 2324 rocketModel[i].numPorts = total_num_chan; 2325 rocketModel[i].model = MODEL_ISA; 2326 2327 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n", 2328 i, rcktpt_io_addr[i], num_aiops, type_string); 2329 2330 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n", 2331 rocketModel[i].modelString, 2332 rocketModel[i].startingPortNumber, 2333 rocketModel[i].startingPortNumber + 2334 rocketModel[i].numPorts - 1); 2335 2336 return (1); 2337} 2338 2339static const struct tty_operations rocket_ops = { 2340 .open = rp_open, 2341 .close = rp_close, 2342 .write = rp_write, 2343 .put_char = rp_put_char, 2344 .write_room = rp_write_room, 2345 .chars_in_buffer = rp_chars_in_buffer, 2346 .flush_buffer = rp_flush_buffer, 2347 .ioctl = rp_ioctl, 2348 .throttle = rp_throttle, 2349 .unthrottle = rp_unthrottle, 2350 .set_termios = rp_set_termios, 2351 .stop = rp_stop, 2352 .start = rp_start, 2353 .hangup = rp_hangup, 2354 .break_ctl = rp_break, 2355 .send_xchar = rp_send_xchar, 2356 .wait_until_sent = rp_wait_until_sent, 2357 .tiocmget = rp_tiocmget, 2358 .tiocmset = rp_tiocmset, 2359}; 2360 2361/* 2362 * The module "startup" routine; it's run when the module is loaded. 2363 */ 2364static int __init rp_init(void) 2365{ 2366 int retval, pci_boards_found, isa_boards_found, i; 2367 2368 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n", 2369 ROCKET_VERSION, ROCKET_DATE); 2370 2371 rocket_driver = alloc_tty_driver(MAX_RP_PORTS); 2372 if (!rocket_driver) 2373 return -ENOMEM; 2374 2375 /* 2376 * Initialize the array of pointers to our own internal state 2377 * structures. 2378 */ 2379 memset(rp_table, 0, sizeof (rp_table)); 2380 memset(xmit_flags, 0, sizeof (xmit_flags)); 2381 2382 for (i = 0; i < MAX_RP_PORTS; i++) 2383 lineNumbers[i] = 0; 2384 nextLineNumber = 0; 2385 memset(rocketModel, 0, sizeof (rocketModel)); 2386 2387 /* 2388 * If board 1 is non-zero, there is at least one ISA configured. If controller is 2389 * zero, use the default controller IO address of board1 + 0x40. 2390 */ 2391 if (board1) { 2392 if (controller == 0) 2393 controller = board1 + 0x40; 2394 } else { 2395 controller = 0; /* Used as a flag, meaning no ISA boards */ 2396 } 2397 2398 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */ 2399 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) { 2400 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller); 2401 return -EBUSY; 2402 } 2403 2404 /* Store ISA variable retrieved from command line or .conf file. */ 2405 rcktpt_io_addr[0] = board1; 2406 rcktpt_io_addr[1] = board2; 2407 rcktpt_io_addr[2] = board3; 2408 rcktpt_io_addr[3] = board4; 2409 2410 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; 2411 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0]; 2412 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; 2413 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1]; 2414 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; 2415 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2]; 2416 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; 2417 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3]; 2418 2419 /* 2420 * Set up the tty driver structure and then register this 2421 * driver with the tty layer. 2422 */ 2423 2424 rocket_driver->owner = THIS_MODULE; 2425 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV; 2426 rocket_driver->name = "ttyR"; 2427 rocket_driver->driver_name = "Comtrol RocketPort"; 2428 rocket_driver->major = TTY_ROCKET_MAJOR; 2429 rocket_driver->minor_start = 0; 2430 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL; 2431 rocket_driver->subtype = SERIAL_TYPE_NORMAL; 2432 rocket_driver->init_termios = tty_std_termios; 2433 rocket_driver->init_termios.c_cflag = 2434 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 2435 rocket_driver->init_termios.c_ispeed = 9600; 2436 rocket_driver->init_termios.c_ospeed = 9600; 2437#ifdef ROCKET_SOFT_FLOW 2438 rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; 2439#endif 2440 tty_set_operations(rocket_driver, &rocket_ops); 2441 2442 retval = tty_register_driver(rocket_driver); 2443 if (retval < 0) { 2444 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval); 2445 put_tty_driver(rocket_driver); 2446 return -1; 2447 } 2448 2449#ifdef ROCKET_DEBUG_OPEN 2450 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major); 2451#endif 2452 2453 /* 2454 * OK, let's probe each of the controllers looking for boards. Any boards found 2455 * will be initialized here. 2456 */ 2457 isa_boards_found = 0; 2458 pci_boards_found = 0; 2459 2460 for (i = 0; i < NUM_BOARDS; i++) { 2461 if (init_ISA(i)) 2462 isa_boards_found++; 2463 } 2464 2465#ifdef CONFIG_PCI 2466 if (isa_boards_found < NUM_BOARDS) 2467 pci_boards_found = init_PCI(isa_boards_found); 2468#endif 2469 2470 max_board = pci_boards_found + isa_boards_found; 2471 2472 if (max_board == 0) { 2473 printk(KERN_INFO "No rocketport ports found; unloading driver.\n"); 2474 del_timer_sync(&rocket_timer); 2475 tty_unregister_driver(rocket_driver); 2476 put_tty_driver(rocket_driver); 2477 return -ENXIO; 2478 } 2479 2480 return 0; 2481} 2482 2483 2484static void rp_cleanup_module(void) 2485{ 2486 int retval; 2487 int i; 2488 2489 del_timer_sync(&rocket_timer); 2490 2491 retval = tty_unregister_driver(rocket_driver); 2492 if (retval) 2493 printk(KERN_INFO "Error %d while trying to unregister " 2494 "rocketport driver\n", -retval); 2495 put_tty_driver(rocket_driver); 2496 2497 for (i = 0; i < MAX_RP_PORTS; i++) 2498 kfree(rp_table[i]); 2499 2500 for (i = 0; i < NUM_BOARDS; i++) { 2501 if (rcktpt_io_addr[i] <= 0 || is_PCI[i]) 2502 continue; 2503 release_region(rcktpt_io_addr[i], 64); 2504 } 2505 if (controller) 2506 release_region(controller, 4); 2507} 2508 2509/*************************************************************************** 2510Function: sInitController 2511Purpose: Initialization of controller global registers and controller 2512 structure. 2513Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize, 2514 IRQNum,Frequency,PeriodicOnly) 2515 CONTROLLER_T *CtlP; Ptr to controller structure 2516 int CtlNum; Controller number 2517 ByteIO_t MudbacIO; Mudbac base I/O address. 2518 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP. 2519 This list must be in the order the AIOPs will be found on the 2520 controller. Once an AIOP in the list is not found, it is 2521 assumed that there are no more AIOPs on the controller. 2522 int AiopIOListSize; Number of addresses in AiopIOList 2523 int IRQNum; Interrupt Request number. Can be any of the following: 2524 0: Disable global interrupts 2525 3: IRQ 3 2526 4: IRQ 4 2527 5: IRQ 5 2528 9: IRQ 9 2529 10: IRQ 10 2530 11: IRQ 11 2531 12: IRQ 12 2532 15: IRQ 15 2533 Byte_t Frequency: A flag identifying the frequency 2534 of the periodic interrupt, can be any one of the following: 2535 FREQ_DIS - periodic interrupt disabled 2536 FREQ_137HZ - 137 Hertz 2537 FREQ_69HZ - 69 Hertz 2538 FREQ_34HZ - 34 Hertz 2539 FREQ_17HZ - 17 Hertz 2540 FREQ_9HZ - 9 Hertz 2541 FREQ_4HZ - 4 Hertz 2542 If IRQNum is set to 0 the Frequency parameter is 2543 overidden, it is forced to a value of FREQ_DIS. 2544 int PeriodicOnly: 1 if all interrupts except the periodic 2545 interrupt are to be blocked. 2546 0 is both the periodic interrupt and 2547 other channel interrupts are allowed. 2548 If IRQNum is set to 0 the PeriodicOnly parameter is 2549 overidden, it is forced to a value of 0. 2550Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller 2551 initialization failed. 2552 2553Comments: 2554 If periodic interrupts are to be disabled but AIOP interrupts 2555 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0. 2556 2557 If interrupts are to be completely disabled set IRQNum to 0. 2558 2559 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an 2560 invalid combination. 2561 2562 This function performs initialization of global interrupt modes, 2563 but it does not actually enable global interrupts. To enable 2564 and disable global interrupts use functions sEnGlobalInt() and 2565 sDisGlobalInt(). Enabling of global interrupts is normally not 2566 done until all other initializations are complete. 2567 2568 Even if interrupts are globally enabled, they must also be 2569 individually enabled for each channel that is to generate 2570 interrupts. 2571 2572Warnings: No range checking on any of the parameters is done. 2573 2574 No context switches are allowed while executing this function. 2575 2576 After this function all AIOPs on the controller are disabled, 2577 they can be enabled with sEnAiop(). 2578*/ 2579static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO, 2580 ByteIO_t * AiopIOList, int AiopIOListSize, 2581 int IRQNum, Byte_t Frequency, int PeriodicOnly) 2582{ 2583 int i; 2584 ByteIO_t io; 2585 int done; 2586 2587 CtlP->AiopIntrBits = aiop_intr_bits; 2588 CtlP->AltChanRingIndicator = 0; 2589 CtlP->CtlNum = CtlNum; 2590 CtlP->CtlID = CTLID_0001; /* controller release 1 */ 2591 CtlP->BusType = isISA; 2592 CtlP->MBaseIO = MudbacIO; 2593 CtlP->MReg1IO = MudbacIO + 1; 2594 CtlP->MReg2IO = MudbacIO + 2; 2595 CtlP->MReg3IO = MudbacIO + 3; 2596 CtlP->MReg2 = 0; /* interrupt disable */ 2597 CtlP->MReg3 = 0; /* no periodic interrupts */ 2598 sOutB(CtlP->MReg2IO, CtlP->MReg2); 2599 sOutB(CtlP->MReg3IO, CtlP->MReg3); 2600 sControllerEOI(CtlP); /* clear EOI if warm init */ 2601 /* Init AIOPs */ 2602 CtlP->NumAiop = 0; 2603 for (i = done = 0; i < AiopIOListSize; i++) { 2604 io = AiopIOList[i]; 2605 CtlP->AiopIO[i] = (WordIO_t) io; 2606 CtlP->AiopIntChanIO[i] = io + _INT_CHAN; 2607 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */ 2608 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */ 2609 if (done) 2610 continue; 2611 sEnAiop(CtlP, i); /* enable the AIOP */ 2612 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */ 2613 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */ 2614 done = 1; /* done looking for AIOPs */ 2615 else { 2616 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */ 2617 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ 2618 sOutB(io + _INDX_DATA, sClockPrescale); 2619 CtlP->NumAiop++; /* bump count of AIOPs */ 2620 } 2621 sDisAiop(CtlP, i); /* disable AIOP */ 2622 } 2623 2624 if (CtlP->NumAiop == 0) 2625 return (-1); 2626 else 2627 return (CtlP->NumAiop); 2628} 2629 2630/*************************************************************************** 2631Function: sPCIInitController 2632Purpose: Initialization of controller global registers and controller 2633 structure. 2634Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize, 2635 IRQNum,Frequency,PeriodicOnly) 2636 CONTROLLER_T *CtlP; Ptr to controller structure 2637 int CtlNum; Controller number 2638 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP. 2639 This list must be in the order the AIOPs will be found on the 2640 controller. Once an AIOP in the list is not found, it is 2641 assumed that there are no more AIOPs on the controller. 2642 int AiopIOListSize; Number of addresses in AiopIOList 2643 int IRQNum; Interrupt Request number. Can be any of the following: 2644 0: Disable global interrupts 2645 3: IRQ 3 2646 4: IRQ 4 2647 5: IRQ 5 2648 9: IRQ 9 2649 10: IRQ 10 2650 11: IRQ 11 2651 12: IRQ 12 2652 15: IRQ 15 2653 Byte_t Frequency: A flag identifying the frequency 2654 of the periodic interrupt, can be any one of the following: 2655 FREQ_DIS - periodic interrupt disabled 2656 FREQ_137HZ - 137 Hertz 2657 FREQ_69HZ - 69 Hertz 2658 FREQ_34HZ - 34 Hertz 2659 FREQ_17HZ - 17 Hertz 2660 FREQ_9HZ - 9 Hertz 2661 FREQ_4HZ - 4 Hertz 2662 If IRQNum is set to 0 the Frequency parameter is 2663 overidden, it is forced to a value of FREQ_DIS. 2664 int PeriodicOnly: 1 if all interrupts except the periodic 2665 interrupt are to be blocked. 2666 0 is both the periodic interrupt and 2667 other channel interrupts are allowed. 2668 If IRQNum is set to 0 the PeriodicOnly parameter is 2669 overidden, it is forced to a value of 0. 2670Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller 2671 initialization failed. 2672 2673Comments: 2674 If periodic interrupts are to be disabled but AIOP interrupts 2675 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0. 2676 2677 If interrupts are to be completely disabled set IRQNum to 0. 2678 2679 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an 2680 invalid combination. 2681 2682 This function performs initialization of global interrupt modes, 2683 but it does not actually enable global interrupts. To enable 2684 and disable global interrupts use functions sEnGlobalInt() and 2685 sDisGlobalInt(). Enabling of global interrupts is normally not 2686 done until all other initializations are complete. 2687 2688 Even if interrupts are globally enabled, they must also be 2689 individually enabled for each channel that is to generate 2690 interrupts. 2691 2692Warnings: No range checking on any of the parameters is done. 2693 2694 No context switches are allowed while executing this function. 2695 2696 After this function all AIOPs on the controller are disabled, 2697 they can be enabled with sEnAiop(). 2698*/ 2699static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum, 2700 ByteIO_t * AiopIOList, int AiopIOListSize, 2701 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency, 2702 int PeriodicOnly, int altChanRingIndicator, 2703 int UPCIRingInd) 2704{ 2705 int i; 2706 ByteIO_t io; 2707 2708 CtlP->AltChanRingIndicator = altChanRingIndicator; 2709 CtlP->UPCIRingInd = UPCIRingInd; 2710 CtlP->CtlNum = CtlNum; 2711 CtlP->CtlID = CTLID_0001; /* controller release 1 */ 2712 CtlP->BusType = isPCI; /* controller release 1 */ 2713 2714 if (ConfigIO) { 2715 CtlP->isUPCI = 1; 2716 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL; 2717 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL; 2718 CtlP->AiopIntrBits = upci_aiop_intr_bits; 2719 } else { 2720 CtlP->isUPCI = 0; 2721 CtlP->PCIIO = 2722 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC); 2723 CtlP->AiopIntrBits = aiop_intr_bits; 2724 } 2725 2726 sPCIControllerEOI(CtlP); /* clear EOI if warm init */ 2727 /* Init AIOPs */ 2728 CtlP->NumAiop = 0; 2729 for (i = 0; i < AiopIOListSize; i++) { 2730 io = AiopIOList[i]; 2731 CtlP->AiopIO[i] = (WordIO_t) io; 2732 CtlP->AiopIntChanIO[i] = io + _INT_CHAN; 2733 2734 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */ 2735 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */ 2736 break; /* done looking for AIOPs */ 2737 2738 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */ 2739 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ 2740 sOutB(io + _INDX_DATA, sClockPrescale); 2741 CtlP->NumAiop++; /* bump count of AIOPs */ 2742 } 2743 2744 if (CtlP->NumAiop == 0) 2745 return (-1); 2746 else 2747 return (CtlP->NumAiop); 2748} 2749 2750/*************************************************************************** 2751Function: sReadAiopID 2752Purpose: Read the AIOP idenfication number directly from an AIOP. 2753Call: sReadAiopID(io) 2754 ByteIO_t io: AIOP base I/O address 2755Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X 2756 is replace by an identifying number. 2757 Flag AIOPID_NULL if no valid AIOP is found 2758Warnings: No context switches are allowed while executing this function. 2759 2760*/ 2761static int sReadAiopID(ByteIO_t io) 2762{ 2763 Byte_t AiopID; /* ID byte from AIOP */ 2764 2765 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */ 2766 sOutB(io + _CMD_REG, 0x0); 2767 AiopID = sInW(io + _CHN_STAT0) & 0x07; 2768 if (AiopID == 0x06) 2769 return (1); 2770 else /* AIOP does not exist */ 2771 return (-1); 2772} 2773 2774/*************************************************************************** 2775Function: sReadAiopNumChan 2776Purpose: Read the number of channels available in an AIOP directly from 2777 an AIOP. 2778Call: sReadAiopNumChan(io) 2779 WordIO_t io: AIOP base I/O address 2780Return: int: The number of channels available 2781Comments: The number of channels is determined by write/reads from identical 2782 offsets within the SRAM address spaces for channels 0 and 4. 2783 If the channel 4 space is mirrored to channel 0 it is a 4 channel 2784 AIOP, otherwise it is an 8 channel. 2785Warnings: No context switches are allowed while executing this function. 2786*/ 2787static int sReadAiopNumChan(WordIO_t io) 2788{ 2789 Word_t x; 2790 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; 2791 2792 /* write to chan 0 SRAM */ 2793 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0])); 2794 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ 2795 x = sInW(io + _INDX_DATA); 2796 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ 2797 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */ 2798 return (8); 2799 else 2800 return (4); 2801} 2802 2803/*************************************************************************** 2804Function: sInitChan 2805Purpose: Initialization of a channel and channel structure 2806Call: sInitChan(CtlP,ChP,AiopNum,ChanNum) 2807 CONTROLLER_T *CtlP; Ptr to controller structure 2808 CHANNEL_T *ChP; Ptr to channel structure 2809 int AiopNum; AIOP number within controller 2810 int ChanNum; Channel number within AIOP 2811Return: int: 1 if initialization succeeded, 0 if it fails because channel 2812 number exceeds number of channels available in AIOP. 2813Comments: This function must be called before a channel can be used. 2814Warnings: No range checking on any of the parameters is done. 2815 2816 No context switches are allowed while executing this function. 2817*/ 2818static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, 2819 int ChanNum) 2820{ 2821 int i; 2822 WordIO_t AiopIO; 2823 WordIO_t ChIOOff; 2824 Byte_t *ChR; 2825 Word_t ChOff; 2826 static Byte_t R[4]; 2827 int brd9600; 2828 2829 if (ChanNum >= CtlP->AiopNumChan[AiopNum]) 2830 return 0; /* exceeds num chans in AIOP */ 2831 2832 /* Channel, AIOP, and controller identifiers */ 2833 ChP->CtlP = CtlP; 2834 ChP->ChanID = CtlP->AiopID[AiopNum]; 2835 ChP->AiopNum = AiopNum; 2836 ChP->ChanNum = ChanNum; 2837 2838 /* Global direct addresses */ 2839 AiopIO = CtlP->AiopIO[AiopNum]; 2840 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG; 2841 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN; 2842 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK; 2843 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR; 2844 ChP->IndexData = AiopIO + _INDX_DATA; 2845 2846 /* Channel direct addresses */ 2847 ChIOOff = AiopIO + ChP->ChanNum * 2; 2848 ChP->TxRxData = ChIOOff + _TD0; 2849 ChP->ChanStat = ChIOOff + _CHN_STAT0; 2850 ChP->TxRxCount = ChIOOff + _FIFO_CNT0; 2851 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0; 2852 2853 /* Initialize the channel from the RData array */ 2854 for (i = 0; i < RDATASIZE; i += 4) { 2855 R[0] = RData[i]; 2856 R[1] = RData[i + 1] + 0x10 * ChanNum; 2857 R[2] = RData[i + 2]; 2858 R[3] = RData[i + 3]; 2859 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0])); 2860 } 2861 2862 ChR = ChP->R; 2863 for (i = 0; i < RREGDATASIZE; i += 4) { 2864 ChR[i] = RRegData[i]; 2865 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum; 2866 ChR[i + 2] = RRegData[i + 2]; 2867 ChR[i + 3] = RRegData[i + 3]; 2868 } 2869 2870 /* Indexed registers */ 2871 ChOff = (Word_t) ChanNum *0x1000; 2872 2873 if (sClockPrescale == 0x14) 2874 brd9600 = 47; 2875 else 2876 brd9600 = 23; 2877 2878 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD); 2879 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8); 2880 ChP->BaudDiv[2] = (Byte_t) brd9600; 2881 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8); 2882 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]); 2883 2884 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL); 2885 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8); 2886 ChP->TxControl[2] = 0; 2887 ChP->TxControl[3] = 0; 2888 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 2889 2890 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL); 2891 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8); 2892 ChP->RxControl[2] = 0; 2893 ChP->RxControl[3] = 0; 2894 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 2895 2896 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS); 2897 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8); 2898 ChP->TxEnables[2] = 0; 2899 ChP->TxEnables[3] = 0; 2900 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]); 2901 2902 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1); 2903 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8); 2904 ChP->TxCompare[2] = 0; 2905 ChP->TxCompare[3] = 0; 2906 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]); 2907 2908 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1); 2909 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8); 2910 ChP->TxReplace1[2] = 0; 2911 ChP->TxReplace1[3] = 0; 2912 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]); 2913 2914 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2); 2915 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8); 2916 ChP->TxReplace2[2] = 0; 2917 ChP->TxReplace2[3] = 0; 2918 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]); 2919 2920 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP; 2921 ChP->TxFIFO = ChOff + _TX_FIFO; 2922 2923 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */ 2924 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */ 2925 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ 2926 sOutW(ChP->IndexData, 0); 2927 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP; 2928 ChP->RxFIFO = ChOff + _RX_FIFO; 2929 2930 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */ 2931 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */ 2932 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ 2933 sOutW(ChP->IndexData, 0); 2934 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ 2935 sOutW(ChP->IndexData, 0); 2936 ChP->TxPrioCnt = ChOff + _TXP_CNT; 2937 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt); 2938 sOutB(ChP->IndexData, 0); 2939 ChP->TxPrioPtr = ChOff + _TXP_PNTR; 2940 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr); 2941 sOutB(ChP->IndexData, 0); 2942 ChP->TxPrioBuf = ChOff + _TXP_BUF; 2943 sEnRxProcessor(ChP); /* start the Rx processor */ 2944 2945 return 1; 2946} 2947 2948/*************************************************************************** 2949Function: sStopRxProcessor 2950Purpose: Stop the receive processor from processing a channel. 2951Call: sStopRxProcessor(ChP) 2952 CHANNEL_T *ChP; Ptr to channel structure 2953 2954Comments: The receive processor can be started again with sStartRxProcessor(). 2955 This function causes the receive processor to skip over the 2956 stopped channel. It does not stop it from processing other channels. 2957 2958Warnings: No context switches are allowed while executing this function. 2959 2960 Do not leave the receive processor stopped for more than one 2961 character time. 2962 2963 After calling this function a delay of 4 uS is required to ensure 2964 that the receive processor is no longer processing this channel. 2965*/ 2966static void sStopRxProcessor(CHANNEL_T * ChP) 2967{ 2968 Byte_t R[4]; 2969 2970 R[0] = ChP->R[0]; 2971 R[1] = ChP->R[1]; 2972 R[2] = 0x0a; 2973 R[3] = ChP->R[3]; 2974 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]); 2975} 2976 2977/*************************************************************************** 2978Function: sFlushRxFIFO 2979Purpose: Flush the Rx FIFO 2980Call: sFlushRxFIFO(ChP) 2981 CHANNEL_T *ChP; Ptr to channel structure 2982Return: void 2983Comments: To prevent data from being enqueued or dequeued in the Tx FIFO 2984 while it is being flushed the receive processor is stopped 2985 and the transmitter is disabled. After these operations a 2986 4 uS delay is done before clearing the pointers to allow 2987 the receive processor to stop. These items are handled inside 2988 this function. 2989Warnings: No context switches are allowed while executing this function. 2990*/ 2991static void sFlushRxFIFO(CHANNEL_T * ChP) 2992{ 2993 int i; 2994 Byte_t Ch; /* channel number within AIOP */ 2995 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */ 2996 2997 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */ 2998 return; /* don't need to flush */ 2999 3000 RxFIFOEnabled = 0; 3001 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */ 3002 RxFIFOEnabled = 1; 3003 sDisRxFIFO(ChP); /* disable it */ 3004 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */ 3005 sInB(ChP->IntChan); /* depends on bus i/o timing */ 3006 } 3007 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */ 3008 Ch = (Byte_t) sGetChanNum(ChP); 3009 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */ 3010 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */ 3011 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ 3012 sOutW(ChP->IndexData, 0); 3013 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ 3014 sOutW(ChP->IndexData, 0); 3015 if (RxFIFOEnabled) 3016 sEnRxFIFO(ChP); /* enable Rx FIFO */ 3017} 3018 3019/*************************************************************************** 3020Function: sFlushTxFIFO 3021Purpose: Flush the Tx FIFO 3022Call: sFlushTxFIFO(ChP) 3023 CHANNEL_T *ChP; Ptr to channel structure 3024Return: void 3025Comments: To prevent data from being enqueued or dequeued in the Tx FIFO 3026 while it is being flushed the receive processor is stopped 3027 and the transmitter is disabled. After these operations a 3028 4 uS delay is done before clearing the pointers to allow 3029 the receive processor to stop. These items are handled inside 3030 this function. 3031Warnings: No context switches are allowed while executing this function. 3032*/ 3033static void sFlushTxFIFO(CHANNEL_T * ChP) 3034{ 3035 int i; 3036 Byte_t Ch; /* channel number within AIOP */ 3037 int TxEnabled; /* 1 if transmitter enabled */ 3038 3039 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */ 3040 return; /* don't need to flush */ 3041 3042 TxEnabled = 0; 3043 if (ChP->TxControl[3] & TX_ENABLE) { 3044 TxEnabled = 1; 3045 sDisTransmit(ChP); /* disable transmitter */ 3046 } 3047 sStopRxProcessor(ChP); /* stop Rx processor */ 3048 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */ 3049 sInB(ChP->IntChan); /* depends on bus i/o timing */ 3050 Ch = (Byte_t) sGetChanNum(ChP); 3051 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */ 3052 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */ 3053 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ 3054 sOutW(ChP->IndexData, 0); 3055 if (TxEnabled) 3056 sEnTransmit(ChP); /* enable transmitter */ 3057 sStartRxProcessor(ChP); /* restart Rx processor */ 3058} 3059 3060/*************************************************************************** 3061Function: sWriteTxPrioByte 3062Purpose: Write a byte of priority transmit data to a channel 3063Call: sWriteTxPrioByte(ChP,Data) 3064 CHANNEL_T *ChP; Ptr to channel structure 3065 Byte_t Data; The transmit data byte 3066 3067Return: int: 1 if the bytes is successfully written, otherwise 0. 3068 3069Comments: The priority byte is transmitted before any data in the Tx FIFO. 3070 3071Warnings: No context switches are allowed while executing this function. 3072*/ 3073static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data) 3074{ 3075 Byte_t DWBuf[4]; /* buffer for double word writes */ 3076 Word_t *WordPtr; /* must be far because Win SS != DS */ 3077 register DWordIO_t IndexAddr; 3078 3079 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */ 3080 IndexAddr = ChP->IndexAddr; 3081 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */ 3082 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */ 3083 return (0); /* nothing sent */ 3084 3085 WordPtr = (Word_t *) (&DWBuf[0]); 3086 *WordPtr = ChP->TxPrioBuf; /* data byte address */ 3087 3088 DWBuf[2] = Data; /* data byte value */ 3089 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ 3090 3091 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */ 3092 3093 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */ 3094 DWBuf[3] = 0; /* priority buffer pointer */ 3095 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ 3096 } else { /* write it to Tx FIFO */ 3097 3098 sWriteTxByte(sGetTxRxDataIO(ChP), Data); 3099 } 3100 return (1); /* 1 byte sent */ 3101} 3102 3103/*************************************************************************** 3104Function: sEnInterrupts 3105Purpose: Enable one or more interrupts for a channel 3106Call: sEnInterrupts(ChP,Flags) 3107 CHANNEL_T *ChP; Ptr to channel structure 3108 Word_t Flags: Interrupt enable flags, can be any combination 3109 of the following flags: 3110 TXINT_EN: Interrupt on Tx FIFO empty 3111 RXINT_EN: Interrupt on Rx FIFO at trigger level (see 3112 sSetRxTrigger()) 3113 SRCINT_EN: Interrupt on SRC (Special Rx Condition) 3114 MCINT_EN: Interrupt on modem input change 3115 CHANINT_EN: Allow channel interrupt signal to the AIOP's 3116 Interrupt Channel Register. 3117Return: void 3118Comments: If an interrupt enable flag is set in Flags, that interrupt will be 3119 enabled. If an interrupt enable flag is not set in Flags, that 3120 interrupt will not be changed. Interrupts can be disabled with 3121 function sDisInterrupts(). 3122 3123 This function sets the appropriate bit for the channel in the AIOP's 3124 Interrupt Mask Register if the CHANINT_EN flag is set. This allows 3125 this channel's bit to be set in the AIOP's Interrupt Channel Register. 3126 3127 Interrupts must also be globally enabled before channel interrupts 3128 will be passed on to the host. This is done with function 3129 sEnGlobalInt(). 3130 3131 In some cases it may be desirable to disable interrupts globally but 3132 enable channel interrupts. This would allow the global interrupt 3133 status register to be used to determine which AIOPs need service. 3134*/ 3135static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags) 3136{ 3137 Byte_t Mask; /* Interrupt Mask Register */ 3138 3139 ChP->RxControl[2] |= 3140 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); 3141 3142 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 3143 3144 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN); 3145 3146 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 3147 3148 if (Flags & CHANINT_EN) { 3149 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum]; 3150 sOutB(ChP->IntMask, Mask); 3151 } 3152} 3153 3154/*************************************************************************** 3155Function: sDisInterrupts 3156Purpose: Disable one or more interrupts for a channel 3157Call: sDisInterrupts(ChP,Flags) 3158 CHANNEL_T *ChP; Ptr to channel structure 3159 Word_t Flags: Interrupt flags, can be any combination 3160 of the following flags: 3161 TXINT_EN: Interrupt on Tx FIFO empty 3162 RXINT_EN: Interrupt on Rx FIFO at trigger level (see 3163 sSetRxTrigger()) 3164 SRCINT_EN: Interrupt on SRC (Special Rx Condition) 3165 MCINT_EN: Interrupt on modem input change 3166 CHANINT_EN: Disable channel interrupt signal to the 3167 AIOP's Interrupt Channel Register. 3168Return: void 3169Comments: If an interrupt flag is set in Flags, that interrupt will be 3170 disabled. If an interrupt flag is not set in Flags, that 3171 interrupt will not be changed. Interrupts can be enabled with 3172 function sEnInterrupts(). 3173 3174 This function clears the appropriate bit for the channel in the AIOP's 3175 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks 3176 this channel's bit from being set in the AIOP's Interrupt Channel 3177 Register. 3178*/ 3179static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags) 3180{ 3181 Byte_t Mask; /* Interrupt Mask Register */ 3182 3183 ChP->RxControl[2] &= 3184 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); 3185 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 3186 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN); 3187 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 3188 3189 if (Flags & CHANINT_EN) { 3190 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum]; 3191 sOutB(ChP->IntMask, Mask); 3192 } 3193} 3194 3195static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode) 3196{ 3197 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum); 3198} 3199 3200/* 3201 * Not an official SSCI function, but how to reset RocketModems. 3202 * ISA bus version 3203 */ 3204static void sModemReset(CONTROLLER_T * CtlP, int chan, int on) 3205{ 3206 ByteIO_t addr; 3207 Byte_t val; 3208 3209 addr = CtlP->AiopIO[0] + 0x400; 3210 val = sInB(CtlP->MReg3IO); 3211 /* if AIOP[1] is not enabled, enable it */ 3212 if ((val & 2) == 0) { 3213 val = sInB(CtlP->MReg2IO); 3214 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03)); 3215 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6)); 3216 } 3217 3218 sEnAiop(CtlP, 1); 3219 if (!on) 3220 addr += 8; 3221 sOutB(addr + chan, 0); /* apply or remove reset */ 3222 sDisAiop(CtlP, 1); 3223} 3224 3225/* 3226 * Not an official SSCI function, but how to reset RocketModems. 3227 * PCI bus version 3228 */ 3229static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on) 3230{ 3231 ByteIO_t addr; 3232 3233 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */ 3234 if (!on) 3235 addr += 8; 3236 sOutB(addr + chan, 0); /* apply or remove reset */ 3237} 3238 3239/* Resets the speaker controller on RocketModem II and III devices */ 3240static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model) 3241{ 3242 ByteIO_t addr; 3243 3244 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */ 3245 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) { 3246 addr = CtlP->AiopIO[0] + 0x4F; 3247 sOutB(addr, 0); 3248 } 3249 3250 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */ 3251 if ((model == MODEL_UPCI_RM3_8PORT) 3252 || (model == MODEL_UPCI_RM3_4PORT)) { 3253 addr = CtlP->AiopIO[0] + 0x88; 3254 sOutB(addr, 0); 3255 } 3256} 3257 3258/* Returns the line number given the controller (board), aiop and channel number */ 3259static unsigned char GetLineNumber(int ctrl, int aiop, int ch) 3260{ 3261 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch]; 3262} 3263 3264/* 3265 * Stores the line number associated with a given controller (board), aiop 3266 * and channel number. 3267 * Returns: The line number assigned 3268 */ 3269static unsigned char SetLineNumber(int ctrl, int aiop, int ch) 3270{ 3271 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++; 3272 return (nextLineNumber - 1); 3273} 3274