1/******************************************************************************* 2* 3* (c) 1998 by Computone Corporation 4* 5******************************************************************************** 6* 7* 8* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport 9* serial I/O controllers. 10* 11* DESCRIPTION: Low-level interface code for the device driver 12* (This is included source code, not a separate compilation 13* module.) 14* 15*******************************************************************************/ 16//--------------------------------------------- 17// Function declarations private to this module 18//--------------------------------------------- 19// Functions called only indirectly through i2eBordStr entries. 20 21static int iiWriteBuf16(i2eBordStrPtr, unsigned char *, int); 22static int iiWriteBuf8(i2eBordStrPtr, unsigned char *, int); 23static int iiReadBuf16(i2eBordStrPtr, unsigned char *, int); 24static int iiReadBuf8(i2eBordStrPtr, unsigned char *, int); 25 26static unsigned short iiReadWord16(i2eBordStrPtr); 27static unsigned short iiReadWord8(i2eBordStrPtr); 28static void iiWriteWord16(i2eBordStrPtr, unsigned short); 29static void iiWriteWord8(i2eBordStrPtr, unsigned short); 30 31static int iiWaitForTxEmptyII(i2eBordStrPtr, int); 32static int iiWaitForTxEmptyIIEX(i2eBordStrPtr, int); 33static int iiTxMailEmptyII(i2eBordStrPtr); 34static int iiTxMailEmptyIIEX(i2eBordStrPtr); 35static int iiTrySendMailII(i2eBordStrPtr, unsigned char); 36static int iiTrySendMailIIEX(i2eBordStrPtr, unsigned char); 37 38static unsigned short iiGetMailII(i2eBordStrPtr); 39static unsigned short iiGetMailIIEX(i2eBordStrPtr); 40 41static void iiEnableMailIrqII(i2eBordStrPtr); 42static void iiEnableMailIrqIIEX(i2eBordStrPtr); 43static void iiWriteMaskII(i2eBordStrPtr, unsigned char); 44static void iiWriteMaskIIEX(i2eBordStrPtr, unsigned char); 45 46static void ii2DelayTimer(unsigned int); 47static void ii2DelayWakeup(unsigned long id); 48static void ii2Nop(void); 49 50//*************** 51//* Static Data * 52//*************** 53 54static int ii2Safe; // Safe I/O address for delay routine 55 56static int iiDelayed; // Set when the iiResetDelay function is 57 // called. Cleared when ANY board is reset. 58static struct timer_list * pDelayTimer; // Used by iiDelayTimer 59static wait_queue_head_t pDelayWait; // Used by iiDelayTimer 60static rwlock_t Dl_spinlock; 61 62//******** 63//* Code * 64//******** 65 66//======================================================= 67// Initialization Routines 68// 69// iiSetAddress 70// iiReset 71// iiResetDelay 72// iiInitialize 73//======================================================= 74 75//****************************************************************************** 76// Function: iiEllisInit() 77// Parameters: None 78// 79// Returns: Nothing 80// 81// Description: 82// 83// This routine performs any required initialization of the iiEllis subsystem. 84// 85//****************************************************************************** 86static void 87iiEllisInit(void) 88{ 89 pDelayTimer = kmalloc ( sizeof (struct timer_list), GFP_KERNEL ); 90 init_timer(pDelayTimer); 91 init_waitqueue_head(&pDelayWait); 92 LOCK_INIT(&Dl_spinlock); 93} 94 95//****************************************************************************** 96// Function: iiEllisCleanup() 97// Parameters: None 98// 99// Returns: Nothing 100// 101// Description: 102// 103// This routine performs any required cleanup of the iiEllis subsystem. 104// 105//****************************************************************************** 106static void 107iiEllisCleanup(void) 108{ 109 kfree(pDelayTimer); 110} 111 112//****************************************************************************** 113// Function: iiSetAddress(pB, address, delay) 114// Parameters: pB - pointer to the board structure 115// address - the purported I/O address of the board 116// delay - pointer to the 1-ms delay function to use 117// in this and any future operations to this board 118// 119// Returns: True if everything appears copacetic. 120// False if there is any error: the pB->i2eError field has the error 121// 122// Description: 123// 124// This routine (roughly) checks for address validity, sets the i2eValid OK and 125// sets the state to II_STATE_COLD which means that we haven't even sent a reset 126// yet. 127// 128//****************************************************************************** 129static int 130iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay ) 131{ 132 // Should any failure occur before init is finished... 133 pB->i2eValid = I2E_INCOMPLETE; 134 135 // Cannot check upper limit except extremely: Might be microchannel 136 // Address must be on an 8-byte boundary 137 138 if ((unsigned int)address <= 0x100 139 || (unsigned int)address >= 0xfff8 140 || (address & 0x7) 141 ) 142 { 143 COMPLETE(pB,I2EE_BADADDR); 144 } 145 146 // Initialize accelerators 147 pB->i2eBase = address; 148 pB->i2eData = address + FIFO_DATA; 149 pB->i2eStatus = address + FIFO_STATUS; 150 pB->i2ePointer = address + FIFO_PTR; 151 pB->i2eXMail = address + FIFO_MAIL; 152 pB->i2eXMask = address + FIFO_MASK; 153 154 // Initialize i/o address for ii2DelayIO 155 ii2Safe = address + FIFO_NOP; 156 157 // Initialize the delay routine 158 pB->i2eDelay = ((delay != (delayFunc_t)NULL) ? delay : (delayFunc_t)ii2Nop); 159 160 pB->i2eValid = I2E_MAGIC; 161 pB->i2eState = II_STATE_COLD; 162 163 COMPLETE(pB, I2EE_GOOD); 164} 165 166//****************************************************************************** 167// Function: iiReset(pB) 168// Parameters: pB - pointer to the board structure 169// 170// Returns: True if everything appears copacetic. 171// False if there is any error: the pB->i2eError field has the error 172// 173// Description: 174// 175// Attempts to reset the board (see also i2hw.h). Normally, we would use this to 176// reset a board immediately after iiSetAddress(), but it is valid to reset a 177// board from any state, say, in order to change or re-load loadware. (Under 178// such circumstances, no reason to re-run iiSetAddress(), which is why it is a 179// separate routine and not included in this routine. 180// 181//****************************************************************************** 182static int 183iiReset(i2eBordStrPtr pB) 184{ 185 // Magic number should be set, else even the address is suspect 186 if (pB->i2eValid != I2E_MAGIC) 187 { 188 COMPLETE(pB, I2EE_BADMAGIC); 189 } 190 191 OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do 192 iiDelay(pB, 50); // Pause between resets 193 OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset 194 195 // We must wait before even attempting to read anything from the FIFO: the 196 // board's P.O.S.T may actually attempt to read and write its end of the 197 // FIFO in order to check flags, loop back (where supported), etc. On 198 // completion of this testing it would reset the FIFO, and on completion 199 // of all // P.O.S.T., write the message. We must not mistake data which 200 // might have been sent for testing as part of the reset message. To 201 // better utilize time, say, when resetting several boards, we allow the 202 // delay to be performed externally; in this way the caller can reset 203 // several boards, delay a single time, then call the initialization 204 // routine for all. 205 206 pB->i2eState = II_STATE_RESET; 207 208 iiDelayed = 0; // i.e., the delay routine hasn't been called since the most 209 // recent reset. 210 211 // Ensure anything which would have been of use to standard loadware is 212 // blanked out, since board has now forgotten everything!. 213 214 pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet 215 pB->i2eWaitingForEmptyFifo = 0; 216 pB->i2eOutMailWaiting = 0; 217 pB->i2eChannelPtr = NULL; 218 pB->i2eChannelCnt = 0; 219 220 pB->i2eLeadoffWord[0] = 0; 221 pB->i2eFifoInInts = 0; 222 pB->i2eFifoOutInts = 0; 223 pB->i2eFatalTrap = NULL; 224 pB->i2eFatal = 0; 225 226 COMPLETE(pB, I2EE_GOOD); 227} 228 229//****************************************************************************** 230// Function: iiResetDelay(pB) 231// Parameters: pB - pointer to the board structure 232// 233// Returns: True if everything appears copacetic. 234// False if there is any error: the pB->i2eError field has the error 235// 236// Description: 237// 238// Using the delay defined in board structure, waits two seconds (for board to 239// reset). 240// 241//****************************************************************************** 242static int 243iiResetDelay(i2eBordStrPtr pB) 244{ 245 if (pB->i2eValid != I2E_MAGIC) { 246 COMPLETE(pB, I2EE_BADMAGIC); 247 } 248 if (pB->i2eState != II_STATE_RESET) { 249 COMPLETE(pB, I2EE_BADSTATE); 250 } 251 iiDelay(pB,2000); /* Now we wait for two seconds. */ 252 iiDelayed = 1; /* Delay has been called: ok to initialize */ 253 COMPLETE(pB, I2EE_GOOD); 254} 255 256//****************************************************************************** 257// Function: iiInitialize(pB) 258// Parameters: pB - pointer to the board structure 259// 260// Returns: True if everything appears copacetic. 261// False if there is any error: the pB->i2eError field has the error 262// 263// Description: 264// 265// Attempts to read the Power-on reset message. Initializes any remaining fields 266// in the pB structure. 267// 268// This should be called as the third step of a process beginning with 269// iiReset(), then iiResetDelay(). This routine checks to see that the structure 270// is "valid" and in the reset state, also confirms that the delay routine has 271// been called since the latest reset (to any board! overly strong!). 272// 273//****************************************************************************** 274static int 275iiInitialize(i2eBordStrPtr pB) 276{ 277 int itemp; 278 unsigned char c; 279 unsigned short utemp; 280 unsigned int ilimit; 281 282 if (pB->i2eValid != I2E_MAGIC) 283 { 284 COMPLETE(pB, I2EE_BADMAGIC); 285 } 286 287 if (pB->i2eState != II_STATE_RESET || !iiDelayed) 288 { 289 COMPLETE(pB, I2EE_BADSTATE); 290 } 291 292 // In case there is a failure short of our completely reading the power-up 293 // message. 294 pB->i2eValid = I2E_INCOMPLETE; 295 296 297 // Now attempt to read the message. 298 299 for (itemp = 0; itemp < sizeof(porStr); itemp++) 300 { 301 // We expect the entire message is ready. 302 if (HAS_NO_INPUT(pB)) 303 { 304 pB->i2ePomSize = itemp; 305 COMPLETE(pB, I2EE_PORM_SHORT); 306 } 307 308 pB->i2ePom.c[itemp] = c = BYTE_FROM(pB); 309 310 // We check the magic numbers as soon as they are supposed to be read 311 // (rather than after) to minimize effect of reading something we 312 // already suspect can't be "us". 313 if ( (itemp == POR_1_INDEX && c != POR_MAGIC_1) || 314 (itemp == POR_2_INDEX && c != POR_MAGIC_2)) 315 { 316 pB->i2ePomSize = itemp+1; 317 COMPLETE(pB, I2EE_BADMAGIC); 318 } 319 } 320 321 pB->i2ePomSize = itemp; 322 323 // Ensure that this was all the data... 324 if (HAS_INPUT(pB)) 325 COMPLETE(pB, I2EE_PORM_LONG); 326 327 // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper: 328 // Implying we will not be able to download any code either: That's ok: the 329 // condition is pretty explicit. 330 if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER) 331 { 332 COMPLETE(pB, I2EE_POSTERR); 333 } 334 335 // Determine anything which must be done differently depending on the family 336 // of boards! 337 switch (pB->i2ePom.e.porID & POR_ID_FAMILY) 338 { 339 case POR_ID_FII: // IntelliPort-II 340 341 pB->i2eFifoStyle = FIFO_II; 342 pB->i2eFifoSize = 512; // 512 bytes, always 343 pB->i2eDataWidth16 = NO; 344 345 pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit 346 // slot, we do allow it to be done (documentation!) 347 348 pB->i2eGoodMap[1] = 349 pB->i2eGoodMap[2] = 350 pB->i2eGoodMap[3] = 351 pB->i2eChannelMap[1] = 352 pB->i2eChannelMap[2] = 353 pB->i2eChannelMap[3] = 0; 354 355 switch (pB->i2ePom.e.porID & POR_ID_SIZE) 356 { 357 case POR_ID_II_4: 358 pB->i2eGoodMap[0] = 359 pB->i2eChannelMap[0] = 0x0f; // four-port 360 361 // Since porPorts1 is based on the Hardware ID register, the numbers 362 // should always be consistent for IntelliPort-II. Ditto below... 363 if (pB->i2ePom.e.porPorts1 != 4) 364 { 365 COMPLETE(pB, I2EE_INCONSIST); 366 } 367 break; 368 369 case POR_ID_II_8: 370 case POR_ID_II_8R: 371 pB->i2eGoodMap[0] = 372 pB->i2eChannelMap[0] = 0xff; // Eight port 373 if (pB->i2ePom.e.porPorts1 != 8) 374 { 375 COMPLETE(pB, I2EE_INCONSIST); 376 } 377 break; 378 379 case POR_ID_II_6: 380 pB->i2eGoodMap[0] = 381 pB->i2eChannelMap[0] = 0x3f; // Six Port 382 if (pB->i2ePom.e.porPorts1 != 6) 383 { 384 COMPLETE(pB, I2EE_INCONSIST); 385 } 386 break; 387 } 388 389 // Fix up the "good channel list based on any errors reported. 390 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART1) 391 { 392 pB->i2eGoodMap[0] &= ~0x0f; 393 } 394 395 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART2) 396 { 397 pB->i2eGoodMap[0] &= ~0xf0; 398 } 399 400 break; // POR_ID_FII case 401 402 case POR_ID_FIIEX: // IntelliPort-IIEX 403 404 pB->i2eFifoStyle = FIFO_IIEX; 405 406 itemp = pB->i2ePom.e.porFifoSize; 407 408 // Implicit assumption that fifo would not grow beyond 32k, 409 // nor would ever be less than 256. 410 411 if (itemp < 8 || itemp > 15) 412 { 413 COMPLETE(pB, I2EE_INCONSIST); 414 } 415 pB->i2eFifoSize = (1 << itemp); 416 417 // These are based on what P.O.S.T thinks should be there, based on 418 // box ID registers 419 ilimit = pB->i2ePom.e.porNumBoxes; 420 if (ilimit > ABS_MAX_BOXES) 421 { 422 ilimit = ABS_MAX_BOXES; 423 } 424 425 // For as many boxes as EXIST, gives the type of box. 426 // Added 8/6/93: check for the ISA-4 (asic) which looks like an 427 // expandable but for whom "8 or 16?" is not the right question. 428 429 utemp = pB->i2ePom.e.porFlags; 430 if (utemp & POR_CEX4) 431 { 432 pB->i2eChannelMap[0] = 0x000f; 433 } else { 434 utemp &= POR_BOXES; 435 for (itemp = 0; itemp < ilimit; itemp++) 436 { 437 pB->i2eChannelMap[itemp] = 438 ((utemp & POR_BOX_16) ? 0xffff : 0x00ff); 439 utemp >>= 1; 440 } 441 } 442 443 // These are based on what P.O.S.T actually found. 444 445 utemp = (pB->i2ePom.e.porPorts2 << 8) + pB->i2ePom.e.porPorts1; 446 447 for (itemp = 0; itemp < ilimit; itemp++) 448 { 449 pB->i2eGoodMap[itemp] = 0; 450 if (utemp & 1) pB->i2eGoodMap[itemp] |= 0x000f; 451 if (utemp & 2) pB->i2eGoodMap[itemp] |= 0x00f0; 452 if (utemp & 4) pB->i2eGoodMap[itemp] |= 0x0f00; 453 if (utemp & 8) pB->i2eGoodMap[itemp] |= 0xf000; 454 utemp >>= 4; 455 } 456 457 // Now determine whether we should transfer in 8 or 16-bit mode. 458 switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) ) 459 { 460 case POR_BUS_SLOT16 | POR_BUS_DIP16: 461 pB->i2eDataWidth16 = YES; 462 pB->i2eMaxIrq = 15; 463 break; 464 465 case POR_BUS_SLOT16: 466 pB->i2eDataWidth16 = NO; 467 pB->i2eMaxIrq = 15; 468 break; 469 470 case 0: 471 case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care. 472 default: 473 pB->i2eDataWidth16 = NO; 474 pB->i2eMaxIrq = 7; 475 break; 476 } 477 break; // POR_ID_FIIEX case 478 479 default: // Unknown type of board 480 COMPLETE(pB, I2EE_BAD_FAMILY); 481 break; 482 } // End the switch based on family 483 484 // Temporarily, claim there is no room in the outbound fifo. 485 // We will maintain this whenever we check for an empty outbound FIFO. 486 pB->i2eFifoRemains = 0; 487 488 // Now, based on the bus type, should we expect to be able to re-configure 489 // interrupts (say, for testing purposes). 490 switch (pB->i2ePom.e.porBus & POR_BUS_TYPE) 491 { 492 case POR_BUS_T_ISA: 493 case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok. 494 pB->i2eChangeIrq = YES; 495 break; 496 case POR_BUS_T_MCA: 497 case POR_BUS_T_EISA: 498 pB->i2eChangeIrq = NO; 499 break; 500 default: 501 COMPLETE(pB, I2EE_BADBUS); 502 } 503 504 if (pB->i2eDataWidth16 == YES) 505 { 506 pB->i2eWriteBuf = iiWriteBuf16; 507 pB->i2eReadBuf = iiReadBuf16; 508 pB->i2eWriteWord = iiWriteWord16; 509 pB->i2eReadWord = iiReadWord16; 510 } else { 511 pB->i2eWriteBuf = iiWriteBuf8; 512 pB->i2eReadBuf = iiReadBuf8; 513 pB->i2eWriteWord = iiWriteWord8; 514 pB->i2eReadWord = iiReadWord8; 515 } 516 517 switch(pB->i2eFifoStyle) 518 { 519 case FIFO_II: 520 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyII; 521 pB->i2eTxMailEmpty = iiTxMailEmptyII; 522 pB->i2eTrySendMail = iiTrySendMailII; 523 pB->i2eGetMail = iiGetMailII; 524 pB->i2eEnableMailIrq = iiEnableMailIrqII; 525 pB->i2eWriteMask = iiWriteMaskII; 526 527 break; 528 529 case FIFO_IIEX: 530 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyIIEX; 531 pB->i2eTxMailEmpty = iiTxMailEmptyIIEX; 532 pB->i2eTrySendMail = iiTrySendMailIIEX; 533 pB->i2eGetMail = iiGetMailIIEX; 534 pB->i2eEnableMailIrq = iiEnableMailIrqIIEX; 535 pB->i2eWriteMask = iiWriteMaskIIEX; 536 537 break; 538 539 default: 540 COMPLETE(pB, I2EE_INCONSIST); 541 } 542 543 // Initialize state information. 544 pB->i2eState = II_STATE_READY; // Ready to load loadware. 545 546 // Some Final cleanup: 547 // For some boards, the bootstrap firmware may perform some sort of test 548 // resulting in a stray character pending in the incoming mailbox. If one is 549 // there, it should be read and discarded, especially since for the standard 550 // firmware, it's the mailbox that interrupts the host. 551 552 pB->i2eStartMail = iiGetMail(pB); 553 554 // Throw it away and clear the mailbox structure element 555 pB->i2eStartMail = NO_MAIL_HERE; 556 557 // Everything is ok now, return with good status/ 558 559 pB->i2eValid = I2E_MAGIC; 560 COMPLETE(pB, I2EE_GOOD); 561} 562 563//======================================================= 564// Delay Routines 565// 566// iiDelayIO 567// iiNop 568//======================================================= 569 570static void 571ii2DelayWakeup(unsigned long id) 572{ 573 wake_up_interruptible ( &pDelayWait ); 574} 575 576//****************************************************************************** 577// Function: ii2DelayTimer(mseconds) 578// Parameters: mseconds - number of milliseconds to delay 579// 580// Returns: Nothing 581// 582// Description: 583// 584// This routine delays for approximately mseconds milliseconds and is intended 585// to be called indirectly through i2Delay field in i2eBordStr. It uses the 586// Linux timer_list mechanism. 587// 588// The Linux timers use a unit called "jiffies" which are 10mS in the Intel 589// architecture. This function rounds the delay period up to the next "jiffy". 590// In the Alpha architecture the "jiffy" is 1mS, but this driver is not intended 591// for Alpha platforms at this time. 592// 593//****************************************************************************** 594static void 595ii2DelayTimer(unsigned int mseconds) 596{ 597 wait_queue_t wait; 598 599 init_waitqueue_entry(&wait, current); 600 601 init_timer ( pDelayTimer ); 602 603 add_wait_queue(&pDelayWait, &wait); 604 605 set_current_state( TASK_INTERRUPTIBLE ); 606 607 pDelayTimer->expires = jiffies + ( mseconds + 9 ) / 10; 608 pDelayTimer->function = ii2DelayWakeup; 609 pDelayTimer->data = 0; 610 611 add_timer ( pDelayTimer ); 612 613 schedule(); 614 615 set_current_state( TASK_RUNNING ); 616 remove_wait_queue(&pDelayWait, &wait); 617 618 del_timer ( pDelayTimer ); 619} 620 621 622//****************************************************************************** 623// Function: ii2Nop() 624// Parameters: None 625// 626// Returns: Nothing 627// 628// Description: 629// 630// iiInitialize will set i2eDelay to this if the delay parameter is NULL. This 631// saves checking for a NULL pointer at every call. 632//****************************************************************************** 633static void 634ii2Nop(void) 635{ 636 return; // no mystery here 637} 638 639//======================================================= 640// Routines which are available in 8/16-bit versions, or 641// in different fifo styles. These are ALL called 642// indirectly through the board structure. 643//======================================================= 644 645//****************************************************************************** 646// Function: iiWriteBuf16(pB, address, count) 647// Parameters: pB - pointer to board structure 648// address - address of data to write 649// count - number of data bytes to write 650// 651// Returns: True if everything appears copacetic. 652// False if there is any error: the pB->i2eError field has the error 653// 654// Description: 655// 656// Writes 'count' bytes from 'address' to the data fifo specified by the board 657// structure pointer pB. Should count happen to be odd, an extra pad byte is 658// sent (identity unknown...). Uses 16-bit (word) operations. Is called 659// indirectly through pB->i2eWriteBuf. 660// 661//****************************************************************************** 662static int 663iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count) 664{ 665 // Rudimentary sanity checking here. 666 if (pB->i2eValid != I2E_MAGIC) 667 COMPLETE(pB, I2EE_INVALID); 668 669 OUTSW ( pB->i2eData, address, count); 670 671 COMPLETE(pB, I2EE_GOOD); 672} 673 674//****************************************************************************** 675// Function: iiWriteBuf8(pB, address, count) 676// Parameters: pB - pointer to board structure 677// address - address of data to write 678// count - number of data bytes to write 679// 680// Returns: True if everything appears copacetic. 681// False if there is any error: the pB->i2eError field has the error 682// 683// Description: 684// 685// Writes 'count' bytes from 'address' to the data fifo specified by the board 686// structure pointer pB. Should count happen to be odd, an extra pad byte is 687// sent (identity unknown...). This is to be consistent with the 16-bit version. 688// Uses 8-bit (byte) operations. Is called indirectly through pB->i2eWriteBuf. 689// 690//****************************************************************************** 691static int 692iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count) 693{ 694 /* Rudimentary sanity checking here */ 695 if (pB->i2eValid != I2E_MAGIC) 696 COMPLETE(pB, I2EE_INVALID); 697 698 OUTSB ( pB->i2eData, address, count ); 699 700 COMPLETE(pB, I2EE_GOOD); 701} 702 703//****************************************************************************** 704// Function: iiReadBuf16(pB, address, count) 705// Parameters: pB - pointer to board structure 706// address - address to put data read 707// count - number of data bytes to read 708// 709// Returns: True if everything appears copacetic. 710// False if there is any error: the pB->i2eError field has the error 711// 712// Description: 713// 714// Reads 'count' bytes into 'address' from the data fifo specified by the board 715// structure pointer pB. Should count happen to be odd, an extra pad byte is 716// received (identity unknown...). Uses 16-bit (word) operations. Is called 717// indirectly through pB->i2eReadBuf. 718// 719//****************************************************************************** 720static int 721iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count) 722{ 723 // Rudimentary sanity checking here. 724 if (pB->i2eValid != I2E_MAGIC) 725 COMPLETE(pB, I2EE_INVALID); 726 727 INSW ( pB->i2eData, address, count); 728 729 COMPLETE(pB, I2EE_GOOD); 730} 731 732//****************************************************************************** 733// Function: iiReadBuf8(pB, address, count) 734// Parameters: pB - pointer to board structure 735// address - address to put data read 736// count - number of data bytes to read 737// 738// Returns: True if everything appears copacetic. 739// False if there is any error: the pB->i2eError field has the error 740// 741// Description: 742// 743// Reads 'count' bytes into 'address' from the data fifo specified by the board 744// structure pointer pB. Should count happen to be odd, an extra pad byte is 745// received (identity unknown...). This to match the 16-bit behaviour. Uses 746// 8-bit (byte) operations. Is called indirectly through pB->i2eReadBuf. 747// 748//****************************************************************************** 749static int 750iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count) 751{ 752 // Rudimentary sanity checking here. 753 if (pB->i2eValid != I2E_MAGIC) 754 COMPLETE(pB, I2EE_INVALID); 755 756 INSB ( pB->i2eData, address, count); 757 758 COMPLETE(pB, I2EE_GOOD); 759} 760 761//****************************************************************************** 762// Function: iiReadWord16(pB) 763// Parameters: pB - pointer to board structure 764// 765// Returns: True if everything appears copacetic. 766// False if there is any error: the pB->i2eError field has the error 767// 768// Description: 769// 770// Returns the word read from the data fifo specified by the board-structure 771// pointer pB. Uses a 16-bit operation. Is called indirectly through 772// pB->i2eReadWord. 773// 774//****************************************************************************** 775static unsigned short 776iiReadWord16(i2eBordStrPtr pB) 777{ 778 return (unsigned short)( INW(pB->i2eData) ); 779} 780 781//****************************************************************************** 782// Function: iiReadWord8(pB) 783// Parameters: pB - pointer to board structure 784// 785// Returns: True if everything appears copacetic. 786// False if there is any error: the pB->i2eError field has the error 787// 788// Description: 789// 790// Returns the word read from the data fifo specified by the board-structure 791// pointer pB. Uses two 8-bit operations. Bytes are assumed to be LSB first. Is 792// called indirectly through pB->i2eReadWord. 793// 794//****************************************************************************** 795static unsigned short 796iiReadWord8(i2eBordStrPtr pB) 797{ 798 unsigned short urs; 799 800 urs = INB ( pB->i2eData ); 801 802 return ( ( INB ( pB->i2eData ) << 8 ) | urs ); 803} 804 805//****************************************************************************** 806// Function: iiWriteWord16(pB, value) 807// Parameters: pB - pointer to board structure 808// value - data to write 809// 810// Returns: True if everything appears copacetic. 811// False if there is any error: the pB->i2eError field has the error 812// 813// Description: 814// 815// Writes the word 'value' to the data fifo specified by the board-structure 816// pointer pB. Uses 16-bit operation. Is called indirectly through 817// pB->i2eWriteWord. 818// 819//****************************************************************************** 820static void 821iiWriteWord16(i2eBordStrPtr pB, unsigned short value) 822{ 823 WORD_TO(pB, (int)value); 824} 825 826//****************************************************************************** 827// Function: iiWriteWord8(pB, value) 828// Parameters: pB - pointer to board structure 829// value - data to write 830// 831// Returns: True if everything appears copacetic. 832// False if there is any error: the pB->i2eError field has the error 833// 834// Description: 835// 836// Writes the word 'value' to the data fifo specified by the board-structure 837// pointer pB. Uses two 8-bit operations (writes LSB first). Is called 838// indirectly through pB->i2eWriteWord. 839// 840//****************************************************************************** 841static void 842iiWriteWord8(i2eBordStrPtr pB, unsigned short value) 843{ 844 BYTE_TO(pB, (char)value); 845 BYTE_TO(pB, (char)(value >> 8) ); 846} 847 848//****************************************************************************** 849// Function: iiWaitForTxEmptyII(pB, mSdelay) 850// Parameters: pB - pointer to board structure 851// mSdelay - period to wait before returning 852// 853// Returns: True if the FIFO is empty. 854// False if it not empty in the required time: the pB->i2eError 855// field has the error. 856// 857// Description: 858// 859// Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if 860// not empty by the required time, returns false and error in pB->i2eError, 861// otherwise returns true. 862// 863// mSdelay == 0 is taken to mean must be empty on the first test. 864// 865// This version operates on IntelliPort-II - style FIFO's 866// 867// Note this routine is organized so that if status is ok there is no delay at 868// all called either before or after the test. Is called indirectly through 869// pB->i2eWaitForTxEmpty. 870// 871//****************************************************************************** 872static int 873iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay) 874{ 875 unsigned long flags; 876 int itemp; 877 878 for (;;) 879 { 880 // This routine hinges on being able to see the "other" status register 881 // (as seen by the local processor). His incoming fifo is our outgoing 882 // FIFO. 883 // 884 // By the nature of this routine, you would be using this as part of a 885 // larger atomic context: i.e., you would use this routine to ensure the 886 // fifo empty, then act on this information. Between these two halves, 887 // you will generally not want to service interrupts or in any way 888 // disrupt the assumptions implicit in the larger context. 889 // 890 // Even worse, however, this routine "shifts" the status register to 891 // point to the local status register which is not the usual situation. 892 // Therefore for extra safety, we force the critical section to be 893 // completely atomic, and pick up after ourselves before allowing any 894 // interrupts of any kind. 895 896 897 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) 898 OUTB(pB->i2ePointer, SEL_COMMAND); 899 OUTB(pB->i2ePointer, SEL_CMD_SH); 900 901 itemp = INB(pB->i2eStatus); 902 903 OUTB(pB->i2ePointer, SEL_COMMAND); 904 OUTB(pB->i2ePointer, SEL_CMD_UNSH); 905 906 if (itemp & ST_IN_EMPTY) 907 { 908 UPDATE_FIFO_ROOM(pB); 909 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 910 COMPLETE(pB, I2EE_GOOD); 911 } 912 913 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 914 915 if (mSdelay-- == 0) 916 break; 917 918 iiDelay(pB, 1); /* 1 mS granularity on checking condition */ 919 } 920 COMPLETE(pB, I2EE_TXE_TIME); 921} 922 923//****************************************************************************** 924// Function: iiWaitForTxEmptyIIEX(pB, mSdelay) 925// Parameters: pB - pointer to board structure 926// mSdelay - period to wait before returning 927// 928// Returns: True if the FIFO is empty. 929// False if it not empty in the required time: the pB->i2eError 930// field has the error. 931// 932// Description: 933// 934// Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if 935// not empty by the required time, returns false and error in pB->i2eError, 936// otherwise returns true. 937// 938// mSdelay == 0 is taken to mean must be empty on the first test. 939// 940// This version operates on IntelliPort-IIEX - style FIFO's 941// 942// Note this routine is organized so that if status is ok there is no delay at 943// all called either before or after the test. Is called indirectly through 944// pB->i2eWaitForTxEmpty. 945// 946//****************************************************************************** 947static int 948iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay) 949{ 950 unsigned long flags; 951 952 for (;;) 953 { 954 // By the nature of this routine, you would be using this as part of a 955 // larger atomic context: i.e., you would use this routine to ensure the 956 // fifo empty, then act on this information. Between these two halves, 957 // you will generally not want to service interrupts or in any way 958 // disrupt the assumptions implicit in the larger context. 959 960 WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) 961 962 if (INB(pB->i2eStatus) & STE_OUT_MT) { 963 UPDATE_FIFO_ROOM(pB); 964 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 965 COMPLETE(pB, I2EE_GOOD); 966 } 967 WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) 968 969 if (mSdelay-- == 0) 970 break; 971 972 iiDelay(pB, 1); // 1 mS granularity on checking condition 973 } 974 COMPLETE(pB, I2EE_TXE_TIME); 975} 976 977//****************************************************************************** 978// Function: iiTxMailEmptyII(pB) 979// Parameters: pB - pointer to board structure 980// 981// Returns: True if the transmit mailbox is empty. 982// False if it not empty. 983// 984// Description: 985// 986// Returns true or false according to whether the transmit mailbox is empty (and 987// therefore able to accept more mail) 988// 989// This version operates on IntelliPort-II - style FIFO's 990// 991//****************************************************************************** 992static int 993iiTxMailEmptyII(i2eBordStrPtr pB) 994{ 995 int port = pB->i2ePointer; 996 OUTB ( port, SEL_OUTMAIL ); 997 return ( INB(port) == 0 ); 998} 999 1000//****************************************************************************** 1001// Function: iiTxMailEmptyIIEX(pB) 1002// Parameters: pB - pointer to board structure 1003// 1004// Returns: True if the transmit mailbox is empty. 1005// False if it not empty. 1006// 1007// Description: 1008// 1009// Returns true or false according to whether the transmit mailbox is empty (and 1010// therefore able to accept more mail) 1011// 1012// This version operates on IntelliPort-IIEX - style FIFO's 1013// 1014//****************************************************************************** 1015static int 1016iiTxMailEmptyIIEX(i2eBordStrPtr pB) 1017{ 1018 return !(INB(pB->i2eStatus) & STE_OUT_MAIL); 1019} 1020 1021//****************************************************************************** 1022// Function: iiTrySendMailII(pB,mail) 1023// Parameters: pB - pointer to board structure 1024// mail - value to write to mailbox 1025// 1026// Returns: True if the transmit mailbox is empty, and mail is sent. 1027// False if it not empty. 1028// 1029// Description: 1030// 1031// If outgoing mailbox is empty, sends mail and returns true. If outgoing 1032// mailbox is not empty, returns false. 1033// 1034// This version operates on IntelliPort-II - style FIFO's 1035// 1036//****************************************************************************** 1037static int 1038iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail) 1039{ 1040 int port = pB->i2ePointer; 1041 1042 OUTB(port, SEL_OUTMAIL); 1043 if (INB(port) == 0) { 1044 OUTB(port, SEL_OUTMAIL); 1045 OUTB(port, mail); 1046 return 1; 1047 } 1048 return 0; 1049} 1050 1051//****************************************************************************** 1052// Function: iiTrySendMailIIEX(pB,mail) 1053// Parameters: pB - pointer to board structure 1054// mail - value to write to mailbox 1055// 1056// Returns: True if the transmit mailbox is empty, and mail is sent. 1057// False if it not empty. 1058// 1059// Description: 1060// 1061// If outgoing mailbox is empty, sends mail and returns true. If outgoing 1062// mailbox is not empty, returns false. 1063// 1064// This version operates on IntelliPort-IIEX - style FIFO's 1065// 1066//****************************************************************************** 1067static int 1068iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) 1069{ 1070 if(INB(pB->i2eStatus) & STE_OUT_MAIL) { 1071 return 0; 1072 } 1073 OUTB(pB->i2eXMail, mail); 1074 return 1; 1075} 1076 1077//****************************************************************************** 1078// Function: iiGetMailII(pB,mail) 1079// Parameters: pB - pointer to board structure 1080// 1081// Returns: Mailbox data or NO_MAIL_HERE. 1082// 1083// Description: 1084// 1085// If no mail available, returns NO_MAIL_HERE otherwise returns the data from 1086// the mailbox, which is guaranteed != NO_MAIL_HERE. 1087// 1088// This version operates on IntelliPort-II - style FIFO's 1089// 1090//****************************************************************************** 1091static unsigned short 1092iiGetMailII(i2eBordStrPtr pB) 1093{ 1094 if (HAS_MAIL(pB)) { 1095 OUTB(pB->i2ePointer, SEL_INMAIL); 1096 return INB(pB->i2ePointer); 1097 } else { 1098 return NO_MAIL_HERE; 1099 } 1100} 1101 1102//****************************************************************************** 1103// Function: iiGetMailIIEX(pB,mail) 1104// Parameters: pB - pointer to board structure 1105// 1106// Returns: Mailbox data or NO_MAIL_HERE. 1107// 1108// Description: 1109// 1110// If no mail available, returns NO_MAIL_HERE otherwise returns the data from 1111// the mailbox, which is guaranteed != NO_MAIL_HERE. 1112// 1113// This version operates on IntelliPort-IIEX - style FIFO's 1114// 1115//****************************************************************************** 1116static unsigned short 1117iiGetMailIIEX(i2eBordStrPtr pB) 1118{ 1119 if (HAS_MAIL(pB)) { 1120 return INB(pB->i2eXMail); 1121 } else { 1122 return NO_MAIL_HERE; 1123 } 1124} 1125 1126//****************************************************************************** 1127// Function: iiEnableMailIrqII(pB) 1128// Parameters: pB - pointer to board structure 1129// 1130// Returns: Nothing 1131// 1132// Description: 1133// 1134// Enables board to interrupt host (only) by writing to host's in-bound mailbox. 1135// 1136// This version operates on IntelliPort-II - style FIFO's 1137// 1138//****************************************************************************** 1139static void 1140iiEnableMailIrqII(i2eBordStrPtr pB) 1141{ 1142 OUTB(pB->i2ePointer, SEL_MASK); 1143 OUTB(pB->i2ePointer, ST_IN_MAIL); 1144} 1145 1146//****************************************************************************** 1147// Function: iiEnableMailIrqIIEX(pB) 1148// Parameters: pB - pointer to board structure 1149// 1150// Returns: Nothing 1151// 1152// Description: 1153// 1154// Enables board to interrupt host (only) by writing to host's in-bound mailbox. 1155// 1156// This version operates on IntelliPort-IIEX - style FIFO's 1157// 1158//****************************************************************************** 1159static void 1160iiEnableMailIrqIIEX(i2eBordStrPtr pB) 1161{ 1162 OUTB(pB->i2eXMask, MX_IN_MAIL); 1163} 1164 1165//****************************************************************************** 1166// Function: iiWriteMaskII(pB) 1167// Parameters: pB - pointer to board structure 1168// 1169// Returns: Nothing 1170// 1171// Description: 1172// 1173// Writes arbitrary value to the mask register. 1174// 1175// This version operates on IntelliPort-II - style FIFO's 1176// 1177//****************************************************************************** 1178static void 1179iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) 1180{ 1181 OUTB(pB->i2ePointer, SEL_MASK); 1182 OUTB(pB->i2ePointer, value); 1183} 1184 1185//****************************************************************************** 1186// Function: iiWriteMaskIIEX(pB) 1187// Parameters: pB - pointer to board structure 1188// 1189// Returns: Nothing 1190// 1191// Description: 1192// 1193// Writes arbitrary value to the mask register. 1194// 1195// This version operates on IntelliPort-IIEX - style FIFO's 1196// 1197//****************************************************************************** 1198static void 1199iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value) 1200{ 1201 OUTB(pB->i2eXMask, value); 1202} 1203 1204//****************************************************************************** 1205// Function: iiDownloadBlock(pB, pSource, isStandard) 1206// Parameters: pB - pointer to board structure 1207// pSource - loadware block to download 1208// isStandard - True if "standard" loadware, else false. 1209// 1210// Returns: Success or Failure 1211// 1212// Description: 1213// 1214// Downloads a single block (at pSource)to the board referenced by pB. Caller 1215// sets isStandard to true/false according to whether the "standard" loadware is 1216// what's being loaded. The normal process, then, is to perform an iiInitialize 1217// to the board, then perform some number of iiDownloadBlocks using the returned 1218// state to determine when download is complete. 1219// 1220// Possible return values: (see I2ELLIS.H) 1221// II_DOWN_BADVALID 1222// II_DOWN_BADFILE 1223// II_DOWN_CONTINUING 1224// II_DOWN_GOOD 1225// II_DOWN_BAD 1226// II_DOWN_BADSTATE 1227// II_DOWN_TIMEOUT 1228// 1229// Uses the i2eState and i2eToLoad fields (initialized at iiInitialize) to 1230// determine whether this is the first block, whether to check for magic 1231// numbers, how many blocks there are to go... 1232// 1233//****************************************************************************** 1234static int 1235iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard) 1236{ 1237 int itemp; 1238 int loadedFirst; 1239 1240 if (pB->i2eValid != I2E_MAGIC) return II_DOWN_BADVALID; 1241 1242 switch(pB->i2eState) 1243 { 1244 case II_STATE_READY: 1245 1246 // Loading the first block after reset. Must check the magic number of the 1247 // loadfile, store the number of blocks we expect to load. 1248 if (pSource->e.loadMagic != MAGIC_LOADFILE) 1249 { 1250 return II_DOWN_BADFILE; 1251 } 1252 1253 // Next we store the total number of blocks to load, including this one. 1254 pB->i2eToLoad = 1 + pSource->e.loadBlocksMore; 1255 1256 // Set the state, store the version numbers. ('Cause this may have come 1257 // from a file - we might want to report these versions and revisions in 1258 // case of an error! 1259 pB->i2eState = II_STATE_LOADING; 1260 pB->i2eLVersion = pSource->e.loadVersion; 1261 pB->i2eLRevision = pSource->e.loadRevision; 1262 pB->i2eLSub = pSource->e.loadSubRevision; 1263 1264 // The time and date of compilation is also available but don't bother 1265 // storing it for normal purposes. 1266 loadedFirst = 1; 1267 break; 1268 1269 case II_STATE_LOADING: 1270 loadedFirst = 0; 1271 break; 1272 1273 default: 1274 return II_DOWN_BADSTATE; 1275 } 1276 1277 // Now we must be in the II_STATE_LOADING state, and we assume i2eToLoad 1278 // must be positive still, because otherwise we would have cleaned up last 1279 // time and set the state to II_STATE_LOADED. 1280 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) { 1281 return II_DOWN_TIMEOUT; 1282 } 1283 1284 if (!iiWriteBuf(pB, pSource->c, LOADWARE_BLOCK_SIZE)) { 1285 return II_DOWN_BADVALID; 1286 } 1287 1288 // If we just loaded the first block, wait for the fifo to empty an extra 1289 // long time to allow for any special startup code in the firmware, like 1290 // sending status messages to the LCD's. 1291 1292 if (loadedFirst) { 1293 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_START_TIME)) { 1294 return II_DOWN_TIMEOUT; 1295 } 1296 } 1297 1298 // Determine whether this was our last block! 1299 if (--(pB->i2eToLoad)) { 1300 return II_DOWN_CONTINUING; // more to come... 1301 } 1302 1303 // It WAS our last block: Clean up operations... 1304 // ...Wait for last buffer to drain from the board... 1305 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) { 1306 return II_DOWN_TIMEOUT; 1307 } 1308 // If there were only a single block written, this would come back 1309 // immediately and be harmless, though not strictly necessary. 1310 itemp = MAX_DLOAD_ACK_TIME/10; 1311 while (--itemp) { 1312 if (HAS_INPUT(pB)) { 1313 switch(BYTE_FROM(pB)) 1314 { 1315 case LOADWARE_OK: 1316 pB->i2eState = 1317 isStandard ? II_STATE_STDLOADED :II_STATE_LOADED; 1318 1319 // Some revisions of the bootstrap firmware (e.g. ISA-8 1.0.2) 1320 // will, // if there is a debug port attached, require some 1321 // time to send information to the debug port now. It will do 1322 // this before // executing any of the code we just downloaded. 1323 // It may take up to 700 milliseconds. 1324 if (pB->i2ePom.e.porDiag2 & POR_DEBUG_PORT) { 1325 iiDelay(pB, 700); 1326 } 1327 1328 return II_DOWN_GOOD; 1329 1330 case LOADWARE_BAD: 1331 default: 1332 return II_DOWN_BAD; 1333 } 1334 } 1335 1336 iiDelay(pB, 10); // 10 mS granularity on checking condition 1337 } 1338 1339 // Drop-through --> timed out waiting for firmware confirmation 1340 1341 pB->i2eState = II_STATE_BADLOAD; 1342 return II_DOWN_TIMEOUT; 1343} 1344 1345//****************************************************************************** 1346// Function: iiDownloadAll(pB, pSource, isStandard, size) 1347// Parameters: pB - pointer to board structure 1348// pSource - loadware block to download 1349// isStandard - True if "standard" loadware, else false. 1350// size - size of data to download (in bytes) 1351// 1352// Returns: Success or Failure 1353// 1354// Description: 1355// 1356// Given a pointer to a board structure, a pointer to the beginning of some 1357// loadware, whether it is considered the "standard loadware", and the size of 1358// the array in bytes loads the entire array to the board as loadware. 1359// 1360// Assumes the board has been freshly reset and the power-up reset message read. 1361// (i.e., in II_STATE_READY). Complains if state is bad, or if there seems to be 1362// too much or too little data to load, or if iiDownloadBlock complains. 1363//****************************************************************************** 1364static int 1365iiDownloadAll(i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard, int size) 1366{ 1367 int status; 1368 1369 // We know (from context) board should be ready for the first block of 1370 // download. Complain if not. 1371 if (pB->i2eState != II_STATE_READY) return II_DOWN_BADSTATE; 1372 1373 while (size > 0) { 1374 size -= LOADWARE_BLOCK_SIZE; // How much data should there be left to 1375 // load after the following operation ? 1376 1377 // Note we just bump pSource by "one", because its size is actually that 1378 // of an entire block, same as LOADWARE_BLOCK_SIZE. 1379 status = iiDownloadBlock(pB, pSource++, isStandard); 1380 1381 switch(status) 1382 { 1383 case II_DOWN_GOOD: 1384 return ( (size > 0) ? II_DOWN_OVER : II_DOWN_GOOD); 1385 1386 case II_DOWN_CONTINUING: 1387 break; 1388 1389 default: 1390 return status; 1391 } 1392 } 1393 1394 // We shouldn't drop out: it means "while" caught us with nothing left to 1395 // download, yet the previous DownloadBlock did not return complete. Ergo, 1396 // not enough data to match the size byte in the header. 1397 return II_DOWN_UNDER; 1398} 1399