1/* 2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * (C) 2007 Bartlomiej Zolnierkiewicz 6 * 7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c 8 * 9 * First cut with LBA48/ATAPI 10 * 11 * TODO: 12 * Channel interlock/reset on both required 13 */ 14 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/pci.h> 18#include <linux/init.h> 19#include <linux/blkdev.h> 20#include <linux/delay.h> 21#include <scsi/scsi_host.h> 22#include <linux/libata.h> 23 24#define DRV_NAME "pata_pdc202xx_old" 25#define DRV_VERSION "0.4.2" 26 27static int pdc2026x_cable_detect(struct ata_port *ap) 28{ 29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 30 u16 cis; 31 32 pci_read_config_word(pdev, 0x50, &cis); 33 if (cis & (1 << (10 + ap->port_no))) 34 return ATA_CBL_PATA40; 35 return ATA_CBL_PATA80; 36} 37 38/** 39 * pdc202xx_configure_piomode - set chip PIO timing 40 * @ap: ATA interface 41 * @adev: ATA device 42 * @pio: PIO mode 43 * 44 * Called to do the PIO mode setup. Our timing registers are shared 45 * so a configure_dmamode call will undo any work we do here and vice 46 * versa 47 */ 48 49static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) 50{ 51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 52 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; 53 static u16 pio_timing[5] = { 54 0x0913, 0x050C , 0x0308, 0x0206, 0x0104 55 }; 56 u8 r_ap, r_bp; 57 58 pci_read_config_byte(pdev, port, &r_ap); 59 pci_read_config_byte(pdev, port + 1, &r_bp); 60 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */ 61 r_bp &= ~0x1F; 62 r_ap |= (pio_timing[pio] >> 8); 63 r_bp |= (pio_timing[pio] & 0xFF); 64 65 if (ata_pio_need_iordy(adev)) 66 r_ap |= 0x20; /* IORDY enable */ 67 if (adev->class == ATA_DEV_ATA) 68 r_ap |= 0x10; /* FIFO enable */ 69 pci_write_config_byte(pdev, port, r_ap); 70 pci_write_config_byte(pdev, port + 1, r_bp); 71} 72 73/** 74 * pdc202xx_set_piomode - set initial PIO mode data 75 * @ap: ATA interface 76 * @adev: ATA device 77 * 78 * Called to do the PIO mode setup. Our timing registers are shared 79 * but we want to set the PIO timing by default. 80 */ 81 82static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev) 83{ 84 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 85} 86 87/** 88 * pdc202xx_configure_dmamode - set DMA mode in chip 89 * @ap: ATA interface 90 * @adev: ATA device 91 * 92 * Load DMA cycle times into the chip ready for a DMA transfer 93 * to occur. 94 */ 95 96static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev) 97{ 98 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 99 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; 100 static u8 udma_timing[6][2] = { 101 { 0x60, 0x03 }, /* 33 Mhz Clock */ 102 { 0x40, 0x02 }, 103 { 0x20, 0x01 }, 104 { 0x40, 0x02 }, /* 66 Mhz Clock */ 105 { 0x20, 0x01 }, 106 { 0x20, 0x01 } 107 }; 108 static u8 mdma_timing[3][2] = { 109 { 0x60, 0x03 }, 110 { 0x60, 0x04 }, 111 { 0xe0, 0x0f }, 112 }; 113 u8 r_bp, r_cp; 114 115 pci_read_config_byte(pdev, port + 1, &r_bp); 116 pci_read_config_byte(pdev, port + 2, &r_cp); 117 118 r_bp &= ~0xE0; 119 r_cp &= ~0x0F; 120 121 if (adev->dma_mode >= XFER_UDMA_0) { 122 int speed = adev->dma_mode - XFER_UDMA_0; 123 r_bp |= udma_timing[speed][0]; 124 r_cp |= udma_timing[speed][1]; 125 126 } else { 127 int speed = adev->dma_mode - XFER_MW_DMA_0; 128 r_bp |= mdma_timing[speed][0]; 129 r_cp |= mdma_timing[speed][1]; 130 } 131 pci_write_config_byte(pdev, port + 1, r_bp); 132 pci_write_config_byte(pdev, port + 2, r_cp); 133 134} 135 136/** 137 * pdc2026x_bmdma_start - DMA engine begin 138 * @qc: ATA command 139 * 140 * In UDMA3 or higher we have to clock switch for the duration of the 141 * DMA transfer sequence. 142 */ 143 144static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) 145{ 146 struct ata_port *ap = qc->ap; 147 struct ata_device *adev = qc->dev; 148 struct ata_taskfile *tf = &qc->tf; 149 int sel66 = ap->port_no ? 0x08: 0x02; 150 151 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; 152 void __iomem *clock = master + 0x11; 153 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); 154 155 u32 len; 156 157 /* Check we keep host level locking here */ 158 if (adev->dma_mode >= XFER_UDMA_2) 159 iowrite8(ioread8(clock) | sel66, clock); 160 else 161 iowrite8(ioread8(clock) & ~sel66, clock); 162 163 pdc202xx_set_dmamode(ap, qc->dev); 164 165 /* Cases the state machine will not complete correctly without help */ 166 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA) 167 { 168 len = qc->nbytes / 2; 169 170 if (tf->flags & ATA_TFLAG_WRITE) 171 len |= 0x06000000; 172 else 173 len |= 0x05000000; 174 175 iowrite32(len, atapi_reg); 176 } 177 178 /* Activate DMA */ 179 ata_bmdma_start(qc); 180} 181 182/** 183 * pdc2026x_bmdma_end - DMA engine stop 184 * @qc: ATA command 185 * 186 * After a DMA completes we need to put the clock back to 33MHz for 187 * PIO timings. 188 */ 189 190static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) 191{ 192 struct ata_port *ap = qc->ap; 193 struct ata_device *adev = qc->dev; 194 struct ata_taskfile *tf = &qc->tf; 195 196 int sel66 = ap->port_no ? 0x08: 0x02; 197 /* The clock bits are in the same register for both channels */ 198 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; 199 void __iomem *clock = master + 0x11; 200 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); 201 202 /* Cases the state machine will not complete correctly */ 203 if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) { 204 iowrite32(0, atapi_reg); 205 iowrite8(ioread8(clock) & ~sel66, clock); 206 } 207 /* Check we keep host level locking here */ 208 /* Flip back to 33Mhz for PIO */ 209 if (adev->dma_mode >= XFER_UDMA_2) 210 iowrite8(ioread8(clock) & ~sel66, clock); 211 212 ata_bmdma_stop(qc); 213} 214 215/** 216 * pdc2026x_dev_config - device setup hook 217 * @adev: newly found device 218 * 219 * Perform chip specific early setup. We need to lock the transfer 220 * sizes to 8bit to avoid making the state engine on the 2026x cards 221 * barf. 222 */ 223 224static void pdc2026x_dev_config(struct ata_device *adev) 225{ 226 adev->max_sectors = 256; 227} 228 229static struct scsi_host_template pdc202xx_sht = { 230 .module = THIS_MODULE, 231 .name = DRV_NAME, 232 .ioctl = ata_scsi_ioctl, 233 .queuecommand = ata_scsi_queuecmd, 234 .can_queue = ATA_DEF_QUEUE, 235 .this_id = ATA_SHT_THIS_ID, 236 .sg_tablesize = LIBATA_MAX_PRD, 237 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 238 .emulated = ATA_SHT_EMULATED, 239 .use_clustering = ATA_SHT_USE_CLUSTERING, 240 .proc_name = DRV_NAME, 241 .dma_boundary = ATA_DMA_BOUNDARY, 242 .slave_configure = ata_scsi_slave_config, 243 .slave_destroy = ata_scsi_slave_destroy, 244 .bios_param = ata_std_bios_param, 245}; 246 247static struct ata_port_operations pdc2024x_port_ops = { 248 .port_disable = ata_port_disable, 249 .set_piomode = pdc202xx_set_piomode, 250 .set_dmamode = pdc202xx_set_dmamode, 251 .mode_filter = ata_pci_default_filter, 252 .tf_load = ata_tf_load, 253 .tf_read = ata_tf_read, 254 .check_status = ata_check_status, 255 .exec_command = ata_exec_command, 256 .dev_select = ata_std_dev_select, 257 258 .freeze = ata_bmdma_freeze, 259 .thaw = ata_bmdma_thaw, 260 .error_handler = ata_bmdma_error_handler, 261 .post_internal_cmd = ata_bmdma_post_internal_cmd, 262 .cable_detect = ata_cable_40wire, 263 264 .bmdma_setup = ata_bmdma_setup, 265 .bmdma_start = ata_bmdma_start, 266 .bmdma_stop = ata_bmdma_stop, 267 .bmdma_status = ata_bmdma_status, 268 269 .qc_prep = ata_qc_prep, 270 .qc_issue = ata_qc_issue_prot, 271 .data_xfer = ata_data_xfer, 272 273 .irq_handler = ata_interrupt, 274 .irq_clear = ata_bmdma_irq_clear, 275 .irq_on = ata_irq_on, 276 .irq_ack = ata_irq_ack, 277 278 .port_start = ata_port_start, 279}; 280 281static struct ata_port_operations pdc2026x_port_ops = { 282 .port_disable = ata_port_disable, 283 .set_piomode = pdc202xx_set_piomode, 284 .set_dmamode = pdc202xx_set_dmamode, 285 .mode_filter = ata_pci_default_filter, 286 .tf_load = ata_tf_load, 287 .tf_read = ata_tf_read, 288 .check_status = ata_check_status, 289 .exec_command = ata_exec_command, 290 .dev_select = ata_std_dev_select, 291 .dev_config = pdc2026x_dev_config, 292 293 .freeze = ata_bmdma_freeze, 294 .thaw = ata_bmdma_thaw, 295 .error_handler = ata_bmdma_error_handler, 296 .post_internal_cmd = ata_bmdma_post_internal_cmd, 297 .cable_detect = pdc2026x_cable_detect, 298 299 .bmdma_setup = ata_bmdma_setup, 300 .bmdma_start = pdc2026x_bmdma_start, 301 .bmdma_stop = pdc2026x_bmdma_stop, 302 .bmdma_status = ata_bmdma_status, 303 304 .qc_prep = ata_qc_prep, 305 .qc_issue = ata_qc_issue_prot, 306 .data_xfer = ata_data_xfer, 307 308 .irq_handler = ata_interrupt, 309 .irq_clear = ata_bmdma_irq_clear, 310 .irq_on = ata_irq_on, 311 .irq_ack = ata_irq_ack, 312 313 .port_start = ata_port_start, 314}; 315 316static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 317{ 318 static const struct ata_port_info info[3] = { 319 { 320 .sht = &pdc202xx_sht, 321 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 322 .pio_mask = 0x1f, 323 .mwdma_mask = 0x07, 324 .udma_mask = ATA_UDMA2, 325 .port_ops = &pdc2024x_port_ops 326 }, 327 { 328 .sht = &pdc202xx_sht, 329 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 330 .pio_mask = 0x1f, 331 .mwdma_mask = 0x07, 332 .udma_mask = ATA_UDMA4, 333 .port_ops = &pdc2026x_port_ops 334 }, 335 { 336 .sht = &pdc202xx_sht, 337 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 338 .pio_mask = 0x1f, 339 .mwdma_mask = 0x07, 340 .udma_mask = ATA_UDMA5, 341 .port_ops = &pdc2026x_port_ops 342 } 343 344 }; 345 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; 346 347 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) { 348 struct pci_dev *bridge = dev->bus->self; 349 /* Don't grab anything behind a Promise I2O RAID */ 350 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) { 351 if( bridge->device == PCI_DEVICE_ID_INTEL_I960) 352 return -ENODEV; 353 if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM) 354 return -ENODEV; 355 } 356 } 357 return ata_pci_init_one(dev, ppi); 358} 359 360static const struct pci_device_id pdc202xx[] = { 361 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, 362 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, 363 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, 364 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, 365 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, 366 367 { }, 368}; 369 370static struct pci_driver pdc202xx_pci_driver = { 371 .name = DRV_NAME, 372 .id_table = pdc202xx, 373 .probe = pdc202xx_init_one, 374 .remove = ata_pci_remove_one, 375#ifdef CONFIG_PM 376 .suspend = ata_pci_device_suspend, 377 .resume = ata_pci_device_resume, 378#endif 379}; 380 381static int __init pdc202xx_init(void) 382{ 383 return pci_register_driver(&pdc202xx_pci_driver); 384} 385 386static void __exit pdc202xx_exit(void) 387{ 388 pci_unregister_driver(&pdc202xx_pci_driver); 389} 390 391MODULE_AUTHOR("Alan Cox"); 392MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267"); 393MODULE_LICENSE("GPL"); 394MODULE_DEVICE_TABLE(pci, pdc202xx); 395MODULE_VERSION(DRV_VERSION); 396 397module_init(pdc202xx_init); 398module_exit(pdc202xx_exit); 399