1/* 2 * pata-legacy.c - Legacy port PATA/SATA controller driver. 3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; see the file COPYING. If not, write to 17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * An ATA driver for the legacy ATA ports. 20 * 21 * Data Sources: 22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 23 * HT6560 series: 24 * Promise 20230/20620: 25 * http://www.ryston.cz/petr/vlb/pdc20230b.html 26 * http://www.ryston.cz/petr/vlb/pdc20230c.html 27 * http://www.ryston.cz/petr/vlb/pdc20630.html 28 * 29 * Unsupported but docs exist: 30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 31 * Winbond W83759A 32 * 33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 34 * on PC class systems. There are three hybrid devices that are exceptions 35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 37 * 38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 39 * opti82c465mv/promise 20230c/20630 40 * 41 * Use the autospeed and pio_mask options with: 42 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 45 * Winbond W83759A, Promise PDC20230-B 46 * 47 * For now use autospeed and pio_mask as above with the W83759A. This may 48 * change. 49 * 50 * TODO 51 * Merge existing pata_qdi driver 52 * 53 */ 54 55#include <linux/kernel.h> 56#include <linux/module.h> 57#include <linux/pci.h> 58#include <linux/init.h> 59#include <linux/blkdev.h> 60#include <linux/delay.h> 61#include <scsi/scsi_host.h> 62#include <linux/ata.h> 63#include <linux/libata.h> 64#include <linux/platform_device.h> 65 66#define DRV_NAME "pata_legacy" 67#define DRV_VERSION "0.5.5" 68 69#define NR_HOST 6 70 71static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 72static int legacy_irq[NR_HOST] = { 14, 15, 11, 10, 8, 12 }; 73 74struct legacy_data { 75 unsigned long timing; 76 u8 clock[2]; 77 u8 last; 78 int fast; 79 struct platform_device *platform_dev; 80 81}; 82 83static struct legacy_data legacy_data[NR_HOST]; 84static struct ata_host *legacy_host[NR_HOST]; 85static int nr_legacy_host; 86 87 88static int probe_all; /* Set to check all ISA port ranges */ 89static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */ 90static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */ 91static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */ 92static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */ 93static int autospeed; /* Chip present which snoops speed changes */ 94static int pio_mask = 0x1F; /* PIO range for autospeed devices */ 95static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ 96 97/** 98 * legacy_set_mode - mode setting 99 * @ap: IDE interface 100 * @unused: Device that failed when error is returned 101 * 102 * Use a non standard set_mode function. We don't want to be tuned. 103 * 104 * The BIOS configured everything. Our job is not to fiddle. Just use 105 * whatever PIO the hardware is using and leave it at that. When we 106 * get some kind of nice user driven API for control then we can 107 * expand on this as per hdparm in the base kernel. 108 */ 109 110static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused) 111{ 112 int i; 113 114 for (i = 0; i < ATA_MAX_DEVICES; i++) { 115 struct ata_device *dev = &ap->device[i]; 116 if (ata_dev_enabled(dev)) { 117 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); 118 dev->pio_mode = XFER_PIO_0; 119 dev->xfer_mode = XFER_PIO_0; 120 dev->xfer_shift = ATA_SHIFT_PIO; 121 dev->flags |= ATA_DFLAG_PIO; 122 } 123 } 124 return 0; 125} 126 127static struct scsi_host_template legacy_sht = { 128 .module = THIS_MODULE, 129 .name = DRV_NAME, 130 .ioctl = ata_scsi_ioctl, 131 .queuecommand = ata_scsi_queuecmd, 132 .can_queue = ATA_DEF_QUEUE, 133 .this_id = ATA_SHT_THIS_ID, 134 .sg_tablesize = LIBATA_MAX_PRD, 135 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 136 .emulated = ATA_SHT_EMULATED, 137 .use_clustering = ATA_SHT_USE_CLUSTERING, 138 .proc_name = DRV_NAME, 139 .dma_boundary = ATA_DMA_BOUNDARY, 140 .slave_configure = ata_scsi_slave_config, 141 .slave_destroy = ata_scsi_slave_destroy, 142 .bios_param = ata_std_bios_param, 143}; 144 145/* 146 * These ops are used if the user indicates the hardware 147 * snoops the commands to decide on the mode and handles the 148 * mode selection "magically" itself. Several legacy controllers 149 * do this. The mode range can be set if it is not 0x1F by setting 150 * pio_mask as well. 151 */ 152 153static struct ata_port_operations simple_port_ops = { 154 .port_disable = ata_port_disable, 155 .tf_load = ata_tf_load, 156 .tf_read = ata_tf_read, 157 .check_status = ata_check_status, 158 .exec_command = ata_exec_command, 159 .dev_select = ata_std_dev_select, 160 161 .freeze = ata_bmdma_freeze, 162 .thaw = ata_bmdma_thaw, 163 .error_handler = ata_bmdma_error_handler, 164 .post_internal_cmd = ata_bmdma_post_internal_cmd, 165 .cable_detect = ata_cable_40wire, 166 167 .qc_prep = ata_qc_prep, 168 .qc_issue = ata_qc_issue_prot, 169 170 .data_xfer = ata_data_xfer_noirq, 171 172 .irq_handler = ata_interrupt, 173 .irq_clear = ata_bmdma_irq_clear, 174 .irq_on = ata_irq_on, 175 .irq_ack = ata_irq_ack, 176 177 .port_start = ata_port_start, 178}; 179 180static struct ata_port_operations legacy_port_ops = { 181 .set_mode = legacy_set_mode, 182 183 .port_disable = ata_port_disable, 184 .tf_load = ata_tf_load, 185 .tf_read = ata_tf_read, 186 .check_status = ata_check_status, 187 .exec_command = ata_exec_command, 188 .dev_select = ata_std_dev_select, 189 .cable_detect = ata_cable_40wire, 190 191 .freeze = ata_bmdma_freeze, 192 .thaw = ata_bmdma_thaw, 193 .error_handler = ata_bmdma_error_handler, 194 .post_internal_cmd = ata_bmdma_post_internal_cmd, 195 196 .qc_prep = ata_qc_prep, 197 .qc_issue = ata_qc_issue_prot, 198 199 .data_xfer = ata_data_xfer_noirq, 200 201 .irq_handler = ata_interrupt, 202 .irq_clear = ata_bmdma_irq_clear, 203 .irq_on = ata_irq_on, 204 .irq_ack = ata_irq_ack, 205 206 .port_start = ata_port_start, 207}; 208 209/* 210 * Promise 20230C and 20620 support 211 * 212 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to 213 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to 214 * controller and PIO'd to the host and not supported. 215 */ 216 217static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 218{ 219 int tries = 5; 220 int pio = adev->pio_mode - XFER_PIO_0; 221 u8 rt; 222 unsigned long flags; 223 224 /* Safe as UP only. Force I/Os to occur together */ 225 226 local_irq_save(flags); 227 228 /* Unlock the control interface */ 229 do 230 { 231 inb(0x1F5); 232 outb(inb(0x1F2) | 0x80, 0x1F2); 233 inb(0x1F2); 234 inb(0x3F6); 235 inb(0x3F6); 236 inb(0x1F2); 237 inb(0x1F2); 238 } 239 while((inb(0x1F2) & 0x80) && --tries); 240 241 local_irq_restore(flags); 242 243 outb(inb(0x1F4) & 0x07, 0x1F4); 244 245 rt = inb(0x1F3); 246 rt &= 0x07 << (3 * adev->devno); 247 if (pio) 248 rt |= (1 + 3 * pio) << (3 * adev->devno); 249 250 udelay(100); 251 outb(inb(0x1F2) | 0x01, 0x1F2); 252 udelay(100); 253 inb(0x1F5); 254 255} 256 257static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) 258{ 259 struct ata_port *ap = adev->ap; 260 int slop = buflen & 3; 261 unsigned long flags; 262 263 if (ata_id_has_dword_io(adev->id)) { 264 local_irq_save(flags); 265 266 /* Perform the 32bit I/O synchronization sequence */ 267 ioread8(ap->ioaddr.nsect_addr); 268 ioread8(ap->ioaddr.nsect_addr); 269 ioread8(ap->ioaddr.nsect_addr); 270 271 /* Now the data */ 272 273 if (write_data) 274 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 275 else 276 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 277 278 if (unlikely(slop)) { 279 u32 pad; 280 if (write_data) { 281 memcpy(&pad, buf + buflen - slop, slop); 282 pad = le32_to_cpu(pad); 283 iowrite32(pad, ap->ioaddr.data_addr); 284 } else { 285 pad = ioread32(ap->ioaddr.data_addr); 286 pad = cpu_to_le16(pad); 287 memcpy(buf + buflen - slop, &pad, slop); 288 } 289 } 290 local_irq_restore(flags); 291 } 292 else 293 ata_data_xfer_noirq(adev, buf, buflen, write_data); 294} 295 296static struct ata_port_operations pdc20230_port_ops = { 297 .set_piomode = pdc20230_set_piomode, 298 299 .port_disable = ata_port_disable, 300 .tf_load = ata_tf_load, 301 .tf_read = ata_tf_read, 302 .check_status = ata_check_status, 303 .exec_command = ata_exec_command, 304 .dev_select = ata_std_dev_select, 305 306 .freeze = ata_bmdma_freeze, 307 .thaw = ata_bmdma_thaw, 308 .error_handler = ata_bmdma_error_handler, 309 .post_internal_cmd = ata_bmdma_post_internal_cmd, 310 .cable_detect = ata_cable_40wire, 311 312 .qc_prep = ata_qc_prep, 313 .qc_issue = ata_qc_issue_prot, 314 315 .data_xfer = pdc_data_xfer_vlb, 316 317 .irq_handler = ata_interrupt, 318 .irq_clear = ata_bmdma_irq_clear, 319 .irq_on = ata_irq_on, 320 .irq_ack = ata_irq_ack, 321 322 .port_start = ata_port_start, 323}; 324 325/* 326 * Holtek 6560A support 327 * 328 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings 329 * can be loaded). 330 */ 331 332static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 333{ 334 u8 active, recover; 335 struct ata_timing t; 336 337 /* Get the timing data in cycles. For now play safe at 50Mhz */ 338 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 339 340 active = FIT(t.active, 2, 15); 341 recover = FIT(t.recover, 4, 15); 342 343 inb(0x3E6); 344 inb(0x3E6); 345 inb(0x3E6); 346 inb(0x3E6); 347 348 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 349 ioread8(ap->ioaddr.status_addr); 350} 351 352static struct ata_port_operations ht6560a_port_ops = { 353 .set_piomode = ht6560a_set_piomode, 354 355 .port_disable = ata_port_disable, 356 .tf_load = ata_tf_load, 357 .tf_read = ata_tf_read, 358 .check_status = ata_check_status, 359 .exec_command = ata_exec_command, 360 .dev_select = ata_std_dev_select, 361 362 .freeze = ata_bmdma_freeze, 363 .thaw = ata_bmdma_thaw, 364 .error_handler = ata_bmdma_error_handler, 365 .post_internal_cmd = ata_bmdma_post_internal_cmd, 366 .cable_detect = ata_cable_40wire, 367 368 .qc_prep = ata_qc_prep, 369 .qc_issue = ata_qc_issue_prot, 370 371 .data_xfer = ata_data_xfer, /* Check vlb/noirq */ 372 373 .irq_handler = ata_interrupt, 374 .irq_clear = ata_bmdma_irq_clear, 375 .irq_on = ata_irq_on, 376 .irq_ack = ata_irq_ack, 377 378 .port_start = ata_port_start, 379}; 380 381 382static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 383{ 384 u8 active, recover; 385 struct ata_timing t; 386 387 /* Get the timing data in cycles. For now play safe at 50Mhz */ 388 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 389 390 active = FIT(t.active, 2, 15); 391 recover = FIT(t.recover, 2, 16); 392 recover &= 0x15; 393 394 inb(0x3E6); 395 inb(0x3E6); 396 inb(0x3E6); 397 inb(0x3E6); 398 399 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 400 401 if (adev->class != ATA_DEV_ATA) { 402 u8 rconf = inb(0x3E6); 403 if (rconf & 0x24) { 404 rconf &= ~ 0x24; 405 outb(rconf, 0x3E6); 406 } 407 } 408 ioread8(ap->ioaddr.status_addr); 409} 410 411static struct ata_port_operations ht6560b_port_ops = { 412 .set_piomode = ht6560b_set_piomode, 413 414 .port_disable = ata_port_disable, 415 .tf_load = ata_tf_load, 416 .tf_read = ata_tf_read, 417 .check_status = ata_check_status, 418 .exec_command = ata_exec_command, 419 .dev_select = ata_std_dev_select, 420 421 .freeze = ata_bmdma_freeze, 422 .thaw = ata_bmdma_thaw, 423 .error_handler = ata_bmdma_error_handler, 424 .post_internal_cmd = ata_bmdma_post_internal_cmd, 425 .cable_detect = ata_cable_40wire, 426 427 .qc_prep = ata_qc_prep, 428 .qc_issue = ata_qc_issue_prot, 429 430 .data_xfer = ata_data_xfer, 431 432 .irq_handler = ata_interrupt, 433 .irq_clear = ata_bmdma_irq_clear, 434 .irq_on = ata_irq_on, 435 .irq_ack = ata_irq_ack, 436 437 .port_start = ata_port_start, 438}; 439 440/* 441 * Opti core chipset helpers 442 */ 443 444/** 445 * opti_syscfg - read OPTI chipset configuration 446 * @reg: Configuration register to read 447 * 448 * Returns the value of an OPTI system board configuration register. 449 */ 450 451static u8 opti_syscfg(u8 reg) 452{ 453 unsigned long flags; 454 u8 r; 455 456 /* Uniprocessor chipset and must force cycles adjancent */ 457 local_irq_save(flags); 458 outb(reg, 0x22); 459 r = inb(0x24); 460 local_irq_restore(flags); 461 return r; 462} 463 464/* 465 * Opti 82C611A 466 * 467 * This controller supports PIO0 to PIO3. 468 */ 469 470static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) 471{ 472 u8 active, recover, setup; 473 struct ata_timing t; 474 struct ata_device *pair = ata_dev_pair(adev); 475 int clock; 476 int khz[4] = { 50000, 40000, 33000, 25000 }; 477 u8 rc; 478 479 /* Enter configuration mode */ 480 ioread16(ap->ioaddr.error_addr); 481 ioread16(ap->ioaddr.error_addr); 482 iowrite8(3, ap->ioaddr.nsect_addr); 483 484 /* Read VLB clock strapping */ 485 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 486 487 /* Get the timing data in cycles */ 488 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 489 490 /* Setup timing is shared */ 491 if (pair) { 492 struct ata_timing tp; 493 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 494 495 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 496 } 497 498 active = FIT(t.active, 2, 17) - 2; 499 recover = FIT(t.recover, 1, 16) - 1; 500 setup = FIT(t.setup, 1, 4) - 1; 501 502 /* Select the right timing bank for write timing */ 503 rc = ioread8(ap->ioaddr.lbal_addr); 504 rc &= 0x7F; 505 rc |= (adev->devno << 7); 506 iowrite8(rc, ap->ioaddr.lbal_addr); 507 508 /* Write the timings */ 509 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 510 511 /* Select the right bank for read timings, also 512 load the shared timings for address */ 513 rc = ioread8(ap->ioaddr.device_addr); 514 rc &= 0xC0; 515 rc |= adev->devno; /* Index select */ 516 rc |= (setup << 4) | 0x04; 517 iowrite8(rc, ap->ioaddr.device_addr); 518 519 /* Load the read timings */ 520 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 521 522 /* Ensure the timing register mode is right */ 523 rc = ioread8(ap->ioaddr.lbal_addr); 524 rc &= 0x73; 525 rc |= 0x84; 526 iowrite8(rc, ap->ioaddr.lbal_addr); 527 528 /* Exit command mode */ 529 iowrite8(0x83, ap->ioaddr.nsect_addr); 530} 531 532 533static struct ata_port_operations opti82c611a_port_ops = { 534 .set_piomode = opti82c611a_set_piomode, 535 536 .port_disable = ata_port_disable, 537 .tf_load = ata_tf_load, 538 .tf_read = ata_tf_read, 539 .check_status = ata_check_status, 540 .exec_command = ata_exec_command, 541 .dev_select = ata_std_dev_select, 542 543 .freeze = ata_bmdma_freeze, 544 .thaw = ata_bmdma_thaw, 545 .error_handler = ata_bmdma_error_handler, 546 .post_internal_cmd = ata_bmdma_post_internal_cmd, 547 .cable_detect = ata_cable_40wire, 548 549 .qc_prep = ata_qc_prep, 550 .qc_issue = ata_qc_issue_prot, 551 552 .data_xfer = ata_data_xfer, 553 554 .irq_handler = ata_interrupt, 555 .irq_clear = ata_bmdma_irq_clear, 556 .irq_on = ata_irq_on, 557 .irq_ack = ata_irq_ack, 558 559 .port_start = ata_port_start, 560}; 561 562/* 563 * Opti 82C465MV 564 * 565 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 566 * version is dual channel but doesn't have a lot of unique registers. 567 */ 568 569static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 570{ 571 u8 active, recover, setup; 572 struct ata_timing t; 573 struct ata_device *pair = ata_dev_pair(adev); 574 int clock; 575 int khz[4] = { 50000, 40000, 33000, 25000 }; 576 u8 rc; 577 u8 sysclk; 578 579 /* Get the clock */ 580 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ 581 582 /* Enter configuration mode */ 583 ioread16(ap->ioaddr.error_addr); 584 ioread16(ap->ioaddr.error_addr); 585 iowrite8(3, ap->ioaddr.nsect_addr); 586 587 /* Read VLB clock strapping */ 588 clock = 1000000000 / khz[sysclk]; 589 590 /* Get the timing data in cycles */ 591 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 592 593 /* Setup timing is shared */ 594 if (pair) { 595 struct ata_timing tp; 596 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 597 598 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 599 } 600 601 active = FIT(t.active, 2, 17) - 2; 602 recover = FIT(t.recover, 1, 16) - 1; 603 setup = FIT(t.setup, 1, 4) - 1; 604 605 /* Select the right timing bank for write timing */ 606 rc = ioread8(ap->ioaddr.lbal_addr); 607 rc &= 0x7F; 608 rc |= (adev->devno << 7); 609 iowrite8(rc, ap->ioaddr.lbal_addr); 610 611 /* Write the timings */ 612 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 613 614 /* Select the right bank for read timings, also 615 load the shared timings for address */ 616 rc = ioread8(ap->ioaddr.device_addr); 617 rc &= 0xC0; 618 rc |= adev->devno; /* Index select */ 619 rc |= (setup << 4) | 0x04; 620 iowrite8(rc, ap->ioaddr.device_addr); 621 622 /* Load the read timings */ 623 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 624 625 /* Ensure the timing register mode is right */ 626 rc = ioread8(ap->ioaddr.lbal_addr); 627 rc &= 0x73; 628 rc |= 0x84; 629 iowrite8(rc, ap->ioaddr.lbal_addr); 630 631 /* Exit command mode */ 632 iowrite8(0x83, ap->ioaddr.nsect_addr); 633 634 /* We need to know this for quad device on the MVB */ 635 ap->host->private_data = ap; 636} 637 638 639static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) 640{ 641 struct ata_port *ap = qc->ap; 642 struct ata_device *adev = qc->dev; 643 644 /* If timings are set and for the wrong channel (2nd test is 645 due to a libata shortcoming and will eventually go I hope) */ 646 if (ap->host->private_data != ap->host 647 && ap->host->private_data != NULL) 648 opti82c46x_set_piomode(ap, adev); 649 650 return ata_qc_issue_prot(qc); 651} 652 653static struct ata_port_operations opti82c46x_port_ops = { 654 .set_piomode = opti82c46x_set_piomode, 655 656 .port_disable = ata_port_disable, 657 .tf_load = ata_tf_load, 658 .tf_read = ata_tf_read, 659 .check_status = ata_check_status, 660 .exec_command = ata_exec_command, 661 .dev_select = ata_std_dev_select, 662 663 .freeze = ata_bmdma_freeze, 664 .thaw = ata_bmdma_thaw, 665 .error_handler = ata_bmdma_error_handler, 666 .post_internal_cmd = ata_bmdma_post_internal_cmd, 667 .cable_detect = ata_cable_40wire, 668 669 .qc_prep = ata_qc_prep, 670 .qc_issue = opti82c46x_qc_issue_prot, 671 672 .data_xfer = ata_data_xfer, 673 674 .irq_handler = ata_interrupt, 675 .irq_clear = ata_bmdma_irq_clear, 676 .irq_on = ata_irq_on, 677 .irq_ack = ata_irq_ack, 678 679 .port_start = ata_port_start, 680}; 681 682 683/** 684 * legacy_init_one - attach a legacy interface 685 * @port: port number 686 * @io: I/O port start 687 * @ctrl: control port 688 * @irq: interrupt line 689 * 690 * Register an ISA bus IDE interface. Such interfaces are PIO and we 691 * assume do not support IRQ sharing. 692 */ 693 694static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq) 695{ 696 struct legacy_data *ld = &legacy_data[nr_legacy_host]; 697 struct ata_host *host; 698 struct ata_port *ap; 699 struct platform_device *pdev; 700 struct ata_port_operations *ops = &legacy_port_ops; 701 void __iomem *io_addr, *ctrl_addr; 702 int pio_modes = pio_mask; 703 u32 mask = (1 << port); 704 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 705 int ret; 706 707 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0); 708 if (IS_ERR(pdev)) 709 return PTR_ERR(pdev); 710 711 ret = -EBUSY; 712 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 713 devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) 714 goto fail; 715 716 ret = -ENOMEM; 717 io_addr = devm_ioport_map(&pdev->dev, io, 8); 718 ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1); 719 if (!io_addr || !ctrl_addr) 720 goto fail; 721 722 if (ht6560a & mask) { 723 ops = &ht6560a_port_ops; 724 pio_modes = 0x07; 725 iordy = ATA_FLAG_NO_IORDY; 726 } 727 if (ht6560b & mask) { 728 ops = &ht6560b_port_ops; 729 pio_modes = 0x1F; 730 } 731 if (opti82c611a & mask) { 732 ops = &opti82c611a_port_ops; 733 pio_modes = 0x0F; 734 } 735 if (opti82c46x & mask) { 736 ops = &opti82c46x_port_ops; 737 pio_modes = 0x0F; 738 } 739 740 /* Probe for automatically detectable controllers */ 741 742 if (io == 0x1F0 && ops == &legacy_port_ops) { 743 unsigned long flags; 744 745 local_irq_save(flags); 746 747 /* Probes */ 748 inb(0x1F5); 749 outb(inb(0x1F2) | 0x80, 0x1F2); 750 inb(0x1F2); 751 inb(0x3F6); 752 inb(0x3F6); 753 inb(0x1F2); 754 inb(0x1F2); 755 756 if ((inb(0x1F2) & 0x80) == 0) { 757 /* PDC20230c or 20630 ? */ 758 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n"); 759 pio_modes = 0x07; 760 ops = &pdc20230_port_ops; 761 iordy = ATA_FLAG_NO_IORDY; 762 udelay(100); 763 inb(0x1F5); 764 } else { 765 outb(0x55, 0x1F2); 766 inb(0x1F2); 767 inb(0x1F2); 768 if (inb(0x1F2) == 0x00) { 769 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n"); 770 } 771 } 772 local_irq_restore(flags); 773 } 774 775 776 /* Chip does mode setting by command snooping */ 777 if (ops == &legacy_port_ops && (autospeed & mask)) 778 ops = &simple_port_ops; 779 780 ret = -ENOMEM; 781 host = ata_host_alloc(&pdev->dev, 1); 782 if (!host) 783 goto fail; 784 ap = host->ports[0]; 785 786 ap->ops = ops; 787 ap->pio_mask = pio_modes; 788 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 789 ap->ioaddr.cmd_addr = io_addr; 790 ap->ioaddr.altstatus_addr = ctrl_addr; 791 ap->ioaddr.ctl_addr = ctrl_addr; 792 ata_std_ports(&ap->ioaddr); 793 ap->private_data = ld; 794 795 ret = ata_host_activate(host, irq, ata_interrupt, 0, &legacy_sht); 796 if (ret) 797 goto fail; 798 799 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev); 800 ld->platform_dev = pdev; 801 return 0; 802 803fail: 804 platform_device_unregister(pdev); 805 return ret; 806} 807 808/** 809 * legacy_check_special_cases - ATA special cases 810 * @p: PCI device to check 811 * @master: set this if we find an ATA master 812 * @master: set this if we find an ATA secondary 813 * 814 * A small number of vendors implemented early PCI ATA interfaces on bridge logic 815 * without the ATA interface being PCI visible. Where we have a matching PCI driver 816 * we must skip the relevant device here. If we don't know about it then the legacy 817 * driver is the right driver anyway. 818 */ 819 820static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary) 821{ 822 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 823 if (p->vendor == 0x1078 && p->device == 0x0000) { 824 *primary = *secondary = 1; 825 return; 826 } 827 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 828 if (p->vendor == 0x1078 && p->device == 0x0002) { 829 *primary = *secondary = 1; 830 return; 831 } 832 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 833 if (p->vendor == 0x8086 && p->device == 0x1234) { 834 u16 r; 835 pci_read_config_word(p, 0x6C, &r); 836 if (r & 0x8000) { /* ATA port enabled */ 837 if (r & 0x4000) 838 *secondary = 1; 839 else 840 *primary = 1; 841 } 842 return; 843 } 844} 845 846 847/** 848 * legacy_init - attach legacy interfaces 849 * 850 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 851 * Right now we do not scan the ide0 and ide1 address but should do so 852 * for non PCI systems or systems with no PCI IDE legacy mode devices. 853 * If you fix that note there are special cases to consider like VLB 854 * drivers and CS5510/20. 855 */ 856 857static __init int legacy_init(void) 858{ 859 int i; 860 int ct = 0; 861 int primary = 0; 862 int secondary = 0; 863 int last_port = NR_HOST; 864 865 struct pci_dev *p = NULL; 866 867 for_each_pci_dev(p) { 868 int r; 869 /* Check for any overlap of the system ATA mappings. Native mode controllers 870 stuck on these addresses or some devices in 'raid' mode won't be found by 871 the storage class test */ 872 for (r = 0; r < 6; r++) { 873 if (pci_resource_start(p, r) == 0x1f0) 874 primary = 1; 875 if (pci_resource_start(p, r) == 0x170) 876 secondary = 1; 877 } 878 /* Check for special cases */ 879 legacy_check_special_cases(p, &primary, &secondary); 880 881 /* If PCI bus is present then don't probe for tertiary legacy ports */ 882 if (probe_all == 0) 883 last_port = 2; 884 } 885 886 /* If an OPTI 82C46X is present find out where the channels are */ 887 if (opti82c46x) { 888 static const char *optis[4] = { 889 "3/463MV", "5MV", 890 "5MVA", "5MVB" 891 }; 892 u8 chans = 1; 893 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 894 895 opti82c46x = 3; /* Assume master and slave first */ 896 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]); 897 if (ctrl == 3) 898 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 899 ctrl = opti_syscfg(0xAC); 900 /* Check enabled and this port is the 465MV port. On the 901 MVB we may have two channels */ 902 if (ctrl & 8) { 903 if (ctrl & 4) 904 opti82c46x = 2; /* Slave */ 905 else 906 opti82c46x = 1; /* Master */ 907 if (chans == 2) 908 opti82c46x = 3; /* Master and Slave */ 909 } /* Slave only */ 910 else if (chans == 1) 911 opti82c46x = 1; 912 } 913 914 for (i = 0; i < last_port; i++) { 915 /* Skip primary if we have seen a PCI one */ 916 if (i == 0 && primary == 1) 917 continue; 918 /* Skip secondary if we have seen a PCI one */ 919 if (i == 1 && secondary == 1) 920 continue; 921 if (legacy_init_one(i, legacy_port[i], 922 legacy_port[i] + 0x0206, 923 legacy_irq[i]) == 0) 924 ct++; 925 } 926 if (ct != 0) 927 return 0; 928 return -ENODEV; 929} 930 931static __exit void legacy_exit(void) 932{ 933 int i; 934 935 for (i = 0; i < nr_legacy_host; i++) { 936 struct legacy_data *ld = &legacy_data[i]; 937 938 ata_host_detach(legacy_host[i]); 939 platform_device_unregister(ld->platform_dev); 940 if (ld->timing) 941 release_region(ld->timing, 2); 942 } 943} 944 945MODULE_AUTHOR("Alan Cox"); 946MODULE_DESCRIPTION("low-level driver for legacy ATA"); 947MODULE_LICENSE("GPL"); 948MODULE_VERSION(DRV_VERSION); 949 950module_param(probe_all, int, 0); 951module_param(autospeed, int, 0); 952module_param(ht6560a, int, 0); 953module_param(ht6560b, int, 0); 954module_param(opti82c611a, int, 0); 955module_param(opti82c46x, int, 0); 956module_param(pio_mask, int, 0); 957module_param(iordy_mask, int, 0); 958 959module_init(legacy_init); 960module_exit(legacy_exit); 961