1/* 2 * Intel Multiprocessor Specification 1.1 and 1.4 3 * compliant MP-table parsing routines. 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 7 * 8 * Fixes 9 * Erich Boleyn : MP v1.4 and additional changes. 10 * Alan Cox : Added EBDA scanning 11 * Ingo Molnar : various cleanups and rewrites 12 * Maciej W. Rozycki: Bits for default MP configurations 13 * Paul Diefenbaugh: Added full ACPI support 14 */ 15 16#include <linux/mm.h> 17#include <linux/init.h> 18#include <linux/delay.h> 19#include <linux/bootmem.h> 20#include <linux/kernel_stat.h> 21#include <linux/mc146818rtc.h> 22#include <linux/acpi.h> 23#include <linux/module.h> 24 25#include <asm/smp.h> 26#include <asm/mtrr.h> 27#include <asm/mpspec.h> 28#include <asm/pgalloc.h> 29#include <asm/io_apic.h> 30#include <asm/proto.h> 31#include <asm/acpi.h> 32 33/* Have we found an MP table */ 34int smp_found_config; 35unsigned int __initdata maxcpus = NR_CPUS; 36 37/* 38 * Various Linux-internal data structures created from the 39 * MP-table. 40 */ 41DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 42int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; 43 44static int mp_current_pci_id = 0; 45/* I/O APIC entries */ 46struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; 47 48/* # of MP IRQ source entries */ 49struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; 50 51/* MP IRQ source entries */ 52int mp_irq_entries; 53 54int nr_ioapics; 55unsigned long mp_lapic_addr = 0; 56 57 58 59/* Processor that is doing the boot up */ 60unsigned int boot_cpu_id = -1U; 61/* Internal processor count */ 62unsigned int num_processors __cpuinitdata = 0; 63 64unsigned disabled_cpus __cpuinitdata; 65 66/* Bitmask of physically existing CPUs */ 67physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE; 68 69u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; 70 71 72/* 73 * Intel MP BIOS table parsing routines: 74 */ 75 76/* 77 * Checksum an MP configuration block. 78 */ 79 80static int __init mpf_checksum(unsigned char *mp, int len) 81{ 82 int sum = 0; 83 84 while (len--) 85 sum += *mp++; 86 87 return sum & 0xFF; 88} 89 90static void __cpuinit MP_processor_info (struct mpc_config_processor *m) 91{ 92 int cpu; 93 cpumask_t tmp_map; 94 char *bootup_cpu = ""; 95 96 if (!(m->mpc_cpuflag & CPU_ENABLED)) { 97 disabled_cpus++; 98 return; 99 } 100 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { 101 bootup_cpu = " (Bootup-CPU)"; 102 boot_cpu_id = m->mpc_apicid; 103 } 104 105 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); 106 107 if (num_processors >= NR_CPUS) { 108 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." 109 " Processor ignored.\n", NR_CPUS); 110 return; 111 } 112 113 num_processors++; 114 cpus_complement(tmp_map, cpu_present_map); 115 cpu = first_cpu(tmp_map); 116 117 physid_set(m->mpc_apicid, phys_cpu_present_map); 118 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { 119 /* 120 * bios_cpu_apicid is required to have processors listed 121 * in same order as logical cpu numbers. Hence the first 122 * entry is BSP, and so on. 123 */ 124 cpu = 0; 125 } 126 bios_cpu_apicid[cpu] = m->mpc_apicid; 127 x86_cpu_to_apicid[cpu] = m->mpc_apicid; 128 129 cpu_set(cpu, cpu_possible_map); 130 cpu_set(cpu, cpu_present_map); 131} 132 133static void __init MP_bus_info (struct mpc_config_bus *m) 134{ 135 char str[7]; 136 137 memcpy(str, m->mpc_bustype, 6); 138 str[6] = 0; 139 Dprintk("Bus #%d is %s\n", m->mpc_busid, str); 140 141 if (strncmp(str, "ISA", 3) == 0) { 142 set_bit(m->mpc_busid, mp_bus_not_pci); 143 } else if (strncmp(str, "PCI", 3) == 0) { 144 clear_bit(m->mpc_busid, mp_bus_not_pci); 145 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; 146 mp_current_pci_id++; 147 } else { 148 printk(KERN_ERR "Unknown bustype %s\n", str); 149 } 150} 151 152static int bad_ioapic(unsigned long address) 153{ 154 if (nr_ioapics >= MAX_IO_APICS) { 155 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " 156 "(found %d)\n", MAX_IO_APICS, nr_ioapics); 157 panic("Recompile kernel with bigger MAX_IO_APICS!\n"); 158 } 159 if (!address) { 160 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" 161 " found in table, skipping!\n"); 162 return 1; 163 } 164 return 0; 165} 166 167static void __init MP_ioapic_info (struct mpc_config_ioapic *m) 168{ 169 if (!(m->mpc_flags & MPC_APIC_USABLE)) 170 return; 171 172 printk("I/O APIC #%d at 0x%X.\n", 173 m->mpc_apicid, m->mpc_apicaddr); 174 175 if (bad_ioapic(m->mpc_apicaddr)) 176 return; 177 178 mp_ioapics[nr_ioapics] = *m; 179 nr_ioapics++; 180} 181 182static void __init MP_intsrc_info (struct mpc_config_intsrc *m) 183{ 184 mp_irqs [mp_irq_entries] = *m; 185 Dprintk("Int: type %d, pol %d, trig %d, bus %d," 186 " IRQ %02x, APIC ID %x, APIC INT %02x\n", 187 m->mpc_irqtype, m->mpc_irqflag & 3, 188 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, 189 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); 190 if (++mp_irq_entries >= MAX_IRQ_SOURCES) 191 panic("Max # of irq sources exceeded!!\n"); 192} 193 194static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) 195{ 196 Dprintk("Lint: type %d, pol %d, trig %d, bus %d," 197 " IRQ %02x, APIC ID %x, APIC LINT %02x\n", 198 m->mpc_irqtype, m->mpc_irqflag & 3, 199 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, 200 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); 201} 202 203/* 204 * Read/parse the MPC 205 */ 206 207static int __init smp_read_mpc(struct mp_config_table *mpc) 208{ 209 char str[16]; 210 int count=sizeof(*mpc); 211 unsigned char *mpt=((unsigned char *)mpc)+count; 212 213 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { 214 printk("MPTABLE: bad signature [%c%c%c%c]!\n", 215 mpc->mpc_signature[0], 216 mpc->mpc_signature[1], 217 mpc->mpc_signature[2], 218 mpc->mpc_signature[3]); 219 return 0; 220 } 221 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { 222 printk("MPTABLE: checksum error!\n"); 223 return 0; 224 } 225 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { 226 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", 227 mpc->mpc_spec); 228 return 0; 229 } 230 if (!mpc->mpc_lapic) { 231 printk(KERN_ERR "MPTABLE: null local APIC address!\n"); 232 return 0; 233 } 234 memcpy(str,mpc->mpc_oem,8); 235 str[8] = 0; 236 printk(KERN_INFO "MPTABLE: OEM ID: %s ",str); 237 238 memcpy(str,mpc->mpc_productid,12); 239 str[12] = 0; 240 printk("MPTABLE: Product ID: %s ",str); 241 242 printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic); 243 244 /* save the local APIC address, it might be non-default */ 245 if (!acpi_lapic) 246 mp_lapic_addr = mpc->mpc_lapic; 247 248 /* 249 * Now process the configuration blocks. 250 */ 251 while (count < mpc->mpc_length) { 252 switch(*mpt) { 253 case MP_PROCESSOR: 254 { 255 struct mpc_config_processor *m= 256 (struct mpc_config_processor *)mpt; 257 if (!acpi_lapic) 258 MP_processor_info(m); 259 mpt += sizeof(*m); 260 count += sizeof(*m); 261 break; 262 } 263 case MP_BUS: 264 { 265 struct mpc_config_bus *m= 266 (struct mpc_config_bus *)mpt; 267 MP_bus_info(m); 268 mpt += sizeof(*m); 269 count += sizeof(*m); 270 break; 271 } 272 case MP_IOAPIC: 273 { 274 struct mpc_config_ioapic *m= 275 (struct mpc_config_ioapic *)mpt; 276 MP_ioapic_info(m); 277 mpt += sizeof(*m); 278 count += sizeof(*m); 279 break; 280 } 281 case MP_INTSRC: 282 { 283 struct mpc_config_intsrc *m= 284 (struct mpc_config_intsrc *)mpt; 285 286 MP_intsrc_info(m); 287 mpt += sizeof(*m); 288 count += sizeof(*m); 289 break; 290 } 291 case MP_LINTSRC: 292 { 293 struct mpc_config_lintsrc *m= 294 (struct mpc_config_lintsrc *)mpt; 295 MP_lintsrc_info(m); 296 mpt += sizeof(*m); 297 count += sizeof(*m); 298 break; 299 } 300 } 301 } 302 setup_apic_routing(); 303 if (!num_processors) 304 printk(KERN_ERR "MPTABLE: no processors registered!\n"); 305 return num_processors; 306} 307 308static int __init ELCR_trigger(unsigned int irq) 309{ 310 unsigned int port; 311 312 port = 0x4d0 + (irq >> 3); 313 return (inb(port) >> (irq & 7)) & 1; 314} 315 316static void __init construct_default_ioirq_mptable(int mpc_default_type) 317{ 318 struct mpc_config_intsrc intsrc; 319 int i; 320 int ELCR_fallback = 0; 321 322 intsrc.mpc_type = MP_INTSRC; 323 intsrc.mpc_irqflag = 0; /* conforming */ 324 intsrc.mpc_srcbus = 0; 325 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; 326 327 intsrc.mpc_irqtype = mp_INT; 328 329 /* 330 * If true, we have an ISA/PCI system with no IRQ entries 331 * in the MP table. To prevent the PCI interrupts from being set up 332 * incorrectly, we try to use the ELCR. The sanity check to see if 333 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can 334 * never be level sensitive, so we simply see if the ELCR agrees. 335 * If it does, we assume it's valid. 336 */ 337 if (mpc_default_type == 5) { 338 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); 339 340 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) 341 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n"); 342 else { 343 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); 344 ELCR_fallback = 1; 345 } 346 } 347 348 for (i = 0; i < 16; i++) { 349 switch (mpc_default_type) { 350 case 2: 351 if (i == 0 || i == 13) 352 continue; /* IRQ0 & IRQ13 not connected */ 353 /* fall through */ 354 default: 355 if (i == 2) 356 continue; /* IRQ2 is never connected */ 357 } 358 359 if (ELCR_fallback) { 360 /* 361 * If the ELCR indicates a level-sensitive interrupt, we 362 * copy that information over to the MP table in the 363 * irqflag field (level sensitive, active high polarity). 364 */ 365 if (ELCR_trigger(i)) 366 intsrc.mpc_irqflag = 13; 367 else 368 intsrc.mpc_irqflag = 0; 369 } 370 371 intsrc.mpc_srcbusirq = i; 372 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ 373 MP_intsrc_info(&intsrc); 374 } 375 376 intsrc.mpc_irqtype = mp_ExtINT; 377 intsrc.mpc_srcbusirq = 0; 378 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ 379 MP_intsrc_info(&intsrc); 380} 381 382static inline void __init construct_default_ISA_mptable(int mpc_default_type) 383{ 384 struct mpc_config_processor processor; 385 struct mpc_config_bus bus; 386 struct mpc_config_ioapic ioapic; 387 struct mpc_config_lintsrc lintsrc; 388 int linttypes[2] = { mp_ExtINT, mp_NMI }; 389 int i; 390 391 /* 392 * local APIC has default address 393 */ 394 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 395 396 /* 397 * 2 CPUs, numbered 0 & 1. 398 */ 399 processor.mpc_type = MP_PROCESSOR; 400 processor.mpc_apicver = 0; 401 processor.mpc_cpuflag = CPU_ENABLED; 402 processor.mpc_cpufeature = 0; 403 processor.mpc_featureflag = 0; 404 processor.mpc_reserved[0] = 0; 405 processor.mpc_reserved[1] = 0; 406 for (i = 0; i < 2; i++) { 407 processor.mpc_apicid = i; 408 MP_processor_info(&processor); 409 } 410 411 bus.mpc_type = MP_BUS; 412 bus.mpc_busid = 0; 413 switch (mpc_default_type) { 414 default: 415 printk(KERN_ERR "???\nUnknown standard configuration %d\n", 416 mpc_default_type); 417 /* fall through */ 418 case 1: 419 case 5: 420 memcpy(bus.mpc_bustype, "ISA ", 6); 421 break; 422 } 423 MP_bus_info(&bus); 424 if (mpc_default_type > 4) { 425 bus.mpc_busid = 1; 426 memcpy(bus.mpc_bustype, "PCI ", 6); 427 MP_bus_info(&bus); 428 } 429 430 ioapic.mpc_type = MP_IOAPIC; 431 ioapic.mpc_apicid = 2; 432 ioapic.mpc_apicver = 0; 433 ioapic.mpc_flags = MPC_APIC_USABLE; 434 ioapic.mpc_apicaddr = 0xFEC00000; 435 MP_ioapic_info(&ioapic); 436 437 /* 438 * We set up most of the low 16 IO-APIC pins according to MPS rules. 439 */ 440 construct_default_ioirq_mptable(mpc_default_type); 441 442 lintsrc.mpc_type = MP_LINTSRC; 443 lintsrc.mpc_irqflag = 0; /* conforming */ 444 lintsrc.mpc_srcbusid = 0; 445 lintsrc.mpc_srcbusirq = 0; 446 lintsrc.mpc_destapic = MP_APIC_ALL; 447 for (i = 0; i < 2; i++) { 448 lintsrc.mpc_irqtype = linttypes[i]; 449 lintsrc.mpc_destapiclint = i; 450 MP_lintsrc_info(&lintsrc); 451 } 452} 453 454static struct intel_mp_floating *mpf_found; 455 456/* 457 * Scan the memory blocks for an SMP configuration block. 458 */ 459void __init get_smp_config (void) 460{ 461 struct intel_mp_floating *mpf = mpf_found; 462 463 /* 464 * ACPI supports both logical (e.g. Hyper-Threading) and physical 465 * processors, where MPS only supports physical. 466 */ 467 if (acpi_lapic && acpi_ioapic) { 468 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); 469 return; 470 } 471 else if (acpi_lapic) 472 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); 473 474 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); 475 476 /* 477 * Now see if we need to read further. 478 */ 479 if (mpf->mpf_feature1 != 0) { 480 481 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); 482 construct_default_ISA_mptable(mpf->mpf_feature1); 483 484 } else if (mpf->mpf_physptr) { 485 486 /* 487 * Read the physical hardware table. Anything here will 488 * override the defaults. 489 */ 490 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { 491 smp_found_config = 0; 492 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); 493 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); 494 return; 495 } 496 /* 497 * If there are no explicit MP IRQ entries, then we are 498 * broken. We set up most of the low 16 IO-APIC pins to 499 * ISA defaults and hope it will work. 500 */ 501 if (!mp_irq_entries) { 502 struct mpc_config_bus bus; 503 504 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); 505 506 bus.mpc_type = MP_BUS; 507 bus.mpc_busid = 0; 508 memcpy(bus.mpc_bustype, "ISA ", 6); 509 MP_bus_info(&bus); 510 511 construct_default_ioirq_mptable(0); 512 } 513 514 } else 515 BUG(); 516 517 printk(KERN_INFO "Processors: %d\n", num_processors); 518 /* 519 * Only use the first configuration found. 520 */ 521} 522 523static int __init smp_scan_config (unsigned long base, unsigned long length) 524{ 525 extern void __bad_mpf_size(void); 526 unsigned int *bp = phys_to_virt(base); 527 struct intel_mp_floating *mpf; 528 529 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); 530 if (sizeof(*mpf) != 16) 531 __bad_mpf_size(); 532 533 while (length > 0) { 534 mpf = (struct intel_mp_floating *)bp; 535 if ((*bp == SMP_MAGIC_IDENT) && 536 (mpf->mpf_length == 1) && 537 !mpf_checksum((unsigned char *)bp, 16) && 538 ((mpf->mpf_specification == 1) 539 || (mpf->mpf_specification == 4)) ) { 540 541 smp_found_config = 1; 542 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); 543 if (mpf->mpf_physptr) 544 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE); 545 mpf_found = mpf; 546 return 1; 547 } 548 bp += 4; 549 length -= 16; 550 } 551 return 0; 552} 553 554void __init find_smp_config(void) 555{ 556 unsigned int address; 557 558 if (smp_scan_config(0x0,0x400) || 559 smp_scan_config(639*0x400,0x400) || 560 smp_scan_config(0xF0000,0x10000)) 561 return; 562 /* 563 * If it is an SMP machine we should know now. 564 * 565 * there is a real-mode segmented pointer pointing to the 566 * 4K EBDA area at 0x40E, calculate and scan it here. 567 * 568 * NOTE! There are Linux loaders that will corrupt the EBDA 569 * area, and as such this kind of SMP config may be less 570 * trustworthy, simply because the SMP table may have been 571 * stomped on during early boot. These loaders are buggy and 572 * should be fixed. 573 */ 574 575 address = *(unsigned short *)phys_to_virt(0x40E); 576 address <<= 4; 577 if (smp_scan_config(address, 0x1000)) 578 return; 579 580 /* If we have come this far, we did not find an MP table */ 581 printk(KERN_INFO "No mptable found.\n"); 582} 583 584/* -------------------------------------------------------------------------- 585 ACPI-based MP Configuration 586 -------------------------------------------------------------------------- */ 587 588#ifdef CONFIG_ACPI 589 590void __init mp_register_lapic_address(u64 address) 591{ 592 mp_lapic_addr = (unsigned long) address; 593 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 594 if (boot_cpu_id == -1U) 595 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); 596} 597 598void __cpuinit mp_register_lapic (u8 id, u8 enabled) 599{ 600 struct mpc_config_processor processor; 601 int boot_cpu = 0; 602 603 if (id == boot_cpu_id) 604 boot_cpu = 1; 605 606 processor.mpc_type = MP_PROCESSOR; 607 processor.mpc_apicid = id; 608 processor.mpc_apicver = 0; 609 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); 610 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); 611 processor.mpc_cpufeature = 0; 612 processor.mpc_featureflag = 0; 613 processor.mpc_reserved[0] = 0; 614 processor.mpc_reserved[1] = 0; 615 616 MP_processor_info(&processor); 617} 618 619#define MP_ISA_BUS 0 620#define MP_MAX_IOAPIC_PIN 127 621 622static struct mp_ioapic_routing { 623 int apic_id; 624 int gsi_start; 625 int gsi_end; 626 u32 pin_programmed[4]; 627} mp_ioapic_routing[MAX_IO_APICS]; 628 629static int mp_find_ioapic(int gsi) 630{ 631 int i = 0; 632 633 /* Find the IOAPIC that manages this GSI. */ 634 for (i = 0; i < nr_ioapics; i++) { 635 if ((gsi >= mp_ioapic_routing[i].gsi_start) 636 && (gsi <= mp_ioapic_routing[i].gsi_end)) 637 return i; 638 } 639 640 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); 641 return -1; 642} 643 644void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) 645{ 646 int idx = 0; 647 648 if (bad_ioapic(address)) 649 return; 650 651 idx = nr_ioapics++; 652 653 mp_ioapics[idx].mpc_type = MP_IOAPIC; 654 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; 655 mp_ioapics[idx].mpc_apicaddr = address; 656 657 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); 658 mp_ioapics[idx].mpc_apicid = id; 659 mp_ioapics[idx].mpc_apicver = 0; 660 661 /* 662 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups 663 * and to prevent reprogramming of IOAPIC pins (PCI IRQs). 664 */ 665 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; 666 mp_ioapic_routing[idx].gsi_start = gsi_base; 667 mp_ioapic_routing[idx].gsi_end = gsi_base + 668 io_apic_get_redir_entries(idx); 669 670 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " 671 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 672 mp_ioapics[idx].mpc_apicaddr, 673 mp_ioapic_routing[idx].gsi_start, 674 mp_ioapic_routing[idx].gsi_end); 675} 676 677void __init 678mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) 679{ 680 struct mpc_config_intsrc intsrc; 681 int ioapic = -1; 682 int pin = -1; 683 684 /* 685 * Convert 'gsi' to 'ioapic.pin'. 686 */ 687 ioapic = mp_find_ioapic(gsi); 688 if (ioapic < 0) 689 return; 690 pin = gsi - mp_ioapic_routing[ioapic].gsi_start; 691 692 /* 693 * TBD: This check is for faulty timer entries, where the override 694 * erroneously sets the trigger to level, resulting in a HUGE 695 * increase of timer interrupts! 696 */ 697 if ((bus_irq == 0) && (trigger == 3)) 698 trigger = 1; 699 700 intsrc.mpc_type = MP_INTSRC; 701 intsrc.mpc_irqtype = mp_INT; 702 intsrc.mpc_irqflag = (trigger << 2) | polarity; 703 intsrc.mpc_srcbus = MP_ISA_BUS; 704 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ 705 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ 706 intsrc.mpc_dstirq = pin; /* INTIN# */ 707 708 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", 709 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 710 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 711 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); 712 713 mp_irqs[mp_irq_entries] = intsrc; 714 if (++mp_irq_entries == MAX_IRQ_SOURCES) 715 panic("Max # of irq sources exceeded!\n"); 716} 717 718void __init mp_config_acpi_legacy_irqs(void) 719{ 720 struct mpc_config_intsrc intsrc; 721 int i = 0; 722 int ioapic = -1; 723 724 /* 725 * Fabricate the legacy ISA bus (bus #31). 726 */ 727 set_bit(MP_ISA_BUS, mp_bus_not_pci); 728 729 /* 730 * Locate the IOAPIC that manages the ISA IRQs (0-15). 731 */ 732 ioapic = mp_find_ioapic(0); 733 if (ioapic < 0) 734 return; 735 736 intsrc.mpc_type = MP_INTSRC; 737 intsrc.mpc_irqflag = 0; /* Conforming */ 738 intsrc.mpc_srcbus = MP_ISA_BUS; 739 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; 740 741 /* 742 * Use the default configuration for the IRQs 0-15. Unless 743 * overridden by (MADT) interrupt source override entries. 744 */ 745 for (i = 0; i < 16; i++) { 746 int idx; 747 748 for (idx = 0; idx < mp_irq_entries; idx++) { 749 struct mpc_config_intsrc *irq = mp_irqs + idx; 750 751 /* Do we already have a mapping for this ISA IRQ? */ 752 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) 753 break; 754 755 /* Do we already have a mapping for this IOAPIC pin */ 756 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && 757 (irq->mpc_dstirq == i)) 758 break; 759 } 760 761 if (idx != mp_irq_entries) { 762 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); 763 continue; /* IRQ already used */ 764 } 765 766 intsrc.mpc_irqtype = mp_INT; 767 intsrc.mpc_srcbusirq = i; /* Identity mapped */ 768 intsrc.mpc_dstirq = i; 769 770 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " 771 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 772 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 773 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, 774 intsrc.mpc_dstirq); 775 776 mp_irqs[mp_irq_entries] = intsrc; 777 if (++mp_irq_entries == MAX_IRQ_SOURCES) 778 panic("Max # of irq sources exceeded!\n"); 779 } 780} 781 782int mp_register_gsi(u32 gsi, int triggering, int polarity) 783{ 784 int ioapic = -1; 785 int ioapic_pin = 0; 786 int idx, bit = 0; 787 788 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) 789 return gsi; 790 791 /* Don't set up the ACPI SCI because it's already set up */ 792 if (acpi_gbl_FADT.sci_interrupt == gsi) 793 return gsi; 794 795 ioapic = mp_find_ioapic(gsi); 796 if (ioapic < 0) { 797 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); 798 return gsi; 799 } 800 801 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start; 802 803 /* 804 * Avoid pin reprogramming. PRTs typically include entries 805 * with redundant pin->gsi mappings (but unique PCI devices); 806 * we only program the IOAPIC on the first. 807 */ 808 bit = ioapic_pin % 32; 809 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); 810 if (idx > 3) { 811 printk(KERN_ERR "Invalid reference to IOAPIC pin " 812 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, 813 ioapic_pin); 814 return gsi; 815 } 816 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { 817 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", 818 mp_ioapic_routing[ioapic].apic_id, ioapic_pin); 819 return gsi; 820 } 821 822 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); 823 824 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, 825 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, 826 polarity == ACPI_ACTIVE_HIGH ? 0 : 1); 827 return gsi; 828} 829#endif /*CONFIG_ACPI*/ 830