1/*
2 * arch/sh/mm/tlb-sh3.c
3 *
4 * SH-3 specific TLB operations
5 *
6 * Copyright (C) 1999  Niibe Yutaka
7 * Copyright (C) 2002  Paul Mundt
8 *
9 * Released under the terms of the GNU GPL v2.0.
10 */
11#include <linux/signal.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/string.h>
16#include <linux/types.h>
17#include <linux/ptrace.h>
18#include <linux/mman.h>
19#include <linux/mm.h>
20#include <linux/smp.h>
21#include <linux/smp_lock.h>
22#include <linux/interrupt.h>
23
24#include <asm/system.h>
25#include <asm/io.h>
26#include <asm/uaccess.h>
27#include <asm/pgalloc.h>
28#include <asm/mmu_context.h>
29#include <asm/cacheflush.h>
30
31void update_mmu_cache(struct vm_area_struct * vma,
32		      unsigned long address, pte_t pte)
33{
34	unsigned long flags;
35	unsigned long pteval;
36	unsigned long vpn;
37
38	/* Ptrace may call this routine. */
39	if (vma && current->active_mm != vma->vm_mm)
40		return;
41
42#if defined(CONFIG_SH7705_CACHE_32KB)
43	{
44		struct page *page = pte_page(pte);
45		unsigned long pfn = pte_pfn(pte);
46
47		if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) {
48			unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
49
50			__flush_wback_region((void *)P1SEGADDR(phys),
51					     PAGE_SIZE);
52			__set_bit(PG_mapped, &page->flags);
53		}
54	}
55#endif
56
57	local_irq_save(flags);
58
59	/* Set PTEH register */
60	vpn = (address & MMU_VPN_MASK) | get_asid();
61	ctrl_outl(vpn, MMU_PTEH);
62
63	pteval = pte_val(pte);
64
65	/* Set PTEL register */
66	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
67	/* conveniently, we want all the software flags to be 0 anyway */
68	ctrl_outl(pteval, MMU_PTEL);
69
70	/* Load the TLB */
71	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
72	local_irq_restore(flags);
73}
74
75void local_flush_tlb_one(unsigned long asid, unsigned long page)
76{
77	unsigned long addr, data;
78	int i, ways = MMU_NTLB_WAYS;
79
80	/*
81	 * NOTE: PTEH.ASID should be set to this MM
82	 *       _AND_ we need to write ASID to the array.
83	 *
84	 * It would be simple if we didn't need to set PTEH.ASID...
85	 */
86	addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
87	data = (page & 0xfffe0000) | asid; /* VALID bit is off */
88
89	if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
90		addr |= MMU_PAGE_ASSOC_BIT;
91		ways = 1;	/* we already know the way .. */
92	}
93
94	for (i = 0; i < ways; i++)
95		ctrl_outl(data, addr + (i << 8));
96}
97