1/* 2 * SH7710 Setup 3 * 4 * Copyright (C) 2006 Paul Mundt 5 * Copyright (C) 2007 Nobuhiro Iwamatsu 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11#include <linux/platform_device.h> 12#include <linux/init.h> 13#include <linux/serial.h> 14#include <asm/sci.h> 15 16static struct plat_sci_port sci_platform_data[] = { 17 { 18 .mapbase = 0xa4400000, 19 .flags = UPF_BOOT_AUTOCONF, 20 .type = PORT_SCIF, 21 .irqs = { 52, 53, 55, 54 }, 22 }, { 23 .mapbase = 0xa4420000, 24 .flags = UPF_BOOT_AUTOCONF, 25 .type = PORT_SCIF, 26 .irqs = { 56, 57, 59, 58 }, 27 }, { 28 29 .flags = 0, 30 } 31}; 32 33static struct platform_device sci_device = { 34 .name = "sh-sci", 35 .id = -1, 36 .dev = { 37 .platform_data = sci_platform_data, 38 }, 39}; 40 41static struct platform_device *sh7710_devices[] __initdata = { 42 &sci_device, 43}; 44 45static int __init sh7710_devices_setup(void) 46{ 47 return platform_add_devices(sh7710_devices, 48 ARRAY_SIZE(sh7710_devices)); 49} 50__initcall(sh7710_devices_setup); 51 52static struct ipr_data sh7710_ipr_map[] = { 53 /* IRQ, IPR-idx, shift, priority */ 54 { 16, 0, 12, 2 }, /* TMU0 TUNI*/ 55 { 17, 0, 8, 2 }, /* TMU1 TUNI */ 56 { 18, 0, 4, 2 }, /* TMU2 TUNI */ 57 { 27, 1, 12, 2 }, /* WDT ITI */ 58 { 20, 0, 0, 2 }, /* RTC ATI (alarm) */ 59 { 21, 0, 0, 2 }, /* RTC PRI (period) */ 60 { 22, 0, 0, 2 }, /* RTC CUI (carry) */ 61 { 48, 4, 12, 7 }, /* DMAC DMTE0 */ 62 { 49, 4, 12, 7 }, /* DMAC DMTE1 */ 63 { 50, 4, 12, 7 }, /* DMAC DMTE2 */ 64 { 51, 4, 12, 7 }, /* DMAC DMTE3 */ 65 { 52, 4, 8, 3 }, /* SCIF0 ERI */ 66 { 53, 4, 8, 3 }, /* SCIF0 RXI */ 67 { 54, 4, 8, 3 }, /* SCIF0 BRI */ 68 { 55, 4, 8, 3 }, /* SCIF0 TXI */ 69 { 56, 4, 4, 3 }, /* SCIF1 ERI */ 70 { 57, 4, 4, 3 }, /* SCIF1 RXI */ 71 { 58, 4, 4, 3 }, /* SCIF1 BRI */ 72 { 59, 4, 4, 3 }, /* SCIF1 TXI */ 73 { 76, 5, 8, 7 }, /* DMAC DMTE4 */ 74 { 77, 5, 8, 7 }, /* DMAC DMTE5 */ 75 { 80, 6, 12, 5 }, /* EDMAC EINT0 */ 76 { 81, 6, 8, 5 }, /* EDMAC EINT1 */ 77 { 82, 6, 4, 5 }, /* EDMAC EINT2 */ 78}; 79 80static unsigned long ipr_offsets[] = { 81 0xA414FEE2 /* 0: IPRA */ 82, 0xA414FEE4 /* 1: IPRB */ 83, 0xA4140016 /* 2: IPRC */ 84, 0xA4140018 /* 3: IPRD */ 85, 0xA414001A /* 4: IPRE */ 86, 0xA4080000 /* 5: IPRF */ 87, 0xA4080002 /* 6: IPRG */ 88, 0xA4080004 /* 7: IPRH */ 89, 0xA4080006 /* 8: IPRI */ 90}; 91 92/* given the IPR index return the address of the IPR register */ 93unsigned int map_ipridx_to_addr(int idx) 94{ 95 if (idx >= ARRAY_SIZE(ipr_offsets)) 96 return 0; 97 return ipr_offsets[idx]; 98} 99 100void __init init_IRQ_ipr() 101{ 102 make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map)); 103} 104