1/* 2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) 3 * 4 * May be copied or modified under the terms of the GNU General Public 5 * License. See linux/COPYING for more information. 6 * 7 * Definitions for the ST40 PCI hardware. 8 */ 9 10#ifndef __PCI_ST40_H__ 11#define __PCI_ST40_H__ 12 13#define ST40PCI_VCR_STATUS 0x00 14 15#define ST40PCI_VCR_VERSION 0x08 16 17#define ST40PCI_CR 0x10 18 19#define CR_SOFT_RESET (1<<12) 20#define CR_PFCS (1<<11) 21#define CR_PFE (1<<9) 22#define CR_BMAM (1<<6) 23#define CR_HOST (1<<5) 24#define CR_CLKEN (1<<4) 25#define CR_SOCS (1<<3) 26#define CR_IOCS (1<<2) 27#define CR_RSTCTL (1<<1) 28#define CR_CFINT (1<<0) 29#define CR_LOCK_MASK 0x5a000000 30 31 32#define ST40PCI_LSR0 0X14 33#define ST40PCI_LAR0 0x1c 34 35#define ST40PCI_INT 0x24 36#define INT_MNLTDIM (1<<15) 37#define INT_TTADI (1<<14) 38#define INT_TMTO (1<<9) 39#define INT_MDEI (1<<8) 40#define INT_APEDI (1<<7) 41#define INT_SDI (1<<6) 42#define INT_DPEITW (1<<5) 43#define INT_PEDITR (1<<4) 44#define INT_TADIM (1<<3) 45#define INT_MADIM (1<<2) 46#define INT_MWPDI (1<<1) 47#define INT_MRDPEI (1<<0) 48 49 50#define ST40PCI_INTM 0x28 51#define ST40PCI_AIR 0x2c 52 53#define ST40PCI_CIR 0x30 54#define CIR_PIOTEM (1<<31) 55#define CIR_RWTET (1<<26) 56 57#define ST40PCI_AINT 0x40 58#define AINT_MBI (1<<13) 59#define AINT_TBTOI (1<<12) 60#define AINT_MBTOI (1<<11) 61#define AINT_TAI (1<<3) 62#define AINT_MAI (1<<2) 63#define AINT_RDPEI (1<<1) 64#define AINT_WDPE (1<<0) 65 66#define ST40PCI_AINTM 0x44 67#define ST40PCI_BMIR 0x48 68#define ST40PCI_PAR 0x4c 69#define ST40PCI_MBR 0x50 70#define ST40PCI_IOBR 0x54 71#define ST40PCI_PINT 0x58 72#define ST40PCI_PINTM 0x5c 73#define ST40PCI_MBMR 0x70 74#define ST40PCI_IOBMR 0x74 75#define ST40PCI_PDR 0x78 76 77/* H8 specific registers start here */ 78#define ST40PCI_WCBAR 0x7c 79#define ST40PCI_LOCCFG_UNLOCK 0x34 80 81#define ST40PCI_RBAR0 0x100 82#define ST40PCI_RSR0 0x104 83#define ST40PCI_RLAR0 0x108 84 85#define ST40PCI_RBAR1 0x110 86#define ST40PCI_RSR1 0x114 87#define ST40PCI_RLAR1 0x118 88 89 90#define ST40PCI_RBAR2 0x120 91#define ST40PCI_RSR2 0x124 92#define ST40PCI_RLAR2 0x128 93 94#define ST40PCI_RBAR3 0x130 95#define ST40PCI_RSR3 0x134 96#define ST40PCI_RLAR3 0x138 97 98#define ST40PCI_RBAR4 0x140 99#define ST40PCI_RSR4 0x144 100#define ST40PCI_RLAR4 0x148 101 102#define ST40PCI_RBAR5 0x150 103#define ST40PCI_RSR5 0x154 104#define ST40PCI_RLAR5 0x158 105 106#define ST40PCI_RBAR6 0x160 107#define ST40PCI_RSR6 0x164 108#define ST40PCI_RLAR6 0x168 109 110#define ST40PCI_RBAR7 0x170 111#define ST40PCI_RSR7 0x174 112#define ST40PCI_RLAR7 0x178 113 114 115#define ST40PCI_RBAR(n) (0x100+(0x10*(n))) 116#define ST40PCI_RSR(n) (0x104+(0x10*(n))) 117#define ST40PCI_RLAR(n) (0x108+(0x10*(n))) 118 119#define ST40PCI_PERF 0x80 120#define PERF_MASTER_WRITE_POSTING (1<<4) 121/* H8 specific registers end here */ 122 123 124/* These are configs space registers */ 125#define ST40PCI_CSR_VID 0x10000 126#define ST40PCI_CSR_DID 0x10002 127#define ST40PCI_CSR_CMD 0x10004 128#define ST40PCI_CSR_STATUS 0x10006 129#define ST40PCI_CSR_MBAR0 0x10010 130#define ST40PCI_CSR_TRDY 0x10040 131#define ST40PCI_CSR_RETRY 0x10041 132#define ST40PCI_CSR_MIT 0x1000d 133 134#define ST40_IO_ADDR 0xb6000000 135 136#endif /* __PCI_ST40_H__ */ 137