1/* 2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) 3 * 4 * May be copied or modified under the terms of the GNU General Public 5 * License. See linux/COPYING for more information. 6 * 7 * Support functions for the ST40 PCI hardware. 8 */ 9 10#include <linux/kernel.h> 11#include <linux/smp.h> 12#include <linux/init.h> 13#include <linux/errno.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/types.h> 17#include <asm/pci.h> 18#include <linux/irq.h> 19#include <linux/interrupt.h> /* irqreturn_t */ 20 21#include "pci-st40.h" 22 23/* This is in P2 of course */ 24#define ST40PCI_BASE_ADDRESS (0xb0000000) 25#define ST40PCI_MEM_ADDRESS (ST40PCI_BASE_ADDRESS+0x0) 26#define ST40PCI_IO_ADDRESS (ST40PCI_BASE_ADDRESS+0x06000000) 27#define ST40PCI_REG_ADDRESS (ST40PCI_BASE_ADDRESS+0x07000000) 28 29#define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x)) 30#define ST40PCI_REG_INDEXED(reg, index) \ 31 (ST40PCI_REG(reg##0) + \ 32 ((ST40PCI_REG(reg##1) - ST40PCI_REG(reg##0))*index)) 33 34#define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg)) 35#define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg)) 36#define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg)) 37#define ST40PCI_WRITE_INDEXED(reg, index, val) \ 38 writel((val), ST40PCI_REG_INDEXED(reg, index)); 39 40#define ST40PCI_READ(reg) readl(ST40PCI_REG(reg)) 41#define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg)) 42#define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg)) 43 44#define ST40PCI_SERR_IRQ 64 45#define ST40PCI_ERR_IRQ 65 46 47 48/* Macros to extract PLL params */ 49#define PLL_MDIV(reg) ( ((unsigned)reg) & 0xff ) 50#define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff ) 51#define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 ) 52#define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff ) 53 54/* Build up the appropriate settings */ 55#define PLL_SET(mdiv,ndiv,pdiv,setup) \ 56( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19)) 57 58#define PLLPCICR (0xbb040000+0x10) 59 60#define PLLPCICR_POWERON (1<<28) 61#define PLLPCICR_OUT_EN (1<<29) 62#define PLLPCICR_LOCKSELECT (1<<30) 63#define PLLPCICR_LOCK (1<<31) 64 65 66#define PLL_25MHZ 0x793c8512 67#define PLL_33MHZ PLL_SET(18,88,3,295) 68 69static void pci_set_rbar_region(unsigned int region, unsigned long localAddr, 70 unsigned long pciOffset, unsigned long regionSize); 71 72static __init void SetPCIPLL(void) 73{ 74 { 75 /* Lets play with the PLL values */ 76 unsigned long pll1cr1; 77 unsigned long mdiv, ndiv, pdiv; 78 unsigned long muxcr; 79 unsigned int muxcr_ratios[4] = { 8, 16, 21, 1 }; 80 unsigned int freq; 81 82#define CLKGENA 0xbb040000 83#define CLKGENA_PLL2_MUXCR CLKGENA + 0x48 84 pll1cr1 = ctrl_inl(PLLPCICR); 85 printk("PLL1CR1 %08lx\n", pll1cr1); 86 mdiv = PLL_MDIV(pll1cr1); 87 ndiv = PLL_NDIV(pll1cr1); 88 pdiv = PLL_PDIV(pll1cr1); 89 printk("mdiv %02lx ndiv %02lx pdiv %02lx\n", mdiv, ndiv, pdiv); 90 freq = ((2*27*ndiv)/mdiv) / (1 << pdiv); 91 printk("PLL freq %dMHz\n", freq); 92 muxcr = ctrl_inl(CLKGENA_PLL2_MUXCR); 93 printk("PCI freq %dMhz\n", freq / muxcr_ratios[muxcr & 3]); 94 } 95} 96 97 98struct pci_err { 99 unsigned mask; 100 const char *error_string; 101}; 102 103static struct pci_err int_error[]={ 104 { INT_MNLTDIM,"MNLTDIM: Master non-lock transfer"}, 105 { INT_TTADI, "TTADI: Illegal byte enable in I/O transfer"}, 106 { INT_TMTO, "TMTO: Target memory read/write timeout"}, 107 { INT_MDEI, "MDEI: Master function disable error"}, 108 { INT_APEDI, "APEDI: Address parity error"}, 109 { INT_SDI, "SDI: SERR detected"}, 110 { INT_DPEITW, "DPEITW: Data parity error target write"}, 111 { INT_PEDITR, "PEDITR: PERR detected"}, 112 { INT_TADIM, "TADIM: Target abort detected"}, 113 { INT_MADIM, "MADIM: Master abort detected"}, 114 { INT_MWPDI, "MWPDI: PERR from target at data write"}, 115 { INT_MRDPEI, "MRDPEI: Master read data parity error"} 116}; 117#define NUM_PCI_INT_ERRS (sizeof(int_error)/sizeof(struct pci_err)) 118 119static struct pci_err aint_error[]={ 120 { AINT_MBI, "MBI: Master broken"}, 121 { AINT_TBTOI, "TBTOI: Target bus timeout"}, 122 { AINT_MBTOI, "MBTOI: Master bus timeout"}, 123 { AINT_TAI, "TAI: Target abort"}, 124 { AINT_MAI, "MAI: Master abort"}, 125 { AINT_RDPEI, "RDPEI: Read data parity"}, 126 { AINT_WDPE, "WDPE: Write data parity"} 127}; 128 129#define NUM_PCI_AINT_ERRS (sizeof(aint_error)/sizeof(struct pci_err)) 130 131static void print_pci_errors(unsigned reg,struct pci_err *error,int num_errors) 132{ 133 int i; 134 135 for(i=0;i<num_errors;i++) { 136 if(reg & error[i].mask) { 137 printk("%s\n",error[i].error_string); 138 } 139 } 140 141} 142 143 144static char * pci_commands[16]={ 145 "Int Ack", 146 "Special Cycle", 147 "I/O Read", 148 "I/O Write", 149 "Reserved", 150 "Reserved", 151 "Memory Read", 152 "Memory Write", 153 "Reserved", 154 "Reserved", 155 "Configuration Read", 156 "Configuration Write", 157 "Memory Read Multiple", 158 "Dual Address Cycle", 159 "Memory Read Line", 160 "Memory Write-and-Invalidate" 161}; 162 163static irqreturn_t st40_pci_irq(int irq, void *dev_instance) 164{ 165 unsigned pci_int, pci_air, pci_cir, pci_aint; 166 static int count=0; 167 168 169 pci_int = ST40PCI_READ(INT);pci_aint = ST40PCI_READ(AINT); 170 pci_cir = ST40PCI_READ(CIR);pci_air = ST40PCI_READ(AIR); 171 172 /* Reset state to stop multiple interrupts */ 173 ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0); 174 175 176 if(++count>1) return IRQ_HANDLED; 177 178 printk("** PCI ERROR **\n"); 179 180 if(pci_int) { 181 printk("** INT register status\n"); 182 print_pci_errors(pci_int,int_error,NUM_PCI_INT_ERRS); 183 } 184 185 if(pci_aint) { 186 printk("** AINT register status\n"); 187 print_pci_errors(pci_aint,aint_error,NUM_PCI_AINT_ERRS); 188 } 189 190 printk("** Address and command info\n"); 191 192 printk("** Command %s : Address 0x%x\n", 193 pci_commands[pci_cir&0xf],pci_air); 194 195 if(pci_cir&CIR_PIOTEM) { 196 printk("CIR_PIOTEM:PIO transfer error for master\n"); 197 } 198 if(pci_cir&CIR_RWTET) { 199 printk("CIR_RWTET:Read/Write transfer error for target\n"); 200 } 201 202 return IRQ_HANDLED; 203} 204 205 206/* Rounds a number UP to the nearest power of two. Used for 207 * sizing the PCI window. 208 */ 209static u32 r2p2(u32 num) 210{ 211 int i = 31; 212 u32 tmp = num; 213 214 if (num == 0) 215 return 0; 216 217 do { 218 if (tmp & (1 << 31)) 219 break; 220 i--; 221 tmp <<= 1; 222 } while (i >= 0); 223 224 tmp = 1 << i; 225 /* If the original number isn't a power of 2, round it up */ 226 if (tmp != num) 227 tmp <<= 1; 228 229 return tmp; 230} 231 232static void __init pci_fixup_ide_bases(struct pci_dev *d) 233{ 234 int i; 235 236 /* 237 * PCI IDE controllers use non-standard I/O port decoding, respect it. 238 */ 239 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) 240 return; 241 printk("PCI: IDE base address fixup for %s\n", pci_name(d)); 242 for(i=0; i<4; i++) { 243 struct resource *r = &d->resource[i]; 244 if ((r->start & ~0x80) == 0x374) { 245 r->start |= 2; 246 r->end = r->start; 247 } 248 } 249} 250DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 251 252int __init st40pci_init(unsigned memStart, unsigned memSize) 253{ 254 u32 lsr0; 255 256 SetPCIPLL(); 257 258 /* Initialises the ST40 pci subsystem, performing a reset, then programming 259 * up the address space decoders appropriately 260 */ 261 262 /* Should reset core here as well methink */ 263 264 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET); 265 266 /* Loop while core resets */ 267 while (ST40PCI_READ(CR) & CR_SOFT_RESET); 268 269 /* Switch off interrupts */ 270 ST40PCI_WRITE(INTM, 0); 271 ST40PCI_WRITE(AINT, 0); 272 273 /* Now, lets reset all the cards on the bus with extreme prejudice */ 274 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL); 275 udelay(250); 276 277 /* Set bus active, take it out of reset */ 278 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_BMAM | CR_CFINT | CR_PFCS | CR_PFE); 279 280 /* The PCI spec says that no access must be made to the bus until 1 second 281 * after reset. This seem ludicrously long, but some delay is needed here 282 */ 283 mdelay(1000); 284 285 /* Switch off interrupts */ 286 ST40PCI_WRITE(INTM, 0); 287 ST40PCI_WRITE(AINT, 0); 288 289 /* Allow it to be a master */ 290 291 ST40PCI_WRITE_SHORT(CSR_CMD, 292 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 293 PCI_COMMAND_IO); 294 295 /* Access to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000 296 * on the PCI bus. This allows a nice 1-1 bus to phys mapping. 297 */ 298 299 300 ST40PCI_WRITE(MBR, 0x10000000); 301 /* Always set the max size 128M (actually, it is only 96MB wide) */ 302 ST40PCI_WRITE(MBMR, 0x07ff0000); 303 304 /* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to 305 * allow cards that have legacy io such as vga to function correctly. This gives a 306 * maximum of 64K of io/space as only the bottom 16 bits of the address are copied 307 * over to the bus when the transaction is made. 64K of io space is more than enough 308 */ 309 ST40PCI_WRITE(IOBR, 0x0); 310 /* Set up the 64K window */ 311 ST40PCI_WRITE(IOBMR, 0x0); 312 313 /* Now we set up the mbars so the PCI bus can see the local memory */ 314 /* Expose a 256M window starting at PCI address 0... */ 315 ST40PCI_WRITE(CSR_MBAR0, 0); 316 ST40PCI_WRITE(LSR0, 0x0fff0001); 317 318 /* ... and set up the initial incoming window to expose all of RAM */ 319 pci_set_rbar_region(7, memStart, memStart, memSize); 320 321 /* Maximise timeout values */ 322 ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff); 323 ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff); 324 ST40PCI_WRITE_BYTE(CSR_MIT, 0xff); 325 326 ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING); 327 328 return 1; 329} 330 331char * __init pcibios_setup(char *str) 332{ 333 return str; 334} 335 336 337#define SET_CONFIG_BITS(bus,devfn,where)\ 338 (((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0)) 339 340#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where) 341 342 343static int CheckForMasterAbort(void) 344{ 345 if (ST40PCI_READ(INT) & INT_MADIM) { 346 /* Should we clear config space version as well ??? */ 347 ST40PCI_WRITE(INT, INT_MADIM); 348 ST40PCI_WRITE_SHORT(CSR_STATUS, 0); 349 return 1; 350 } 351 352 return 0; 353} 354 355/* Write to config register */ 356static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) 357{ 358 ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); 359 switch (size) { 360 case 1: 361 *val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3)); 362 break; 363 case 2: 364 *val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2)); 365 break; 366 case 4: 367 *val = ST40PCI_READ(PDR); 368 break; 369 } 370 371 if (CheckForMasterAbort()){ 372 switch (size) { 373 case 1: 374 *val = (u8)0xff; 375 break; 376 case 2: 377 *val = (u16)0xffff; 378 break; 379 case 4: 380 *val = 0xffffffff; 381 break; 382 } 383 } 384 385 return PCIBIOS_SUCCESSFUL; 386} 387 388static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) 389{ 390 ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); 391 392 switch (size) { 393 case 1: 394 ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val); 395 break; 396 case 2: 397 ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val); 398 break; 399 case 4: 400 ST40PCI_WRITE(PDR, val); 401 break; 402 } 403 404 CheckForMasterAbort(); 405 406 return PCIBIOS_SUCCESSFUL; 407} 408 409struct pci_ops st40pci_config_ops = { 410 .read = st40pci_read, 411 .write = st40pci_write, 412}; 413 414 415/* Everything hangs off this */ 416static struct pci_bus *pci_root_bus; 417 418static int __init pcibios_init(void) 419{ 420 extern unsigned long memory_start, memory_end; 421 422 printk(KERN_ALERT "pci-st40.c: pcibios_init\n"); 423 424 if (sh_mv.mv_init_pci != NULL) { 425 sh_mv.mv_init_pci(); 426 } 427 428 /* The pci subsytem needs to know where memory is and how much 429 * of it there is. I've simply made these globals. A better mechanism 430 * is probably needed. 431 */ 432 st40pci_init(PHYSADDR(memory_start), 433 PHYSADDR(memory_end) - PHYSADDR(memory_start)); 434 435 if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq, 436 IRQF_DISABLED, "st40pci", NULL)) { 437 printk(KERN_ERR "st40pci: Cannot hook interrupt\n"); 438 return -EIO; 439 } 440 441 /* Enable the PCI interrupts on the device */ 442 ST40PCI_WRITE(INTM, ~0); 443 ST40PCI_WRITE(AINT, ~0); 444 445 /* Map the io address apprioately */ 446#ifdef CONFIG_HD64465 447 hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1, 448 ST40_IO_ADDR + PCIBIOS_MIN_IO, 0); 449#endif 450 451 /* ok, do the scan man */ 452 pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL); 453 pci_assign_unassigned_resources(); 454 455 return 0; 456} 457subsys_initcall(pcibios_init); 458 459/* 460 * Publish a region of local address space over the PCI bus 461 * to other devices. 462 */ 463static void pci_set_rbar_region(unsigned int region, unsigned long localAddr, 464 unsigned long pciOffset, unsigned long regionSize) 465{ 466 unsigned long mask; 467 468 if (region > 7) 469 return; 470 471 if (regionSize > (512 * 1024 * 1024)) 472 return; 473 474 mask = r2p2(regionSize) - 0x10000; 475 476 /* Disable the region (in case currently in use, should never happen) */ 477 ST40PCI_WRITE_INDEXED(RSR, region, 0); 478 479 /* Start of local address space to publish */ 480 ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) ); 481 482 /* Start of region in PCI address space as an offset from MBAR0 */ 483 ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset); 484 485 /* Size of region */ 486 ST40PCI_WRITE_INDEXED(RSR, region, mask | 1); 487} 488