1/*
2 * arch/sh/boards/dreamcast/irq.c
3 *
4 * Holly IRQ support for the Sega Dreamcast.
5 *
6 * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
7 *
8 * This file is part of the LinuxDC project (www.linuxdc.org)
9 * Released under the terms of the GNU GPL v2.0
10 */
11
12#include <linux/irq.h>
13#include <asm/io.h>
14#include <asm/irq.h>
15#include <asm/dreamcast/sysasic.h>
16
17/* Dreamcast System ASIC Hardware Events -
18
19   The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
20   hardware events from system peripherals and triggering an SH7750 IRQ.
21   Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
22   set in the Event Mask Registers (EMRs).  When a hardware event is
23   triggered, it's corresponding bit in the Event Status Registers (ESRs)
24   is set, and that bit should be rewritten to the ESR to acknowledge that
25   event.
26
27   There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908.  Event
28   types can be found in include/asm-sh/dreamcast/sysasic.h. There are three
29   groups of EMRs that parallel the ESRs.  Each EMR group corresponds to an
30   IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928
31   triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
32
33   In the kernel, these events are mapped to virtual IRQs so that drivers can
34   respond to them as they would a normal interrupt.  In order to keep this
35   mapping simple, the events are mapped as:
36
37   6900/6910 - Events  0-31, IRQ 13
38   6904/6924 - Events 32-63, IRQ 11
39   6908/6938 - Events 64-95, IRQ  9
40
41*/
42
43#define ESR_BASE 0x005f6900    /* Base event status register */
44#define EMR_BASE 0x005f6910    /* Base event mask register */
45
46/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
47   1 = 0x6920, 2 = 0x6930; also determine the event offset */
48#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
49
50/* Return the hardware event's bit positon within the EMR/ESR */
51#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
52
53/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ
54   (logically mapped to the corresponding bit for the hardware event). */
55
56/* Disable the hardware event by masking its bit in its EMR */
57static inline void disable_systemasic_irq(unsigned int irq)
58{
59        __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
60        __u32 mask;
61
62        mask = inl(emr);
63        mask &= ~(1 << EVENT_BIT(irq));
64        outl(mask, emr);
65}
66
67/* Enable the hardware event by setting its bit in its EMR */
68static inline void enable_systemasic_irq(unsigned int irq)
69{
70        __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
71        __u32 mask;
72
73        mask = inl(emr);
74        mask |= (1 << EVENT_BIT(irq));
75        outl(mask, emr);
76}
77
78/* Acknowledge a hardware event by writing its bit back to its ESR */
79static void ack_systemasic_irq(unsigned int irq)
80{
81        __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
82        disable_systemasic_irq(irq);
83        outl((1 << EVENT_BIT(irq)), esr);
84}
85
86/* After a IRQ has been ack'd and responded to, it needs to be renabled */
87static void end_systemasic_irq(unsigned int irq)
88{
89        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
90                enable_systemasic_irq(irq);
91}
92
93static unsigned int startup_systemasic_irq(unsigned int irq)
94{
95        enable_systemasic_irq(irq);
96
97        return 0;
98}
99
100static void shutdown_systemasic_irq(unsigned int irq)
101{
102        disable_systemasic_irq(irq);
103}
104
105struct hw_interrupt_type systemasic_int = {
106        .typename       = "System ASIC",
107        .startup        = startup_systemasic_irq,
108        .shutdown       = shutdown_systemasic_irq,
109        .enable         = enable_systemasic_irq,
110        .disable        = disable_systemasic_irq,
111        .ack            = ack_systemasic_irq,
112        .end            = end_systemasic_irq,
113};
114
115/*
116 * Map the hardware event indicated by the processor IRQ to a virtual IRQ.
117 */
118int systemasic_irq_demux(int irq)
119{
120        __u32 emr, esr, status, level;
121        __u32 j, bit;
122
123        switch (irq) {
124                case 13:
125                        level = 0;
126                        break;
127                case 11:
128                        level = 1;
129                        break;
130                case  9:
131                        level = 2;
132                        break;
133                default:
134                        return irq;
135        }
136        emr = EMR_BASE + (level << 4) + (level << 2);
137        esr = ESR_BASE + (level << 2);
138
139        /* Mask the ESR to filter any spurious, unwanted interrtupts */
140        status = inl(esr);
141        status &= inl(emr);
142
143        /* Now scan and find the first set bit as the event to map */
144        for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
145                if (status & bit) {
146                        irq = HW_EVENT_IRQ_BASE + j + (level << 5);
147                        return irq;
148                }
149        }
150
151        /* Not reached */
152        return irq;
153}
154