1/*
2 * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
3 * Real Time Clocks/Timekeepers.
4 *
5 * Author: Mark A. Greer
6 *         mgreer@mvista.com
7 *
8 * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
9 * the terms of the GNU General Public License version 2.  This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#include <linux/errno.h>
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/time.h>
17#include <linux/timex.h>
18#include <linux/bcd.h>
19#include <linux/mc146818rtc.h>
20
21#include <asm/machdep.h>
22#include <asm/io.h>
23#include <asm/time.h>
24#include <asm/todc.h>
25
26/*
27 * Depending on the hardware on your board and your board design, the
28 * RTC/NVRAM may be accessed either directly (like normal memory) or via
29 * address/data registers.  If your board uses the direct method, set
30 * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
31 * 'nvram_as1' NULL.  If your board uses address/data regs to access nvram,
32 * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
33 * address of the upper byte (leave NULL if using mc146818), and set
34 * 'nvram_data' to the address of the 8-bit data register.
35 *
36 * In order to break the assumption that the RTC and NVRAM are accessed by
37 * the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and
38 * 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val'
39 * and 'ppc_md.rtc_write_val' will be used.
40 *
41 * Note: Even though the documentation for the various RTC chips say that it
42 * 	 take up to a second before it starts updating once the 'R' bit is
43 * 	 cleared, they always seem to update even though we bang on it many
44 * 	 times a second.  This is true, except for the Dallas Semi 1746/1747
45 * 	 (possibly others).  Those chips seem to have a real problem whenever
46 * 	 we set the 'R' bit before reading them, they basically stop counting.
47 * 	 					--MAG
48 */
49
50/*
51 * 'todc_info' should be initialized in your *_setup.c file to
52 * point to a fully initialized 'todc_info_t' structure.
53 * This structure holds all the register offsets for your particular
54 * TODC/RTC chip.
55 * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
56 */
57
58#ifdef	RTC_FREQ_SELECT
59#undef	RTC_FREQ_SELECT
60#define	RTC_FREQ_SELECT		control_b	/* Register A */
61#endif
62
63#ifdef	RTC_CONTROL
64#undef	RTC_CONTROL
65#define	RTC_CONTROL		control_a	/* Register B */
66#endif
67
68#ifdef	RTC_INTR_FLAGS
69#undef	RTC_INTR_FLAGS
70#define	RTC_INTR_FLAGS		watchdog	/* Register C */
71#endif
72
73#ifdef	RTC_VALID
74#undef	RTC_VALID
75#define	RTC_VALID		interrupts	/* Register D */
76#endif
77
78/* Access routines when RTC accessed directly (like normal memory) */
79u_char
80todc_direct_read_val(int addr)
81{
82	return readb((void __iomem *)(todc_info->nvram_data + addr));
83}
84
85void
86todc_direct_write_val(int addr, unsigned char val)
87{
88	writeb(val, (void __iomem *)(todc_info->nvram_data + addr));
89	return;
90}
91
92/* Access routines for accessing m48txx type chips via addr/data regs */
93u_char
94todc_m48txx_read_val(int addr)
95{
96	outb(addr, todc_info->nvram_as0);
97	outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
98	return inb(todc_info->nvram_data);
99}
100
101void
102todc_m48txx_write_val(int addr, unsigned char val)
103{
104	outb(addr, todc_info->nvram_as0);
105	outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
106   	outb(val, todc_info->nvram_data);
107	return;
108}
109
110/* Access routines for accessing mc146818 type chips via addr/data regs */
111u_char
112todc_mc146818_read_val(int addr)
113{
114	outb_p(addr, todc_info->nvram_as0);
115	return inb_p(todc_info->nvram_data);
116}
117
118void
119todc_mc146818_write_val(int addr, unsigned char val)
120{
121	outb_p(addr, todc_info->nvram_as0);
122   	outb_p(val, todc_info->nvram_data);
123}
124
125
126/*
127 * Routines to make RTC chips with NVRAM buried behind an addr/data pair
128 * have the NVRAM and clock regs appear at the same level.
129 * The NVRAM will appear to start at addr 0 and the clock regs will appear
130 * to start immediately after the NVRAM (actually, start at offset
131 * todc_info->nvram_size).
132 */
133static inline u_char
134todc_read_val(int addr)
135{
136	u_char	val;
137
138	if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
139		if (addr < todc_info->nvram_size) { /* NVRAM */
140			ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
141			val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
142		}
143		else { /* Clock Reg */
144			addr -= todc_info->nvram_size;
145			val = ppc_md.rtc_read_val(addr);
146		}
147	}
148	else {
149		val = ppc_md.rtc_read_val(addr);
150	}
151
152	return val;
153}
154
155static inline void
156todc_write_val(int addr, u_char val)
157{
158	if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
159		if (addr < todc_info->nvram_size) { /* NVRAM */
160			ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
161			ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
162		}
163		else { /* Clock Reg */
164			addr -= todc_info->nvram_size;
165			ppc_md.rtc_write_val(addr, val);
166		}
167	}
168	else {
169		ppc_md.rtc_write_val(addr, val);
170	}
171}
172
173/*
174 * TODC routines
175 *
176 * There is some ugly stuff in that there are assumptions for the mc146818.
177 *
178 * Assumptions:
179 *	- todc_info->control_a has the offset as mc146818 Register B reg
180 *	- todc_info->control_b has the offset as mc146818 Register A reg
181 *	- m48txx control reg's write enable or 'W' bit is same as
182 *	  mc146818 Register B 'SET' bit (i.e., 0x80)
183 *
184 * These assumptions were made to make the code simpler.
185 */
186long __init
187todc_time_init(void)
188{
189	u_char	cntl_b;
190
191	if (!ppc_md.rtc_read_val)
192		ppc_md.rtc_read_val = ppc_md.nvram_read_val;
193	if (!ppc_md.rtc_write_val)
194		ppc_md.rtc_write_val = ppc_md.nvram_write_val;
195
196	cntl_b = todc_read_val(todc_info->control_b);
197
198	if (todc_info->rtc_type == TODC_TYPE_MC146818) {
199		if ((cntl_b & 0x70) != 0x20) {
200			printk(KERN_INFO "TODC %s %s\n",
201				"real-time-clock was stopped.",
202				"Now starting...");
203			cntl_b &= ~0x70;
204			cntl_b |= 0x20;
205		}
206
207		todc_write_val(todc_info->control_b, cntl_b);
208	} else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
209		u_char mode;
210
211		mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
212		/* Make sure countdown clear is not set */
213		mode &= ~0x40;
214		/* Enable oscillator, extended register set */
215		mode |= 0x30;
216		todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
217
218	} else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
219		u_char	month;
220
221		todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
222		todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
223
224		month = todc_read_val(todc_info->month);
225
226		if ((month & 0x80) == 0x80) {
227			printk(KERN_INFO "TODC %s %s\n",
228				"real-time-clock was stopped.",
229				"Now starting...");
230			month &= ~0x80;
231			todc_write_val(todc_info->month, month);
232		}
233
234		cntl_b &= ~TODC_DS1501_CNTL_B_TE;
235		todc_write_val(todc_info->control_b, cntl_b);
236	} else { /* must be a m48txx type */
237		u_char	cntl_a;
238
239		todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
240		todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
241
242		cntl_a = todc_read_val(todc_info->control_a);
243
244		/* Check & clear STOP bit in control B register */
245		if (cntl_b & TODC_MK48TXX_DAY_CB) {
246			printk(KERN_INFO "TODC %s %s\n",
247				"real-time-clock was stopped.",
248				"Now starting...");
249
250			cntl_a |= todc_info->enable_write;
251			cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
252
253			todc_write_val(todc_info->control_a, cntl_a);
254			todc_write_val(todc_info->control_b, cntl_b);
255		}
256
257		/* Make sure READ & WRITE bits are cleared. */
258		cntl_a &= ~(todc_info->enable_write |
259			    todc_info->enable_read);
260		todc_write_val(todc_info->control_a, cntl_a);
261	}
262
263	return 0;
264}
265
266/*
267 * There is some ugly stuff in that there are assumptions that for a mc146818,
268 * the todc_info->control_a has the offset of the mc146818 Register B reg and
269 * that the register'ss 'SET' bit is the same as the m48txx's write enable
270 * bit in the control register of the m48txx (i.e., 0x80).
271 *
272 * It was done to make the code look simpler.
273 */
274ulong
275todc_get_rtc_time(void)
276{
277	uint	year = 0, mon = 0, day = 0, hour = 0, min = 0, sec = 0;
278	uint	limit, i;
279	u_char	save_control, uip = 0;
280
281	spin_lock(&rtc_lock);
282	save_control = todc_read_val(todc_info->control_a);
283
284	if (todc_info->rtc_type != TODC_TYPE_MC146818) {
285		limit = 1;
286
287		switch (todc_info->rtc_type) {
288			case TODC_TYPE_DS1553:
289			case TODC_TYPE_DS1557:
290			case TODC_TYPE_DS1743:
291			case TODC_TYPE_DS1746:
292			case TODC_TYPE_DS1747:
293			case TODC_TYPE_DS17285:
294				break;
295			default:
296				todc_write_val(todc_info->control_a,
297				       (save_control | todc_info->enable_read));
298		}
299	}
300	else {
301		limit = 100000000;
302	}
303
304	for (i=0; i<limit; i++) {
305		if (todc_info->rtc_type == TODC_TYPE_MC146818) {
306			uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
307		}
308
309		sec = todc_read_val(todc_info->seconds) & 0x7f;
310		min = todc_read_val(todc_info->minutes) & 0x7f;
311		hour = todc_read_val(todc_info->hours) & 0x3f;
312		day = todc_read_val(todc_info->day_of_month) & 0x3f;
313		mon = todc_read_val(todc_info->month) & 0x1f;
314		year = todc_read_val(todc_info->year) & 0xff;
315
316		if (todc_info->rtc_type == TODC_TYPE_MC146818) {
317			uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
318			if ((uip & RTC_UIP) == 0) break;
319		}
320	}
321
322	if (todc_info->rtc_type != TODC_TYPE_MC146818) {
323		switch (todc_info->rtc_type) {
324			case TODC_TYPE_DS1553:
325			case TODC_TYPE_DS1557:
326			case TODC_TYPE_DS1743:
327			case TODC_TYPE_DS1746:
328			case TODC_TYPE_DS1747:
329			case TODC_TYPE_DS17285:
330				break;
331			default:
332				save_control &= ~(todc_info->enable_read);
333				todc_write_val(todc_info->control_a,
334						       save_control);
335		}
336	}
337	spin_unlock(&rtc_lock);
338
339	if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
340	    ((save_control & RTC_DM_BINARY) == 0) ||
341	    RTC_ALWAYS_BCD) {
342
343		BCD_TO_BIN(sec);
344		BCD_TO_BIN(min);
345		BCD_TO_BIN(hour);
346		BCD_TO_BIN(day);
347		BCD_TO_BIN(mon);
348		BCD_TO_BIN(year);
349	}
350
351	year = year + 1900;
352	if (year < 1970) {
353		year += 100;
354	}
355
356	return mktime(year, mon, day, hour, min, sec);
357}
358
359int
360todc_set_rtc_time(unsigned long nowtime)
361{
362	struct rtc_time	tm;
363	u_char		save_control, save_freq_select = 0;
364
365	spin_lock(&rtc_lock);
366	to_tm(nowtime, &tm);
367
368	save_control = todc_read_val(todc_info->control_a);
369
370	/* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
371	todc_write_val(todc_info->control_a,
372			       (save_control | todc_info->enable_write));
373	save_control &= ~(todc_info->enable_write); /* in case it was set */
374
375	if (todc_info->rtc_type == TODC_TYPE_MC146818) {
376		save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
377		todc_write_val(todc_info->RTC_FREQ_SELECT,
378				       save_freq_select | RTC_DIV_RESET2);
379	}
380
381
382        tm.tm_year = (tm.tm_year - 1900) % 100;
383
384	if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
385	    ((save_control & RTC_DM_BINARY) == 0) ||
386	    RTC_ALWAYS_BCD) {
387
388		BIN_TO_BCD(tm.tm_sec);
389		BIN_TO_BCD(tm.tm_min);
390		BIN_TO_BCD(tm.tm_hour);
391		BIN_TO_BCD(tm.tm_mon);
392		BIN_TO_BCD(tm.tm_mday);
393		BIN_TO_BCD(tm.tm_year);
394	}
395
396	todc_write_val(todc_info->seconds,      tm.tm_sec);
397	todc_write_val(todc_info->minutes,      tm.tm_min);
398	todc_write_val(todc_info->hours,        tm.tm_hour);
399	todc_write_val(todc_info->month,        tm.tm_mon);
400	todc_write_val(todc_info->day_of_month, tm.tm_mday);
401	todc_write_val(todc_info->year,         tm.tm_year);
402
403	todc_write_val(todc_info->control_a, save_control);
404
405	if (todc_info->rtc_type == TODC_TYPE_MC146818) {
406		todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
407	}
408	spin_unlock(&rtc_lock);
409
410	return 0;
411}
412
413/*
414 * Manipulates read bit to reliably read seconds at a high rate.
415 */
416static unsigned char __init todc_read_timereg(int addr)
417{
418	unsigned char save_control = 0, val;
419
420	switch (todc_info->rtc_type) {
421		case TODC_TYPE_DS1553:
422		case TODC_TYPE_DS1557:
423		case TODC_TYPE_DS1746:
424		case TODC_TYPE_DS1747:
425		case TODC_TYPE_DS17285:
426		case TODC_TYPE_MC146818:
427			break;
428		default:
429			save_control = todc_read_val(todc_info->control_a);
430			todc_write_val(todc_info->control_a,
431				       (save_control | todc_info->enable_read));
432	}
433	val = todc_read_val(addr);
434
435	switch (todc_info->rtc_type) {
436		case TODC_TYPE_DS1553:
437		case TODC_TYPE_DS1557:
438		case TODC_TYPE_DS1746:
439		case TODC_TYPE_DS1747:
440		case TODC_TYPE_DS17285:
441		case TODC_TYPE_MC146818:
442			break;
443		default:
444			save_control &= ~(todc_info->enable_read);
445			todc_write_val(todc_info->control_a, save_control);
446	}
447
448	return val;
449}
450
451/*
452 * This was taken from prep_setup.c
453 * Use the NVRAM RTC to time a second to calibrate the decrementer.
454 */
455void __init
456todc_calibrate_decr(void)
457{
458	ulong	freq;
459	ulong	tbl, tbu;
460        long	i, loop_count;
461        u_char	sec;
462
463	todc_time_init();
464
465	/*
466	 * Actually this is bad for precision, we should have a loop in
467	 * which we only read the seconds counter. todc_read_val writes
468	 * the address bytes on every call and this takes a lot of time.
469	 * Perhaps an nvram_wait_change method returning a time
470	 * stamp with a loop count as parameter would be the solution.
471	 */
472	/*
473	 * Need to make sure the tbl doesn't roll over so if tbu increments
474	 * during this test, we need to do it again.
475	 */
476	loop_count = 0;
477
478	sec = todc_read_timereg(todc_info->seconds) & 0x7f;
479
480	do {
481		tbu = get_tbu();
482
483		for (i = 0 ; i < 10000000 ; i++) {/* may take up to 1 second */
484		   tbl = get_tbl();
485
486		   if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
487		      break;
488		   }
489		}
490
491		sec = todc_read_timereg(todc_info->seconds) & 0x7f;
492
493		for (i = 0 ; i < 10000000 ; i++) { /* Should take 1 second */
494		   freq = get_tbl();
495
496		   if ((todc_read_timereg(todc_info->seconds) & 0x7f) != sec) {
497		      break;
498		   }
499		}
500
501		freq -= tbl;
502	} while ((get_tbu() != tbu) && (++loop_count < 2));
503
504	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
505	       freq/1000000, freq%1000000);
506
507	tb_ticks_per_jiffy = freq / HZ;
508	tb_to_us = mulhwu_scale_factor(freq, 1000000);
509
510	return;
511}
512