1/*
2 *  Copyright (C) 1995  Linus Torvalds
3 *  Adapted from 'alpha' version by Gary Thomas
4 *  Modified by Cort Dougan (cort@cs.nmt.edu)
5 *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
6 *  Further modified for generic 8xx by Dan.
7 */
8
9/*
10 * bootup setup stuff..
11 */
12
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/stddef.h>
18#include <linux/unistd.h>
19#include <linux/ptrace.h>
20#include <linux/slab.h>
21#include <linux/user.h>
22#include <linux/a.out.h>
23#include <linux/tty.h>
24#include <linux/major.h>
25#include <linux/interrupt.h>
26#include <linux/reboot.h>
27#include <linux/init.h>
28#include <linux/initrd.h>
29#include <linux/ioport.h>
30#include <linux/bootmem.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33
34#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
35#include <linux/mtd/partitions.h>
36#include <linux/mtd/physmap.h>
37#include <linux/mtd/mtd.h>
38#include <linux/mtd/map.h>
39#endif
40
41#include <asm/mmu.h>
42#include <asm/reg.h>
43#include <asm/residual.h>
44#include <asm/io.h>
45#include <asm/pgtable.h>
46#include <asm/mpc8xx.h>
47#include <asm/8xx_immap.h>
48#include <asm/machdep.h>
49#include <asm/bootinfo.h>
50#include <asm/time.h>
51#include <asm/xmon.h>
52#include <asm/ppc_sys.h>
53
54#include "ppc8xx_pic.h"
55
56#ifdef CONFIG_MTD_PHYSMAP
57#define MPC8xxADS_BANK_WIDTH 4
58#endif
59
60#define MPC8xxADS_U_BOOT_SIZE          0x80000
61#define MPC8xxADS_FREE_AREA_OFFSET     MPC8xxADS_U_BOOT_SIZE
62
63#if defined(CONFIG_MTD_PARTITIONS)
64 /*
65   NOTE: bank width and interleave relative to the installed flash
66   should have been chosen within MTD_CFI_GEOMETRY options.
67 */
68static struct mtd_partition mpc8xxads_partitions[] = {
69	{
70		.name = "bootloader",
71		.size = MPC8xxADS_U_BOOT_SIZE,
72		.offset = 0,
73		.mask_flags   = MTD_WRITEABLE,  /* force read-only */
74	}, {
75		.name = "User FS",
76		.offset = MPC8xxADS_FREE_AREA_OFFSET
77	}
78};
79
80#define mpc8xxads_part_num ARRAY_SIZE(mpc8xxads_partitions)
81
82#endif
83
84static int m8xx_set_rtc_time(unsigned long time);
85static unsigned long m8xx_get_rtc_time(void);
86void m8xx_calibrate_decr(void);
87
88unsigned char __res[sizeof(bd_t)];
89
90extern void m8xx_ide_init(void);
91
92extern unsigned long find_available_memory(void);
93extern void m8xx_cpm_reset(void);
94extern void m8xx_wdt_handler_install(bd_t *bp);
95extern void rpxfb_alloc_pages(void);
96extern void cpm_interrupt_init(void);
97
98void __attribute__ ((weak))
99board_init(void)
100{
101}
102
103void __init
104m8xx_setup_arch(void)
105{
106#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
107	bd_t *binfo = (bd_t *)__res;
108#endif
109
110	/* Reset the Communication Processor Module.
111	*/
112	m8xx_cpm_reset();
113
114#ifdef CONFIG_FB_RPX
115	rpxfb_alloc_pages();
116#endif
117
118#ifdef notdef
119	ROOT_DEV = Root_HDA1; /* hda1 */
120#endif
121
122#ifdef CONFIG_BLK_DEV_INITRD
123#endif
124
125#if defined(CONFIG_MPC86XADS) || defined(CONFIG_MPC885ADS)
126#if defined(CONFIG_MTD_PHYSMAP)
127       physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
128                                               MPC8xxADS_BANK_WIDTH, NULL);
129#ifdef CONFIG_MTD_PARTITIONS
130       physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
131#endif /* CONFIG_MTD_PARTITIONS */
132#endif /* CONFIG_MTD_PHYSMAP */
133#endif
134
135	board_init();
136}
137
138void
139abort(void)
140{
141#ifdef CONFIG_XMON
142	xmon(0);
143#endif
144	machine_restart(NULL);
145
146	/* not reached */
147	for (;;);
148}
149
150/* A place holder for time base interrupts, if they are ever enabled. */
151irqreturn_t timebase_interrupt(int irq, void * dev)
152{
153	printk ("timebase_interrupt()\n");
154
155	return IRQ_HANDLED;
156}
157
158static struct irqaction tbint_irqaction = {
159	.handler = timebase_interrupt,
160	.mask = CPU_MASK_NONE,
161	.name = "tbint",
162};
163
164/* per-board overridable init_internal_rtc() function. */
165void __init __attribute__ ((weak))
166init_internal_rtc(void)
167{
168	/* Disable the RTC one second and alarm interrupts. */
169	clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
170
171	/* Enable the RTC */
172	setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
173
174}
175
176/* The decrementer counts at the system (internal) clock frequency divided by
177 * sixteen, or external oscillator divided by four.  We force the processor
178 * to use system clock divided by sixteen.
179 */
180void __init m8xx_calibrate_decr(void)
181{
182	bd_t	*binfo = (bd_t *)__res;
183	int freq, fp, divisor;
184
185	/* Unlock the SCCR. */
186	out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY);
187	out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
188
189	/* Force all 8xx processors to use divide by 16 processor clock. */
190	setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
191	/* Processor frequency is MHz.
192	 * The value 'fp' is the number of decrementer ticks per second.
193	 */
194	fp = binfo->bi_intfreq / 16;
195	freq = fp*60;	/* try to make freq/1e6 an integer */
196        divisor = 60;
197        printk("Decrementer Frequency = %d/%d\n", freq, divisor);
198        tb_ticks_per_jiffy = freq / HZ / divisor;
199	tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
200
201	/* Perform some more timer/timebase initialization.  This used
202	 * to be done elsewhere, but other changes caused it to get
203	 * called more than once....that is a bad thing.
204	 *
205	 * First, unlock all of the registers we are going to modify.
206	 * To protect them from corruption during power down, registers
207	 * that are maintained by keep alive power are "locked".  To
208	 * modify these registers we have to write the key value to
209	 * the key location associated with the register.
210	 * Some boards power up with these unlocked, while others
211	 * are locked.  Writing anything (including the unlock code?)
212	 * to the unlocked registers will lock them again.  So, here
213	 * we guarantee the registers are locked, then we unlock them
214	 * for our use.
215	 */
216	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY);
217	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY);
218	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY);
219	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY);
220	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
221	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
222
223	init_internal_rtc();
224
225	/* Enabling the decrementer also enables the timebase interrupts
226	 * (or from the other point of view, to get decrementer interrupts
227	 * we have to enable the timebase).  The decrementer interrupt
228	 * is wired into the vector table, nothing to do here for that.
229	 */
230	out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE));
231
232	if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
233		panic("Could not allocate timer IRQ!");
234
235#ifdef CONFIG_8xx_WDT
236	/* Install watchdog timer handler early because it might be
237	 * already enabled by the bootloader
238	 */
239	m8xx_wdt_handler_install(binfo);
240#endif
241}
242
243/* The RTC on the MPC8xx is an internal register.
244 * We want to protect this during power down, so we need to unlock,
245 * modify, and re-lock.
246 */
247static int
248m8xx_set_rtc_time(unsigned long time)
249{
250	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY);
251	out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time);
252	out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY);
253	return(0);
254}
255
256static unsigned long
257m8xx_get_rtc_time(void)
258{
259	/* Get time from the RTC. */
260	return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc);
261}
262
263static void
264m8xx_restart(char *cmd)
265{
266	__volatile__ unsigned char dummy;
267
268	local_irq_disable();
269
270	setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
271	/* Clear the ME bit in MSR to cause checkstop on machine check
272	*/
273	mtmsr(mfmsr() & ~0x1000);
274
275	dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]);
276	printk("Restart failed\n");
277	while(1);
278}
279
280static void
281m8xx_power_off(void)
282{
283   m8xx_restart(NULL);
284}
285
286static void
287m8xx_halt(void)
288{
289   m8xx_restart(NULL);
290}
291
292
293static int
294m8xx_show_percpuinfo(struct seq_file *m, int i)
295{
296	bd_t	*bp;
297
298	bp = (bd_t *)__res;
299
300	seq_printf(m, "clock\t\t: %uMHz\n"
301		   "bus clock\t: %uMHz\n",
302		   bp->bi_intfreq / 1000000,
303		   bp->bi_busfreq / 1000000);
304
305	return 0;
306}
307
308#ifdef CONFIG_PCI
309static struct irqaction mbx_i8259_irqaction = {
310	.handler = mbx_i8259_action,
311	.mask = CPU_MASK_NONE,
312	.name = "i8259 cascade",
313};
314#endif
315
316/* Initialize the internal interrupt controller.  The number of
317 * interrupts supported can vary with the processor type, and the
318 * 82xx family can have up to 64.
319 * External interrupts can be either edge or level triggered, and
320 * need to be initialized by the appropriate driver.
321 */
322static void __init
323m8xx_init_IRQ(void)
324{
325	int i;
326
327	for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
328		irq_desc[i].chip = &ppc8xx_pic;
329
330	cpm_interrupt_init();
331
332#if defined(CONFIG_PCI)
333	for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
334		irq_desc[i].chip = &i8259_pic;
335
336	i8259_pic_irq_offset = I8259_IRQ_OFFSET;
337	i8259_init(0);
338
339	/* The i8259 cascade interrupt must be level sensitive. */
340
341	clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
342	if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
343		enable_irq(ISA_BRIDGE_INT);
344#endif	/* CONFIG_PCI */
345}
346
347/* -------------------------------------------------------------------- */
348
349/*
350 * This is a big hack right now, but it may turn into something real
351 * someday.
352 *
353 * For the 8xx boards (at this time anyway), there is nothing to initialize
354 * associated the PROM.  Rather than include all of the prom.c
355 * functions in the image just to get prom_init, all we really need right
356 * now is the initialization of the physical memory region.
357 */
358static unsigned long __init
359m8xx_find_end_of_memory(void)
360{
361	bd_t	*binfo;
362	extern unsigned char __res[];
363
364	binfo = (bd_t *)__res;
365
366	return binfo->bi_memsize;
367}
368
369/*
370 * Now map in some of the I/O space that is generically needed
371 * or shared with multiple devices.
372 * All of this fits into the same 4Mbyte region, so it only
373 * requires one page table page.  (or at least it used to  -- paulus)
374 */
375static void __init
376m8xx_map_io(void)
377{
378        io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
379#ifdef CONFIG_MBX
380        io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
381        io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
382        io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
383
384	/* Map some of the PCI/ISA I/O space to get the IDE interface.
385	*/
386        io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
387        io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
388#endif
389#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
390	io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
391#if !defined(CONFIG_PCI)
392	io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
393#endif
394#endif
395#if defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
396	io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
397#endif
398#ifdef CONFIG_FADS
399	io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
400#endif
401#ifdef CONFIG_PCI
402        io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
403#endif
404#if defined(CONFIG_NETTA)
405	io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
406#endif
407}
408
409void __init
410platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
411		unsigned long r6, unsigned long r7)
412{
413	parse_bootinfo(find_bootinfo());
414
415	if ( r3 )
416		memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
417
418#ifdef CONFIG_PCI
419	m8xx_setup_pci_ptrs();
420#endif
421
422#ifdef CONFIG_BLK_DEV_INITRD
423	/* take care of initrd if we have one */
424	if ( r4 )
425	{
426		initrd_start = r4 + KERNELBASE;
427		initrd_end = r5 + KERNELBASE;
428	}
429#endif /* CONFIG_BLK_DEV_INITRD */
430	/* take care of cmd line */
431	if ( r6 )
432	{
433		*(char *)(r7+KERNELBASE) = 0;
434		strcpy(cmd_line, (char *)(r6+KERNELBASE));
435	}
436
437	identify_ppc_sys_by_name(BOARD_CHIP_NAME);
438
439	ppc_md.setup_arch		= m8xx_setup_arch;
440	ppc_md.show_percpuinfo		= m8xx_show_percpuinfo;
441	ppc_md.init_IRQ			= m8xx_init_IRQ;
442	ppc_md.get_irq			= m8xx_get_irq;
443	ppc_md.init			= NULL;
444
445	ppc_md.restart			= m8xx_restart;
446	ppc_md.power_off		= m8xx_power_off;
447	ppc_md.halt			= m8xx_halt;
448
449	ppc_md.time_init		= NULL;
450	ppc_md.set_rtc_time		= m8xx_set_rtc_time;
451	ppc_md.get_rtc_time		= m8xx_get_rtc_time;
452	ppc_md.calibrate_decr		= m8xx_calibrate_decr;
453
454	ppc_md.find_end_of_memory	= m8xx_find_end_of_memory;
455	ppc_md.setup_io_mappings	= m8xx_map_io;
456
457#if defined(CONFIG_BLK_DEV_MPC8xx_IDE)
458	m8xx_ide_init();
459#endif
460}
461