1/* 2 * PReP pci functions. 3 * Originally by Gary Thomas 4 * rewritten and updated by Cort Dougan (cort@cs.nmt.edu) 5 * 6 * The motherboard routes/maps will disappear shortly. -- Cort 7 */ 8 9#include <linux/types.h> 10#include <linux/pci.h> 11#include <linux/kernel.h> 12#include <linux/init.h> 13 14#include <asm/sections.h> 15#include <asm/byteorder.h> 16#include <asm/io.h> 17#include <asm/ptrace.h> 18#include <asm/prom.h> 19#include <asm/pci-bridge.h> 20#include <asm/residual.h> 21#include <asm/irq.h> 22#include <asm/machdep.h> 23#include <asm/open_pic.h> 24 25extern void (*setup_ibm_pci)(char *irq_lo, char *irq_hi); 26 27/* Which PCI interrupt line does a given device [slot] use? */ 28/* Note: This really should be two dimensional based in slot/pin used */ 29static unsigned char *Motherboard_map; 30unsigned char *Motherboard_map_name; 31 32/* How is the 82378 PIRQ mapping setup? */ 33static unsigned char *Motherboard_routes; 34 35static void (*Motherboard_non0)(struct pci_dev *); 36 37static void Powerplus_Map_Non0(struct pci_dev *); 38 39/* Used for Motorola to store system config register */ 40static unsigned long *ProcInfo; 41 42/* Tables for known hardware */ 43 44/* Motorola PowerStackII - Utah */ 45static char Utah_pci_IRQ_map[23] = 46{ 47 0, /* Slot 0 - unused */ 48 0, /* Slot 1 - unused */ 49 5, /* Slot 2 - SCSI - NCR825A */ 50 0, /* Slot 3 - unused */ 51 3, /* Slot 4 - Ethernet - DEC2114x */ 52 0, /* Slot 5 - unused */ 53 2, /* Slot 6 - PCI Card slot #1 */ 54 3, /* Slot 7 - PCI Card slot #2 */ 55 5, /* Slot 8 - PCI Card slot #3 */ 56 5, /* Slot 9 - PCI Bridge */ 57 /* added here in case we ever support PCI bridges */ 58 /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */ 59 0, /* Slot 10 - unused */ 60 0, /* Slot 11 - unused */ 61 5, /* Slot 12 - SCSI - NCR825A */ 62 0, /* Slot 13 - unused */ 63 3, /* Slot 14 - enet */ 64 0, /* Slot 15 - unused */ 65 2, /* Slot 16 - unused */ 66 3, /* Slot 17 - unused */ 67 5, /* Slot 18 - unused */ 68 0, /* Slot 19 - unused */ 69 0, /* Slot 20 - unused */ 70 0, /* Slot 21 - unused */ 71 0, /* Slot 22 - unused */ 72}; 73 74static char Utah_pci_IRQ_routes[] = 75{ 76 0, /* Line 0 - Unused */ 77 9, /* Line 1 */ 78 10, /* Line 2 */ 79 11, /* Line 3 */ 80 14, /* Line 4 */ 81 15, /* Line 5 */ 82}; 83 84/* Motorola PowerStackII - Omaha */ 85/* no integrated SCSI or ethernet */ 86static char Omaha_pci_IRQ_map[23] = 87{ 88 0, /* Slot 0 - unused */ 89 0, /* Slot 1 - unused */ 90 3, /* Slot 2 - Winbond EIDE */ 91 0, /* Slot 3 - unused */ 92 0, /* Slot 4 - unused */ 93 0, /* Slot 5 - unused */ 94 1, /* Slot 6 - PCI slot 1 */ 95 2, /* Slot 7 - PCI slot 2 */ 96 3, /* Slot 8 - PCI slot 3 */ 97 4, /* Slot 9 - PCI slot 4 */ /* needs indirect access */ 98 0, /* Slot 10 - unused */ 99 0, /* Slot 11 - unused */ 100 0, /* Slot 12 - unused */ 101 0, /* Slot 13 - unused */ 102 0, /* Slot 14 - unused */ 103 0, /* Slot 15 - unused */ 104 1, /* Slot 16 - PCI slot 1 */ 105 2, /* Slot 17 - PCI slot 2 */ 106 3, /* Slot 18 - PCI slot 3 */ 107 4, /* Slot 19 - PCI slot 4 */ /* needs indirect access */ 108 0, 109 0, 110 0, 111}; 112 113static char Omaha_pci_IRQ_routes[] = 114{ 115 0, /* Line 0 - Unused */ 116 9, /* Line 1 */ 117 11, /* Line 2 */ 118 14, /* Line 3 */ 119 15 /* Line 4 */ 120}; 121 122/* Motorola PowerStack */ 123static char Blackhawk_pci_IRQ_map[19] = 124{ 125 0, /* Slot 0 - unused */ 126 0, /* Slot 1 - unused */ 127 0, /* Slot 2 - unused */ 128 0, /* Slot 3 - unused */ 129 0, /* Slot 4 - unused */ 130 0, /* Slot 5 - unused */ 131 0, /* Slot 6 - unused */ 132 0, /* Slot 7 - unused */ 133 0, /* Slot 8 - unused */ 134 0, /* Slot 9 - unused */ 135 0, /* Slot 10 - unused */ 136 0, /* Slot 11 - unused */ 137 3, /* Slot 12 - SCSI */ 138 0, /* Slot 13 - unused */ 139 1, /* Slot 14 - Ethernet */ 140 0, /* Slot 15 - unused */ 141 1, /* Slot P7 */ 142 2, /* Slot P6 */ 143 3, /* Slot P5 */ 144}; 145 146static char Blackhawk_pci_IRQ_routes[] = 147{ 148 0, /* Line 0 - Unused */ 149 9, /* Line 1 */ 150 11, /* Line 2 */ 151 15, /* Line 3 */ 152 15 /* Line 4 */ 153}; 154 155/* Motorola Mesquite */ 156static char Mesquite_pci_IRQ_map[23] = 157{ 158 0, /* Slot 0 - unused */ 159 0, /* Slot 1 - unused */ 160 0, /* Slot 2 - unused */ 161 0, /* Slot 3 - unused */ 162 0, /* Slot 4 - unused */ 163 0, /* Slot 5 - unused */ 164 0, /* Slot 6 - unused */ 165 0, /* Slot 7 - unused */ 166 0, /* Slot 8 - unused */ 167 0, /* Slot 9 - unused */ 168 0, /* Slot 10 - unused */ 169 0, /* Slot 11 - unused */ 170 0, /* Slot 12 - unused */ 171 0, /* Slot 13 - unused */ 172 2, /* Slot 14 - Ethernet */ 173 0, /* Slot 15 - unused */ 174 3, /* Slot 16 - PMC */ 175 0, /* Slot 17 - unused */ 176 0, /* Slot 18 - unused */ 177 0, /* Slot 19 - unused */ 178 0, /* Slot 20 - unused */ 179 0, /* Slot 21 - unused */ 180 0, /* Slot 22 - unused */ 181}; 182 183/* Motorola Sitka */ 184static char Sitka_pci_IRQ_map[21] = 185{ 186 0, /* Slot 0 - unused */ 187 0, /* Slot 1 - unused */ 188 0, /* Slot 2 - unused */ 189 0, /* Slot 3 - unused */ 190 0, /* Slot 4 - unused */ 191 0, /* Slot 5 - unused */ 192 0, /* Slot 6 - unused */ 193 0, /* Slot 7 - unused */ 194 0, /* Slot 8 - unused */ 195 0, /* Slot 9 - unused */ 196 0, /* Slot 10 - unused */ 197 0, /* Slot 11 - unused */ 198 0, /* Slot 12 - unused */ 199 0, /* Slot 13 - unused */ 200 2, /* Slot 14 - Ethernet */ 201 0, /* Slot 15 - unused */ 202 9, /* Slot 16 - PMC 1 */ 203 12, /* Slot 17 - PMC 2 */ 204 0, /* Slot 18 - unused */ 205 0, /* Slot 19 - unused */ 206 4, /* Slot 20 - NT P2P bridge */ 207}; 208 209/* Motorola MTX */ 210static char MTX_pci_IRQ_map[23] = 211{ 212 0, /* Slot 0 - unused */ 213 0, /* Slot 1 - unused */ 214 0, /* Slot 2 - unused */ 215 0, /* Slot 3 - unused */ 216 0, /* Slot 4 - unused */ 217 0, /* Slot 5 - unused */ 218 0, /* Slot 6 - unused */ 219 0, /* Slot 7 - unused */ 220 0, /* Slot 8 - unused */ 221 0, /* Slot 9 - unused */ 222 0, /* Slot 10 - unused */ 223 0, /* Slot 11 - unused */ 224 3, /* Slot 12 - SCSI */ 225 0, /* Slot 13 - unused */ 226 2, /* Slot 14 - Ethernet */ 227 0, /* Slot 15 - unused */ 228 9, /* Slot 16 - PCI/PMC slot 1 */ 229 10, /* Slot 17 - PCI/PMC slot 2 */ 230 11, /* Slot 18 - PCI slot 3 */ 231 0, /* Slot 19 - unused */ 232 0, /* Slot 20 - unused */ 233 0, /* Slot 21 - unused */ 234 0, /* Slot 22 - unused */ 235}; 236 237/* Motorola MTX Plus */ 238/* Secondary bus interrupt routing is not supported yet */ 239static char MTXplus_pci_IRQ_map[23] = 240{ 241 0, /* Slot 0 - unused */ 242 0, /* Slot 1 - unused */ 243 0, /* Slot 2 - unused */ 244 0, /* Slot 3 - unused */ 245 0, /* Slot 4 - unused */ 246 0, /* Slot 5 - unused */ 247 0, /* Slot 6 - unused */ 248 0, /* Slot 7 - unused */ 249 0, /* Slot 8 - unused */ 250 0, /* Slot 9 - unused */ 251 0, /* Slot 10 - unused */ 252 0, /* Slot 11 - unused */ 253 3, /* Slot 12 - SCSI */ 254 0, /* Slot 13 - unused */ 255 2, /* Slot 14 - Ethernet 1 */ 256 0, /* Slot 15 - unused */ 257 9, /* Slot 16 - PCI slot 1P */ 258 10, /* Slot 17 - PCI slot 2P */ 259 11, /* Slot 18 - PCI slot 3P */ 260 10, /* Slot 19 - Ethernet 2 */ 261 0, /* Slot 20 - P2P Bridge */ 262 0, /* Slot 21 - unused */ 263 0, /* Slot 22 - unused */ 264}; 265 266static char Raven_pci_IRQ_routes[] = 267{ 268 0, /* This is a dummy structure */ 269}; 270 271/* Motorola MVME16xx */ 272static char Genesis_pci_IRQ_map[16] = 273{ 274 0, /* Slot 0 - unused */ 275 0, /* Slot 1 - unused */ 276 0, /* Slot 2 - unused */ 277 0, /* Slot 3 - unused */ 278 0, /* Slot 4 - unused */ 279 0, /* Slot 5 - unused */ 280 0, /* Slot 6 - unused */ 281 0, /* Slot 7 - unused */ 282 0, /* Slot 8 - unused */ 283 0, /* Slot 9 - unused */ 284 0, /* Slot 10 - unused */ 285 0, /* Slot 11 - unused */ 286 3, /* Slot 12 - SCSI */ 287 0, /* Slot 13 - unused */ 288 1, /* Slot 14 - Ethernet */ 289 0, /* Slot 15 - unused */ 290}; 291 292static char Genesis_pci_IRQ_routes[] = 293{ 294 0, /* Line 0 - Unused */ 295 10, /* Line 1 */ 296 11, /* Line 2 */ 297 14, /* Line 3 */ 298 15 /* Line 4 */ 299}; 300 301static char Genesis2_pci_IRQ_map[23] = 302{ 303 0, /* Slot 0 - unused */ 304 0, /* Slot 1 - unused */ 305 0, /* Slot 2 - unused */ 306 0, /* Slot 3 - unused */ 307 0, /* Slot 4 - unused */ 308 0, /* Slot 5 - unused */ 309 0, /* Slot 6 - unused */ 310 0, /* Slot 7 - unused */ 311 0, /* Slot 8 - unused */ 312 0, /* Slot 9 - unused */ 313 0, /* Slot 10 - unused */ 314 0, /* Slot 11 - IDE */ 315 3, /* Slot 12 - SCSI */ 316 5, /* Slot 13 - Universe PCI - VME Bridge */ 317 2, /* Slot 14 - Ethernet */ 318 0, /* Slot 15 - unused */ 319 9, /* Slot 16 - PMC 1 */ 320 12, /* Slot 17 - pci */ 321 11, /* Slot 18 - pci */ 322 10, /* Slot 19 - pci */ 323 0, /* Slot 20 - pci */ 324 0, /* Slot 21 - unused */ 325 0, /* Slot 22 - unused */ 326}; 327 328/* Motorola Series-E */ 329static char Comet_pci_IRQ_map[23] = 330{ 331 0, /* Slot 0 - unused */ 332 0, /* Slot 1 - unused */ 333 0, /* Slot 2 - unused */ 334 0, /* Slot 3 - unused */ 335 0, /* Slot 4 - unused */ 336 0, /* Slot 5 - unused */ 337 0, /* Slot 6 - unused */ 338 0, /* Slot 7 - unused */ 339 0, /* Slot 8 - unused */ 340 0, /* Slot 9 - unused */ 341 0, /* Slot 10 - unused */ 342 0, /* Slot 11 - unused */ 343 3, /* Slot 12 - SCSI */ 344 0, /* Slot 13 - unused */ 345 1, /* Slot 14 - Ethernet */ 346 0, /* Slot 15 - unused */ 347 1, /* Slot 16 - PCI slot 1 */ 348 2, /* Slot 17 - PCI slot 2 */ 349 3, /* Slot 18 - PCI slot 3 */ 350 4, /* Slot 19 - PCI bridge */ 351 0, 352 0, 353 0, 354}; 355 356static char Comet_pci_IRQ_routes[] = 357{ 358 0, /* Line 0 - Unused */ 359 10, /* Line 1 */ 360 11, /* Line 2 */ 361 14, /* Line 3 */ 362 15 /* Line 4 */ 363}; 364 365/* Motorola Series-EX */ 366static char Comet2_pci_IRQ_map[23] = 367{ 368 0, /* Slot 0 - unused */ 369 0, /* Slot 1 - unused */ 370 3, /* Slot 2 - SCSI - NCR825A */ 371 0, /* Slot 3 - unused */ 372 1, /* Slot 4 - Ethernet - DEC2104X */ 373 0, /* Slot 5 - unused */ 374 1, /* Slot 6 - PCI slot 1 */ 375 2, /* Slot 7 - PCI slot 2 */ 376 3, /* Slot 8 - PCI slot 3 */ 377 4, /* Slot 9 - PCI bridge */ 378 0, /* Slot 10 - unused */ 379 0, /* Slot 11 - unused */ 380 3, /* Slot 12 - SCSI - NCR825A */ 381 0, /* Slot 13 - unused */ 382 1, /* Slot 14 - Ethernet - DEC2104X */ 383 0, /* Slot 15 - unused */ 384 1, /* Slot 16 - PCI slot 1 */ 385 2, /* Slot 17 - PCI slot 2 */ 386 3, /* Slot 18 - PCI slot 3 */ 387 4, /* Slot 19 - PCI bridge */ 388 0, 389 0, 390 0, 391}; 392 393static char Comet2_pci_IRQ_routes[] = 394{ 395 0, /* Line 0 - Unused */ 396 10, /* Line 1 */ 397 11, /* Line 2 */ 398 14, /* Line 3 */ 399 15, /* Line 4 */ 400}; 401 402/* 403 * ibm 830 (and 850?). 404 * This is actually based on the Carolina motherboard 405 * -- Cort 406 */ 407static char ibm8xx_pci_IRQ_map[23] = { 408 0, /* Slot 0 - unused */ 409 0, /* Slot 1 - unused */ 410 0, /* Slot 2 - unused */ 411 0, /* Slot 3 - unused */ 412 0, /* Slot 4 - unused */ 413 0, /* Slot 5 - unused */ 414 0, /* Slot 6 - unused */ 415 0, /* Slot 7 - unused */ 416 0, /* Slot 8 - unused */ 417 0, /* Slot 9 - unused */ 418 0, /* Slot 10 - unused */ 419 0, /* Slot 11 - FireCoral */ 420 4, /* Slot 12 - Ethernet PCIINTD# */ 421 2, /* Slot 13 - PCI Slot #2 */ 422 2, /* Slot 14 - S3 Video PCIINTD# */ 423 0, /* Slot 15 - onboard SCSI (INDI) [1] */ 424 3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */ 425 0, /* Slot 17 - unused */ 426 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */ 427 0, /* Slot 19 - unused */ 428 0, /* Slot 20 - unused */ 429 0, /* Slot 21 - unused */ 430 2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */ 431}; 432 433static char ibm8xx_pci_IRQ_routes[] = { 434 0, /* Line 0 - unused */ 435 15, /* Line 1 */ 436 15, /* Line 2 */ 437 15, /* Line 3 */ 438 15, /* Line 4 */ 439}; 440 441/* 442 * a 6015 ibm board 443 * -- Cort 444 */ 445static char ibm6015_pci_IRQ_map[23] = { 446 0, /* Slot 0 - unused */ 447 0, /* Slot 1 - unused */ 448 0, /* Slot 2 - unused */ 449 0, /* Slot 3 - unused */ 450 0, /* Slot 4 - unused */ 451 0, /* Slot 5 - unused */ 452 0, /* Slot 6 - unused */ 453 0, /* Slot 7 - unused */ 454 0, /* Slot 8 - unused */ 455 0, /* Slot 9 - unused */ 456 0, /* Slot 10 - unused */ 457 0, /* Slot 11 - */ 458 1, /* Slot 12 - SCSI */ 459 2, /* Slot 13 - */ 460 2, /* Slot 14 - */ 461 1, /* Slot 15 - */ 462 1, /* Slot 16 - */ 463 0, /* Slot 17 - */ 464 2, /* Slot 18 - */ 465 0, /* Slot 19 - */ 466 0, /* Slot 20 - */ 467 0, /* Slot 21 - */ 468 2, /* Slot 22 - */ 469}; 470 471static char ibm6015_pci_IRQ_routes[] = { 472 0, /* Line 0 - unused */ 473 13, /* Line 1 */ 474 15, /* Line 2 */ 475 15, /* Line 3 */ 476 15, /* Line 4 */ 477}; 478 479 480/* IBM Nobis and Thinkpad 850 */ 481static char Nobis_pci_IRQ_map[23] ={ 482 0, /* Slot 0 - unused */ 483 0, /* Slot 1 - unused */ 484 0, /* Slot 2 - unused */ 485 0, /* Slot 3 - unused */ 486 0, /* Slot 4 - unused */ 487 0, /* Slot 5 - unused */ 488 0, /* Slot 6 - unused */ 489 0, /* Slot 7 - unused */ 490 0, /* Slot 8 - unused */ 491 0, /* Slot 9 - unused */ 492 0, /* Slot 10 - unused */ 493 0, /* Slot 11 - unused */ 494 3, /* Slot 12 - SCSI */ 495 0, /* Slot 13 - unused */ 496 0, /* Slot 14 - unused */ 497 0, /* Slot 15 - unused */ 498}; 499 500static char Nobis_pci_IRQ_routes[] = { 501 0, /* Line 0 - Unused */ 502 13, /* Line 1 */ 503 13, /* Line 2 */ 504 13, /* Line 3 */ 505 13 /* Line 4 */ 506}; 507 508static char ibm43p_pci_IRQ_map[23] = { 509 0, /* Slot 0 - unused */ 510 0, /* Slot 1 - unused */ 511 0, /* Slot 2 - unused */ 512 0, /* Slot 3 - unused */ 513 0, /* Slot 4 - unused */ 514 0, /* Slot 5 - unused */ 515 0, /* Slot 6 - unused */ 516 0, /* Slot 7 - unused */ 517 0, /* Slot 8 - unused */ 518 0, /* Slot 9 - unused */ 519 0, /* Slot 10 - unused */ 520 0, /* Slot 11 - FireCoral ISA bridge */ 521 6, /* Slot 12 - Ethernet */ 522 0, /* Slot 13 - openpic */ 523 0, /* Slot 14 - unused */ 524 0, /* Slot 15 - unused */ 525 7, /* Slot 16 - NCR58C825a onboard scsi */ 526 0, /* Slot 17 - unused */ 527 2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */ 528 0, /* Slot 19 - unused */ 529 0, /* Slot 20 - unused */ 530 0, /* Slot 21 - unused */ 531 1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */ 532}; 533 534static char ibm43p_pci_IRQ_routes[] = { 535 0, /* Line 0 - unused */ 536 15, /* Line 1 */ 537 15, /* Line 2 */ 538 15, /* Line 3 */ 539 15, /* Line 4 */ 540}; 541 542/* Motorola PowerPlus architecture PCI IRQ tables */ 543/* Interrupt line values for INTA-D on primary/secondary MPIC inputs */ 544 545struct powerplus_irq_list 546{ 547 unsigned char primary[4]; /* INT A-D */ 548 unsigned char secondary[4]; /* INT A-D */ 549}; 550 551/* 552 * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to 553 * OpenPIC inputs 9-12. PCI INTs A-D from the on board P2P bridge 554 * are routed to OpenPIC inputs 5-8. These values are offset by 555 * 16 in the table to reflect the Linux kernel interrupt value. 556 */ 557struct powerplus_irq_list Powerplus_pci_IRQ_list = 558{ 559 {25, 26, 27, 28}, 560 {21, 22, 23, 24} 561}; 562 563/* 564 * For the MCP750 (system slot board), cPCI INTs A-D are routed to 565 * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC 566 * input 3. On a hot swap MCP750, the companion card PCI INTs A-D 567 * are routed to OpenPIC inputs 12-15. These values are offset by 568 * 16 in the table to reflect the Linux kernel interrupt value. 569 */ 570struct powerplus_irq_list Mesquite_pci_IRQ_list = 571{ 572 {24, 25, 26, 27}, 573 {28, 29, 30, 31} 574}; 575 576/* 577 * This table represents the standard PCI swizzle defined in the 578 * PCI bus specification. 579 */ 580static unsigned char prep_pci_intpins[4][4] = 581{ 582 { 1, 2, 3, 4}, /* Buses 0, 4, 8, ... */ 583 { 2, 3, 4, 1}, /* Buses 1, 5, 9, ... */ 584 { 3, 4, 1, 2}, /* Buses 2, 6, 10 ... */ 585 { 4, 1, 2, 3}, /* Buses 3, 7, 11 ... */ 586}; 587 588/* We have to turn on LEVEL mode for changed IRQs */ 589/* All PCI IRQs need to be level mode, so this should be something 590 * other than hard-coded as well... IRQs are individually mappable 591 * to either edge or level. 592 */ 593 594/* 595 * 8259 edge/level control definitions 596 */ 597#define ISA8259_M_ELCR 0x4d0 598#define ISA8259_S_ELCR 0x4d1 599 600#define ELCRS_INT15_LVL 0x80 601#define ELCRS_INT14_LVL 0x40 602#define ELCRS_INT12_LVL 0x10 603#define ELCRS_INT11_LVL 0x08 604#define ELCRS_INT10_LVL 0x04 605#define ELCRS_INT9_LVL 0x02 606#define ELCRS_INT8_LVL 0x01 607#define ELCRM_INT7_LVL 0x80 608#define ELCRM_INT5_LVL 0x20 609 610 611#define MOTOROLA_CPUTYPE_REG 0x800 612#define MOTOROLA_BASETYPE_REG 0x803 613#define MPIC_RAVEN_ID 0x48010000 614#define MPIC_HAWK_ID 0x48030000 615#define MOT_PROC2_BIT 0x800 616 617static u_char prep_openpic_initsenses[] __initdata = { 618 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */ 619 (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCN_ECC_ERR */ 620 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */ 621 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */ 622 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */ 623 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */ 624 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */ 625 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */ 626 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */ 627 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */ 628 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */ 629 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */ 630 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */ 631 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */ 632 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */ 633}; 634 635#define MOT_RAVEN_PRESENT 0x1 636#define MOT_HAWK_PRESENT 0x2 637 638int mot_entry = -1; 639int prep_keybd_present = 1; 640int MotMPIC; 641int mot_multi; 642 643int __init 644raven_init(void) 645{ 646 unsigned int devid; 647 unsigned int pci_membase; 648 unsigned char base_mod; 649 650 /* Check to see if the Raven chip exists. */ 651 if ( _prep_type != _PREP_Motorola) { 652 OpenPIC_Addr = NULL; 653 return 0; 654 } 655 656 /* Check to see if this board is a type that might have a Raven. */ 657 if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) { 658 OpenPIC_Addr = NULL; 659 return 0; 660 } 661 662 /* Check the first PCI device to see if it is a Raven. */ 663 early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &devid); 664 665 switch (devid & 0xffff0000) { 666 case MPIC_RAVEN_ID: 667 MotMPIC = MOT_RAVEN_PRESENT; 668 break; 669 case MPIC_HAWK_ID: 670 MotMPIC = MOT_HAWK_PRESENT; 671 break; 672 default: 673 OpenPIC_Addr = NULL; 674 return 0; 675 } 676 677 678 /* Read the memory base register. */ 679 early_read_config_dword(NULL, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase); 680 681 if (pci_membase == 0) { 682 OpenPIC_Addr = NULL; 683 return 0; 684 } 685 686 /* Map the Raven MPIC registers to virtual memory. */ 687 OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000); 688 689 OpenPIC_InitSenses = prep_openpic_initsenses; 690 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); 691 692 ppc_md.get_irq = openpic_get_irq; 693 694 /* If raven is present on Motorola store the system config register 695 * for later use. 696 */ 697 ProcInfo = (unsigned long *)ioremap(0xfef80400, 4); 698 699 /* Indicate to system if this is a multiprocessor board */ 700 if (!(*ProcInfo & MOT_PROC2_BIT)) { 701 mot_multi = 1; 702 } 703 704 /* This is a hack. If this is a 2300 or 2400 mot board then there is 705 * no keyboard controller and we have to indicate that. 706 */ 707 base_mod = inb(MOTOROLA_BASETYPE_REG); 708 if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) || 709 (base_mod == 0xFA) || (base_mod == 0xE1)) 710 prep_keybd_present = 0; 711 712 return 1; 713} 714 715struct mot_info { 716 int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */ 717 /* 0x200 if this board has a Hawk chip. */ 718 int base_type; 719 int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */ 720 const char *name; 721 unsigned char *map; 722 unsigned char *routes; 723 void (*map_non0_bus)(struct pci_dev *); /* For boards with more than bus 0 devices. */ 724 struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */ 725 unsigned char secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */ 726} mot_info[] = { 727 {0x300, 0x00, 0x00, "MVME 2400", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 728 {0x010, 0x00, 0x00, "Genesis", Genesis_pci_IRQ_map, Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, 729 {0x020, 0x00, 0x00, "Powerstack (Series E)", Comet_pci_IRQ_map, Comet_pci_IRQ_routes, NULL, NULL, 0x00}, 730 {0x040, 0x00, 0x00, "Blackhawk (Powerstack)", Blackhawk_pci_IRQ_map, Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00}, 731 {0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)", Omaha_pci_IRQ_map, Omaha_pci_IRQ_routes, NULL, NULL, 0x00}, 732 {0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)", Utah_pci_IRQ_map, Utah_pci_IRQ_routes, NULL, NULL, 0x00}, 733 {0x0A0, 0x00, 0x00, "Powerstack (Series EX)", Comet2_pci_IRQ_map, Comet2_pci_IRQ_routes, NULL, NULL, 0x00}, 734 {0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF}, 735 {0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", Sitka_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 736 {0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", Mesquite_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0}, 737 {0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0}, 738 {0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0}, 739 {0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, 740 {0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, 741 {0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, 742 {0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, 743 {0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 744 {0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 745 {0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 746 {0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 747 {0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00}, 748 {0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 749 {0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 750 {0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 751 {0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011", Genesis2_pci_IRQ_map, Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF}, 752 {0x000, 0x00, 0x00, "", NULL, NULL, NULL, NULL, 0x00} 753}; 754 755void __init 756ibm_prep_init(void) 757{ 758 if (have_residual_data) { 759 u32 addr, real_addr, len, offset; 760 PPC_DEVICE *mpic; 761 PnP_TAG_PACKET *pkt; 762 763 /* Use the PReP residual data to determine if an OpenPIC is 764 * present. If so, get the large vendor packet which will 765 * tell us the base address and length in memory. 766 * If we are successful, ioremap the memory area and set 767 * OpenPIC_Addr (this indicates that the OpenPIC was found). 768 */ 769 mpic = residual_find_device(-1, NULL, SystemPeripheral, 770 ProgrammableInterruptController, MPIC, 0); 771 if (!mpic) 772 return; 773 774 pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap + 775 mpic->AllocatedOffset, 9, 0); 776 777 if (!pkt) 778 return; 779 780#define p pkt->L4_Pack.L4_Data.L4_PPCPack 781 if (p.PPCData[1] == 32) { 782 switch (p.PPCData[0]) { 783 case 1: offset = PREP_ISA_IO_BASE; break; 784 case 2: offset = PREP_ISA_MEM_BASE; break; 785 default: return; /* Not I/O or memory?? */ 786 } 787 } 788 else 789 return; /* Not a 32-bit address */ 790 791 real_addr = ld_le32((unsigned int *) (p.PPCData + 4)); 792 if (real_addr == 0xffffffff) 793 return; 794 795 /* Adjust address to be as seen by CPU */ 796 addr = real_addr + offset; 797 798 len = ld_le32((unsigned int *) (p.PPCData + 12)); 799 if (!len) 800 return; 801#undef p 802 OpenPIC_Addr = ioremap(addr, len); 803 ppc_md.get_irq = openpic_get_irq; 804 805 OpenPIC_InitSenses = prep_openpic_initsenses; 806 OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses); 807 808 printk(KERN_INFO "MPIC at 0x%08x (0x%08x), length 0x%08x " 809 "mapped to 0x%p\n", addr, real_addr, len, OpenPIC_Addr); 810 } 811} 812 813static void __init 814ibm43p_pci_map_non0(struct pci_dev *dev) 815{ 816 unsigned char intpin; 817 static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 }; 818 819 if (dev == NULL) 820 return; 821 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin); 822 if (intpin < 1 || intpin > 4) 823 return; 824 intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3; 825 dev->irq = openpic_to_irq(bridge_intrs[intpin]); 826 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 827} 828 829void __init 830prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) 831{ 832 if (have_residual_data) { 833 Motherboard_map_name = res->VitalProductData.PrintableModel; 834 Motherboard_map = NULL; 835 Motherboard_routes = NULL; 836 residual_irq_mask(irq_edge_mask_lo, irq_edge_mask_hi); 837 } 838} 839 840void __init 841prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) 842{ 843 Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)"; 844 Motherboard_map = ibm6015_pci_IRQ_map; 845 Motherboard_routes = ibm6015_pci_IRQ_routes; 846 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 847 *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ 848} 849 850void __init 851prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) 852{ 853 Motherboard_map_name = "IBM Thinkpad 850/860"; 854 Motherboard_map = Nobis_pci_IRQ_map; 855 Motherboard_routes = Nobis_pci_IRQ_routes; 856 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 857 *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ 858} 859 860void __init 861prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) 862{ 863 Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)"; 864 Motherboard_map = ibm8xx_pci_IRQ_map; 865 Motherboard_routes = ibm8xx_pci_IRQ_routes; 866 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 867 *irq_edge_mask_hi = 0xA4; /* IRQs 10, 13, 15 level-triggered */ 868} 869 870void __init 871prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi) 872{ 873 Motherboard_map_name = "IBM 43P-140 (Tiger1)"; 874 Motherboard_map = ibm43p_pci_IRQ_map; 875 Motherboard_routes = ibm43p_pci_IRQ_routes; 876 Motherboard_non0 = ibm43p_pci_map_non0; 877 *irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */ 878 *irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */ 879} 880 881void __init 882prep_route_pci_interrupts(void) 883{ 884 unsigned char *ibc_pirq = (unsigned char *)0x80800860; 885 unsigned char *ibc_pcicon = (unsigned char *)0x80800840; 886 int i; 887 888 if ( _prep_type == _PREP_Motorola) 889 { 890 unsigned short irq_mode; 891 unsigned char cpu_type; 892 unsigned char base_mod; 893 int entry; 894 895 cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0; 896 base_mod = inb(MOTOROLA_BASETYPE_REG); 897 898 for (entry = 0; mot_info[entry].cpu_type != 0; entry++) { 899 if (mot_info[entry].cpu_type & 0x200) { /* Check for Hawk chip */ 900 if (!(MotMPIC & MOT_HAWK_PRESENT)) 901 continue; 902 } else { /* Check non hawk boards */ 903 if ((mot_info[entry].cpu_type & 0xff) != cpu_type) 904 continue; 905 906 if (mot_info[entry].base_type == 0) { 907 mot_entry = entry; 908 break; 909 } 910 911 if (mot_info[entry].base_type != base_mod) 912 continue; 913 } 914 915 if (!(mot_info[entry].max_cpu & 0x80)) { 916 mot_entry = entry; 917 break; 918 } 919 920 /* processor 1 not present and max processor zero indicated */ 921 if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) { 922 mot_entry = entry; 923 break; 924 } 925 926 /* processor 1 present and max processor zero indicated */ 927 if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) { 928 mot_entry = entry; 929 break; 930 } 931 } 932 933 if (mot_entry == -1) /* No particular cpu type found - assume Blackhawk */ 934 mot_entry = 3; 935 936 Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name; 937 Motherboard_map = mot_info[mot_entry].map; 938 Motherboard_routes = mot_info[mot_entry].routes; 939 Motherboard_non0 = mot_info[mot_entry].map_non0_bus; 940 941 if (!(mot_info[entry].cpu_type & 0x100)) { 942 /* AJF adjust level/edge control according to routes */ 943 irq_mode = 0; 944 for (i = 1; i <= 4; i++) 945 irq_mode |= ( 1 << Motherboard_routes[i] ); 946 outb( irq_mode & 0xff, 0x4d0 ); 947 outb( (irq_mode >> 8) & 0xff, 0x4d1 ); 948 } 949 } else if ( _prep_type == _PREP_IBM ) { 950 unsigned char irq_edge_mask_lo, irq_edge_mask_hi; 951 unsigned short irq_edge_mask; 952 int i; 953 954 setup_ibm_pci(&irq_edge_mask_lo, &irq_edge_mask_hi); 955 956 outb(inb(0x04d0)|irq_edge_mask_lo, 0x4d0); /* primary 8259 */ 957 outb(inb(0x04d1)|irq_edge_mask_hi, 0x4d1); /* cascaded 8259 */ 958 959 irq_edge_mask = (irq_edge_mask_hi << 8) | irq_edge_mask_lo; 960 for (i = 0; i < 16; ++i, irq_edge_mask >>= 1) 961 if (irq_edge_mask & 1) 962 irq_desc[i].status |= IRQ_LEVEL; 963 } else { 964 printk("No known machine pci routing!\n"); 965 return; 966 } 967 968 /* Set up mapping from slots */ 969 if (Motherboard_routes) { 970 for (i = 1; i <= 4; i++) 971 ibc_pirq[i-1] = Motherboard_routes[i]; 972 973 /* Enable PCI interrupts */ 974 *ibc_pcicon |= 0x20; 975 } 976} 977 978void __init 979prep_pib_init(void) 980{ 981 unsigned char reg; 982 unsigned short short_reg; 983 984 struct pci_dev *dev = NULL; 985 986 if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) { 987 /* 988 * Perform specific configuration for the Via Tech or 989 * or Winbond PCI-ISA-Bridge part. 990 */ 991 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, 992 PCI_DEVICE_ID_VIA_82C586_1, dev))) { 993 /* 994 * PPCBUG does not set the enable bits 995 * for the IDE device. Force them on here. 996 */ 997 pci_read_config_byte(dev, 0x40, ®); 998 999 reg |= 0x03; /* IDE: Chip Enable Bits */ 1000 pci_write_config_byte(dev, 0x40, reg); 1001 } 1002 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, 1003 PCI_DEVICE_ID_VIA_82C586_2, 1004 dev)) && (dev->devfn = 0x5a)) { 1005 /* Force correct USB interrupt */ 1006 dev->irq = 11; 1007 pci_write_config_byte(dev, 1008 PCI_INTERRUPT_LINE, 1009 dev->irq); 1010 } 1011 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, 1012 PCI_DEVICE_ID_WINBOND_83C553, dev))) { 1013 /* Clear PCI Interrupt Routing Control Register. */ 1014 short_reg = 0x0000; 1015 pci_write_config_word(dev, 0x44, short_reg); 1016 if (OpenPIC_Addr){ 1017 /* Route IDE interrupts to IRQ 14 */ 1018 reg = 0xEE; 1019 pci_write_config_byte(dev, 0x43, reg); 1020 } 1021 } 1022 pci_dev_put(dev); 1023 } 1024 1025 if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND, 1026 PCI_DEVICE_ID_WINBOND_82C105, dev))){ 1027 if (OpenPIC_Addr){ 1028 /* 1029 * Disable LEGIRQ mode so PCI INTS are routed 1030 * directly to the 8259 and enable both channels 1031 */ 1032 pci_write_config_dword(dev, 0x40, 0x10ff0033); 1033 1034 /* Force correct IDE interrupt */ 1035 dev->irq = 14; 1036 pci_write_config_byte(dev, 1037 PCI_INTERRUPT_LINE, 1038 dev->irq); 1039 } else { 1040 /* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */ 1041 pci_write_config_dword(dev, 0x40, 0x10ff08a1); 1042 } 1043 } 1044 pci_dev_put(dev); 1045} 1046 1047static void __init 1048Powerplus_Map_Non0(struct pci_dev *dev) 1049{ 1050 struct pci_bus *pbus; /* Parent bus structure pointer */ 1051 struct pci_dev *tdev = dev; /* Temporary device structure */ 1052 unsigned int devnum; /* Accumulated device number */ 1053 unsigned char intline; /* Linux interrupt value */ 1054 unsigned char intpin; /* PCI interrupt pin */ 1055 1056 /* Check for valid PCI dev pointer */ 1057 if (dev == NULL) return; 1058 1059 /* Initialize bridge IDSEL variable */ 1060 devnum = PCI_SLOT(tdev->devfn); 1061 1062 /* Read the interrupt pin of the device and adjust for indexing */ 1063 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin); 1064 1065 /* If device doesn't request an interrupt, return */ 1066 if ( (intpin < 1) || (intpin > 4) ) 1067 return; 1068 1069 intpin--; 1070 1071 /* 1072 * Walk up to bus 0, adjusting the interrupt pin for the standard 1073 * PCI bus swizzle. 1074 */ 1075 do { 1076 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1; 1077 pbus = tdev->bus; /* up one level */ 1078 tdev = pbus->self; 1079 devnum = PCI_SLOT(tdev->devfn); 1080 } while(tdev->bus->number); 1081 1082 /* Use the primary interrupt inputs by default */ 1083 intline = mot_info[mot_entry].pci_irq_list->primary[intpin]; 1084 1085 /* 1086 * If the board has secondary interrupt inputs, walk the bus and 1087 * note the devfn of the bridge from bus 0. If it is the same as 1088 * the devfn of the bus bridge with secondary inputs, use those. 1089 * Otherwise, assume it's a PMC site and get the interrupt line 1090 * value from the interrupt routing table. 1091 */ 1092 if (mot_info[mot_entry].secondary_bridge_devfn) { 1093 pbus = dev->bus; 1094 1095 while (pbus->primary != 0) 1096 pbus = pbus->parent; 1097 1098 if ((pbus->self)->devfn != 0xA0) { 1099 if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn) 1100 intline = mot_info[mot_entry].pci_irq_list->secondary[intpin]; 1101 else { 1102 if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map) 1103 intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16; 1104 else { 1105 int i; 1106 for (i=0;i<3;i++) 1107 intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1; 1108 intline = mot_info[mot_entry].pci_irq_list->primary[intpin]; 1109 } 1110 } 1111 } 1112 } 1113 1114 /* Write calculated interrupt value to header and device list */ 1115 dev->irq = intline; 1116 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq); 1117} 1118 1119void __init 1120prep_pcibios_fixup(void) 1121{ 1122 struct pci_dev *dev = NULL; 1123 int irq; 1124 int have_openpic = (OpenPIC_Addr != NULL); 1125 1126 prep_route_pci_interrupts(); 1127 1128 printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name); 1129 1130 /* Iterate through all the PCI devices, setting the IRQ */ 1131 for_each_pci_dev(dev) { 1132 /* 1133 * If we have residual data, then this is easy: query the 1134 * residual data for the IRQ line allocated to the device. 1135 * This works the same whether we have an OpenPic or not. 1136 */ 1137 if (have_residual_data) { 1138 irq = residual_pcidev_irq(dev); 1139 dev->irq = have_openpic ? openpic_to_irq(irq) : irq; 1140 } 1141 /* 1142 * If we don't have residual data, then we need to use 1143 * tables to determine the IRQ. The table organisation 1144 * is different depending on whether there is an OpenPIC 1145 * or not. The tables are only used for bus 0, so check 1146 * this first. 1147 */ 1148 else if (dev->bus->number == 0) { 1149 irq = Motherboard_map[PCI_SLOT(dev->devfn)]; 1150 dev->irq = have_openpic ? openpic_to_irq(irq) 1151 : Motherboard_routes[irq]; 1152 } 1153 /* 1154 * Finally, if we don't have residual data and the bus is 1155 * non-zero, use the callback (if provided) 1156 */ 1157 else { 1158 if (Motherboard_non0 != NULL) 1159 Motherboard_non0(dev); 1160 1161 continue; 1162 } 1163 1164 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 1165 } 1166 1167 /* Setup the Winbond or Via PIB - prep_pib_init() is coded for 1168 * the non-openpic case, but it breaks (at least) the Utah 1169 * (Powerstack II Pro4000), so only call it if we have an 1170 * openpic. 1171 */ 1172 if (have_openpic) 1173 prep_pib_init(); 1174} 1175 1176static void __init 1177prep_pcibios_after_init(void) 1178{ 1179} 1180 1181static void __init 1182prep_init_resource(struct resource *res, unsigned long start, 1183 unsigned long end, int flags) 1184{ 1185 res->flags = flags; 1186 res->start = start; 1187 res->end = end; 1188 res->name = "PCI host bridge"; 1189 res->parent = NULL; 1190 res->sibling = NULL; 1191 res->child = NULL; 1192} 1193 1194void __init 1195prep_find_bridges(void) 1196{ 1197 struct pci_controller* hose; 1198 1199 hose = pcibios_alloc_controller(); 1200 if (!hose) 1201 return; 1202 1203 hose->first_busno = 0; 1204 hose->last_busno = 0xff; 1205 hose->pci_mem_offset = PREP_ISA_MEM_BASE; 1206 hose->io_base_phys = PREP_ISA_IO_BASE; 1207 hose->io_base_virt = ioremap(PREP_ISA_IO_BASE, 0x800000); 1208 prep_init_resource(&hose->io_resource, 0, 0x007fffff, IORESOURCE_IO); 1209 prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff, 1210 IORESOURCE_MEM); 1211 setup_indirect_pci(hose, PREP_ISA_IO_BASE + 0xcf8, 1212 PREP_ISA_IO_BASE + 0xcfc); 1213 1214 printk("PReP architecture\n"); 1215 1216 if (have_residual_data) { 1217 PPC_DEVICE *hostbridge; 1218 1219 hostbridge = residual_find_device(PROCESSORDEVICE, NULL, 1220 BridgeController, PCIBridge, -1, 0); 1221 if (hostbridge && 1222 ((hostbridge->DeviceId.Interface == PCIBridgeIndirect) || 1223 (hostbridge->DeviceId.Interface == PCIBridgeRS6K))) { 1224 PnP_TAG_PACKET * pkt; 1225 pkt = PnP_find_large_vendor_packet( 1226 res->DevicePnPHeap+hostbridge->AllocatedOffset, 1227 3, 0); 1228 if(pkt) { 1229#define p pkt->L4_Pack.L4_Data.L4_PPCPack 1230 setup_indirect_pci(hose, 1231 ld_le32((unsigned *) (p.PPCData)), 1232 ld_le32((unsigned *) (p.PPCData+8))); 1233#undef p 1234 } else 1235 setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc); 1236 } 1237 } 1238 1239 ppc_md.pcibios_fixup = prep_pcibios_fixup; 1240 ppc_md.pcibios_after_init = prep_pcibios_after_init; 1241} 1242