1 2/******************************************************************* 3* 4* CAUTION: This file is automatically generated by libgen. 5* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 6* DO NOT EDIT. 7* 8* Copyright (c) 2005 Xilinx, Inc. All rights reserved. 9* 10* Description: Driver parameters 11* 12*******************************************************************/ 13 14#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000 15#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF 16 17/******************************************************************/ 18 19#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000 20#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF 21#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000 22#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF 23#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 24#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF 25#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000 26#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF 27#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000 28#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF 29 30/******************************************************************/ 31 32#define XPAR_XEMAC_NUM_INSTANCES 1 33#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 34#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF 35#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 36#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 37#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 38#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 39 40/******************************************************************/ 41 42#define XPAR_XUARTNS550_NUM_INSTANCES 1 43#define XPAR_XUARTNS550_CLOCK_HZ 100000000 44#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 45#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF 46#define XPAR_OPB_UART16550_0_DEVICE_ID 0 47 48/******************************************************************/ 49 50#define XPAR_XGPIO_NUM_INSTANCES 3 51#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000 52#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF 53#define XPAR_OPB_GPIO_0_DEVICE_ID 0 54#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0 55#define XPAR_OPB_GPIO_0_IS_DUAL 1 56#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000 57#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF 58#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1 59#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0 60#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1 61#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000 62#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF 63#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2 64#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0 65#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0 66 67/******************************************************************/ 68 69#define XPAR_XPS2_NUM_INSTANCES 2 70#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 71#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 72#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) 73#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 74#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) 75#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) 76 77/******************************************************************/ 78 79#define XPAR_XIIC_NUM_INSTANCES 1 80#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 81#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF 82#define XPAR_OPB_IIC_0_DEVICE_ID 0 83#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 84#define XPAR_OPB_IIC_0_GPO_WIDTH 1 85 86/******************************************************************/ 87 88#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10 89#define XPAR_XINTC_HAS_IPR 1 90#define XPAR_XINTC_USE_DCR 0 91#define XPAR_XINTC_NUM_INSTANCES 1 92#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0 93#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF 94#define XPAR_OPB_INTC_0_DEVICE_ID 0 95#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000 96 97/******************************************************************/ 98 99#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0 100#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF 101#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID 102#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001 103#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0 104#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002 105#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1 106#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004 107#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2 108#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008 109#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3 110#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010 111#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4 112#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020 113#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5 114#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040 115#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6 116#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080 117#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7 118#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100 119#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 120#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200 121#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9 122 123/******************************************************************/ 124 125#define XPAR_XTFT_NUM_INSTANCES 1 126#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 127#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 128#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 129 130/******************************************************************/ 131 132#define XPAR_XSYSACE_MEM_WIDTH 16 133#define XPAR_XSYSACE_NUM_INSTANCES 1 134#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 135#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF 136#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 137#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16 138 139/******************************************************************/ 140 141#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 142 143/******************************************************************/ 144 145 146/******************************************************************/ 147 148/* Linux Redefines */ 149 150/******************************************************************/ 151 152#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) 153#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR 154#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ 155#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID 156 157/******************************************************************/ 158 159#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR 160#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR 161#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR 162#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID 163 164/******************************************************************/ 165 166#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 167#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 168#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 169#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 170#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 171#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 172 173/******************************************************************/ 174 175#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 176 177/******************************************************************/ 178 179#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR 180#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR 181#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT 182#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST 183#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 184#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID 185 186/******************************************************************/ 187 188#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0 189#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0 190#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0 191#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1 192#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1 193#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1 194#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0 195#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0 196#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0 197#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1 198#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1 199#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1 200#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 201#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 202#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 203 204/******************************************************************/ 205 206#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 207#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 208#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 209#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 210#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 211#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 212 213/******************************************************************/ 214 215#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR 216#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR 217#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID 218 219/******************************************************************/ 220 221#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR 222#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR 223#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR 224#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID 225 226/******************************************************************/ 227 228#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 229#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 230#define XPAR_DDR_0_SIZE 0x4000000 231 232/******************************************************************/ 233 234#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 235#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF 236#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 237 238/******************************************************************/ 239 240#define XPAR_PCI_0_CLOCK_FREQ_HZ 0 241 242/******************************************************************/ 243