1/*
2 * arch/powerpc/sysdev/uic.c
3 *
4 * IBM PowerPC 4xx Universal Interrupt Controller
5 *
6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
7 *
8 * This program is free software; you can redistribute  it and/or modify it
9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <asm/irq.h>
28#include <asm/io.h>
29#include <asm/prom.h>
30#include <asm/dcr.h>
31
32#define NR_UIC_INTS	32
33
34#define UIC_SR		0x0
35#define UIC_ER		0x2
36#define UIC_CR		0x3
37#define UIC_PR		0x4
38#define UIC_TR		0x5
39#define UIC_MSR		0x6
40#define UIC_VR		0x7
41#define UIC_VCR		0x8
42
43#define uic_irq_to_hw(virq)	(irq_map[virq].hwirq)
44
45struct uic *primary_uic;
46
47struct uic {
48	int index;
49	int dcrbase;
50
51	spinlock_t lock;
52
53	/* The remapper for this UIC */
54	struct irq_host	*irqhost;
55
56	/* For secondary UICs, the cascade interrupt's irqaction */
57	struct irqaction cascade;
58
59	/* The device node of the interrupt controller */
60	struct device_node *of_node;
61};
62
63static void uic_unmask_irq(unsigned int virq)
64{
65	struct uic *uic = get_irq_chip_data(virq);
66	unsigned int src = uic_irq_to_hw(virq);
67	unsigned long flags;
68	u32 er;
69
70	spin_lock_irqsave(&uic->lock, flags);
71	er = mfdcr(uic->dcrbase + UIC_ER);
72	er |= 1 << (31 - src);
73	mtdcr(uic->dcrbase + UIC_ER, er);
74	spin_unlock_irqrestore(&uic->lock, flags);
75}
76
77static void uic_mask_irq(unsigned int virq)
78{
79	struct uic *uic = get_irq_chip_data(virq);
80	unsigned int src = uic_irq_to_hw(virq);
81	unsigned long flags;
82	u32 er;
83
84	spin_lock_irqsave(&uic->lock, flags);
85	er = mfdcr(uic->dcrbase + UIC_ER);
86	er &= ~(1 << (31 - src));
87	mtdcr(uic->dcrbase + UIC_ER, er);
88	spin_unlock_irqrestore(&uic->lock, flags);
89}
90
91static void uic_ack_irq(unsigned int virq)
92{
93	struct uic *uic = get_irq_chip_data(virq);
94	unsigned int src = uic_irq_to_hw(virq);
95	unsigned long flags;
96
97	spin_lock_irqsave(&uic->lock, flags);
98	mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
99	spin_unlock_irqrestore(&uic->lock, flags);
100}
101
102static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
103{
104	struct uic *uic = get_irq_chip_data(virq);
105	unsigned int src = uic_irq_to_hw(virq);
106	struct irq_desc *desc = get_irq_desc(virq);
107	unsigned long flags;
108	int trigger, polarity;
109	u32 tr, pr, mask;
110
111	switch (flow_type & IRQ_TYPE_SENSE_MASK) {
112	case IRQ_TYPE_NONE:
113		uic_mask_irq(virq);
114		return 0;
115
116	case IRQ_TYPE_EDGE_RISING:
117		trigger = 1; polarity = 1;
118		break;
119	case IRQ_TYPE_EDGE_FALLING:
120		trigger = 1; polarity = 0;
121		break;
122	case IRQ_TYPE_LEVEL_HIGH:
123		trigger = 0; polarity = 1;
124		break;
125	case IRQ_TYPE_LEVEL_LOW:
126		trigger = 0; polarity = 0;
127		break;
128	default:
129		return -EINVAL;
130	}
131
132	mask = ~(1 << (31 - src));
133
134	spin_lock_irqsave(&uic->lock, flags);
135	tr = mfdcr(uic->dcrbase + UIC_TR);
136	pr = mfdcr(uic->dcrbase + UIC_PR);
137	tr = (tr & mask) | (trigger << (31-src));
138	pr = (pr & mask) | (polarity << (31-src));
139
140	mtdcr(uic->dcrbase + UIC_PR, pr);
141	mtdcr(uic->dcrbase + UIC_TR, tr);
142
143	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
144	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
145	if (trigger)
146		desc->status |= IRQ_LEVEL;
147
148	spin_unlock_irqrestore(&uic->lock, flags);
149
150	return 0;
151}
152
153static struct irq_chip uic_irq_chip = {
154	.typename	= " UIC  ",
155	.unmask		= uic_unmask_irq,
156	.mask		= uic_mask_irq,
157/* 	.mask_ack	= uic_mask_irq_and_ack, */
158	.ack		= uic_ack_irq,
159	.set_type	= uic_set_irq_type,
160};
161
162static int uic_host_match(struct irq_host *h, struct device_node *node)
163{
164	struct uic *uic = h->host_data;
165	return uic->of_node == node;
166}
167
168static int uic_host_map(struct irq_host *h, unsigned int virq,
169			irq_hw_number_t hw)
170{
171	struct uic *uic = h->host_data;
172
173	set_irq_chip_data(virq, uic);
174	set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
175
176	/* Set default irq type */
177	set_irq_type(virq, IRQ_TYPE_NONE);
178
179	return 0;
180}
181
182static int uic_host_xlate(struct irq_host *h, struct device_node *ct,
183			  u32 *intspec, unsigned int intsize,
184			  irq_hw_number_t *out_hwirq, unsigned int *out_type)
185
186{
187	/* UIC intspecs must have 2 cells */
188	BUG_ON(intsize != 2);
189	*out_hwirq = intspec[0];
190	*out_type = intspec[1];
191	return 0;
192}
193
194static struct irq_host_ops uic_host_ops = {
195	.match	= uic_host_match,
196	.map	= uic_host_map,
197	.xlate	= uic_host_xlate,
198};
199
200irqreturn_t uic_cascade(int virq, void *data)
201{
202	struct uic *uic = data;
203	u32 msr;
204	int src;
205	int subvirq;
206
207	msr = mfdcr(uic->dcrbase + UIC_MSR);
208	src = 32 - ffs(msr);
209
210	subvirq = irq_linear_revmap(uic->irqhost, src);
211	generic_handle_irq(subvirq);
212
213	return IRQ_HANDLED;
214}
215
216static struct uic * __init uic_init_one(struct device_node *node)
217{
218	struct uic *uic;
219	const u32 *indexp, *dcrreg;
220	int len;
221
222	BUG_ON(! of_device_is_compatible(node, "ibm,uic"));
223
224	uic = alloc_bootmem(sizeof(*uic));
225	if (! uic)
226		return NULL;
227
228	memset(uic, 0, sizeof(*uic));
229	spin_lock_init(&uic->lock);
230	uic->of_node = of_node_get(node);
231	indexp = of_get_property(node, "cell-index", &len);
232	if (!indexp || (len != sizeof(u32))) {
233		printk(KERN_ERR "uic: Device node %s has missing or invalid "
234		       "cell-index property\n", node->full_name);
235		return NULL;
236	}
237	uic->index = *indexp;
238
239	dcrreg = of_get_property(node, "dcr-reg", &len);
240	if (!dcrreg || (len != 2*sizeof(u32))) {
241		printk(KERN_ERR "uic: Device node %s has missing or invalid "
242		       "dcr-reg property\n", node->full_name);
243		return NULL;
244	}
245	uic->dcrbase = *dcrreg;
246
247	uic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, NR_UIC_INTS,
248				      &uic_host_ops, -1);
249	if (! uic->irqhost) {
250		of_node_put(node);
251		return NULL;
252	}
253
254	uic->irqhost->host_data = uic;
255
256	/* Start with all interrupts disabled, level and non-critical */
257	mtdcr(uic->dcrbase + UIC_ER, 0);
258	mtdcr(uic->dcrbase + UIC_CR, 0);
259	mtdcr(uic->dcrbase + UIC_TR, 0);
260	/* Clear any pending interrupts, in case the firmware left some */
261	mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
262
263	printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index,
264		NR_UIC_INTS, uic->dcrbase);
265
266	return uic;
267}
268
269void __init uic_init_tree(void)
270{
271	struct device_node *np;
272	struct uic *uic;
273	const u32 *interrupts;
274
275	/* First locate and initialize the top-level UIC */
276
277	np = of_find_compatible_node(NULL, NULL, "ibm,uic");
278	while (np) {
279		interrupts = of_get_property(np, "interrupts", NULL);
280		if (! interrupts)
281			break;
282
283		np = of_find_compatible_node(np, NULL, "ibm,uic");
284	}
285
286	BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
287		      * top-level interrupt controller */
288	primary_uic = uic_init_one(np);
289	if (! primary_uic)
290		panic("Unable to initialize primary UIC %s\n", np->full_name);
291
292	irq_set_default_host(primary_uic->irqhost);
293	of_node_put(np);
294
295	/* The scan again for cascaded UICs */
296	np = of_find_compatible_node(NULL, NULL, "ibm,uic");
297	while (np) {
298		interrupts = of_get_property(np, "interrupts", NULL);
299		if (interrupts) {
300			/* Secondary UIC */
301			int cascade_virq;
302			int ret;
303
304			uic = uic_init_one(np);
305			if (! uic)
306				panic("Unable to initialize a secondary UIC %s\n",
307				      np->full_name);
308
309			cascade_virq = irq_of_parse_and_map(np, 0);
310
311			uic->cascade.handler = uic_cascade;
312			uic->cascade.name = "UIC cascade";
313			uic->cascade.dev_id = uic;
314
315			ret = setup_irq(cascade_virq, &uic->cascade);
316			if (ret)
317				printk(KERN_ERR "Failed to setup_irq(%d) for "
318				       "UIC%d cascade\n", cascade_virq,
319				       uic->index);
320
321		}
322
323		np = of_find_compatible_node(np, NULL, "ibm,uic");
324	}
325}
326
327/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
328unsigned int uic_get_irq(void)
329{
330	u32 msr;
331	int src;
332
333	BUG_ON(! primary_uic);
334
335	msr = mfdcr(primary_uic->dcrbase + UIC_MSR);
336	src = 32 - ffs(msr);
337
338	return irq_linear_revmap(primary_uic->irqhost, src);
339}
340