1/* 2 * External Interrupt Controller on Spider South Bridge 3 * 4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 5 * 6 * Author: Arnd Bergmann <arndb@de.ibm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/interrupt.h> 24#include <linux/irq.h> 25#include <linux/ioport.h> 26 27#include <asm/pgtable.h> 28#include <asm/prom.h> 29#include <asm/io.h> 30 31#include "interrupt.h" 32 33/* register layout taken from Spider spec, table 7.4-4 */ 34enum { 35 TIR_DEN = 0x004, /* Detection Enable Register */ 36 TIR_MSK = 0x084, /* Mask Level Register */ 37 TIR_EDC = 0x0c0, /* Edge Detection Clear Register */ 38 TIR_PNDA = 0x100, /* Pending Register A */ 39 TIR_PNDB = 0x104, /* Pending Register B */ 40 TIR_CS = 0x144, /* Current Status Register */ 41 TIR_LCSA = 0x150, /* Level Current Status Register A */ 42 TIR_LCSB = 0x154, /* Level Current Status Register B */ 43 TIR_LCSC = 0x158, /* Level Current Status Register C */ 44 TIR_LCSD = 0x15c, /* Level Current Status Register D */ 45 TIR_CFGA = 0x200, /* Setting Register A0 */ 46 TIR_CFGB = 0x204, /* Setting Register B0 */ 47 /* 0x208 ... 0x3ff Setting Register An/Bn */ 48 TIR_PPNDA = 0x400, /* Packet Pending Register A */ 49 TIR_PPNDB = 0x404, /* Packet Pending Register B */ 50 TIR_PIERA = 0x408, /* Packet Output Error Register A */ 51 TIR_PIERB = 0x40c, /* Packet Output Error Register B */ 52 TIR_PIEN = 0x444, /* Packet Output Enable Register */ 53 TIR_PIPND = 0x454, /* Packet Output Pending Register */ 54 TIRDID = 0x484, /* Spider Device ID Register */ 55 REISTIM = 0x500, /* Reissue Command Timeout Time Setting */ 56 REISTIMEN = 0x504, /* Reissue Command Timeout Setting */ 57 REISWAITEN = 0x508, /* Reissue Wait Control*/ 58}; 59 60#define SPIDER_CHIP_COUNT 4 61#define SPIDER_SRC_COUNT 64 62#define SPIDER_IRQ_INVALID 63 63 64struct spider_pic { 65 struct irq_host *host; 66 struct device_node *of_node; 67 void __iomem *regs; 68 unsigned int node_id; 69}; 70static struct spider_pic spider_pics[SPIDER_CHIP_COUNT]; 71 72static struct spider_pic *spider_virq_to_pic(unsigned int virq) 73{ 74 return irq_map[virq].host->host_data; 75} 76 77static void __iomem *spider_get_irq_config(struct spider_pic *pic, 78 unsigned int src) 79{ 80 return pic->regs + TIR_CFGA + 8 * src; 81} 82 83static void spider_unmask_irq(unsigned int virq) 84{ 85 struct spider_pic *pic = spider_virq_to_pic(virq); 86 void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq); 87 88 out_be32(cfg, in_be32(cfg) | 0x30000000u); 89} 90 91static void spider_mask_irq(unsigned int virq) 92{ 93 struct spider_pic *pic = spider_virq_to_pic(virq); 94 void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq); 95 96 out_be32(cfg, in_be32(cfg) & ~0x30000000u); 97} 98 99static void spider_ack_irq(unsigned int virq) 100{ 101 struct spider_pic *pic = spider_virq_to_pic(virq); 102 unsigned int src = irq_map[virq].hwirq; 103 104 /* Reset edge detection logic if necessary 105 */ 106 if (get_irq_desc(virq)->status & IRQ_LEVEL) 107 return; 108 109 /* Only interrupts 47 to 50 can be set to edge */ 110 if (src < 47 || src > 50) 111 return; 112 113 /* Perform the clear of the edge logic */ 114 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); 115} 116 117static int spider_set_irq_type(unsigned int virq, unsigned int type) 118{ 119 unsigned int sense = type & IRQ_TYPE_SENSE_MASK; 120 struct spider_pic *pic = spider_virq_to_pic(virq); 121 unsigned int hw = irq_map[virq].hwirq; 122 void __iomem *cfg = spider_get_irq_config(pic, hw); 123 struct irq_desc *desc = get_irq_desc(virq); 124 u32 old_mask; 125 u32 ic; 126 127 /* Note that only level high is supported for most interrupts */ 128 if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH && 129 (hw < 47 || hw > 50)) 130 return -EINVAL; 131 132 /* Decode sense type */ 133 switch(sense) { 134 case IRQ_TYPE_EDGE_RISING: 135 ic = 0x3; 136 break; 137 case IRQ_TYPE_EDGE_FALLING: 138 ic = 0x2; 139 break; 140 case IRQ_TYPE_LEVEL_LOW: 141 ic = 0x0; 142 break; 143 case IRQ_TYPE_LEVEL_HIGH: 144 case IRQ_TYPE_NONE: 145 ic = 0x1; 146 break; 147 default: 148 return -EINVAL; 149 } 150 151 /* Update irq_desc */ 152 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 153 desc->status |= type & IRQ_TYPE_SENSE_MASK; 154 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 155 desc->status |= IRQ_LEVEL; 156 157 /* Configure the source. One gross hack that was there before and 158 * that I've kept around is the priority to the BE which I set to 159 * be the same as the interrupt source number. I don't know wether 160 * that's supposed to make any kind of sense however, we'll have to 161 * decide that, but for now, I'm not changing the behaviour. 162 */ 163 old_mask = in_be32(cfg) & 0x30000000u; 164 out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) | 165 (pic->node_id << 4) | 0xe); 166 out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff)); 167 168 return 0; 169} 170 171static struct irq_chip spider_pic = { 172 .typename = " SPIDER ", 173 .unmask = spider_unmask_irq, 174 .mask = spider_mask_irq, 175 .ack = spider_ack_irq, 176 .set_type = spider_set_irq_type, 177}; 178 179static int spider_host_match(struct irq_host *h, struct device_node *node) 180{ 181 struct spider_pic *pic = h->host_data; 182 return node == pic->of_node; 183} 184 185static int spider_host_map(struct irq_host *h, unsigned int virq, 186 irq_hw_number_t hw) 187{ 188 set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq); 189 190 /* Set default irq type */ 191 set_irq_type(virq, IRQ_TYPE_NONE); 192 193 return 0; 194} 195 196static int spider_host_xlate(struct irq_host *h, struct device_node *ct, 197 u32 *intspec, unsigned int intsize, 198 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 199 200{ 201 /* Spider interrupts have 2 cells, first is the interrupt source, 202 * second, well, I don't know for sure yet ... We mask the top bits 203 * because old device-trees encode a node number in there 204 */ 205 *out_hwirq = intspec[0] & 0x3f; 206 *out_flags = IRQ_TYPE_LEVEL_HIGH; 207 return 0; 208} 209 210static struct irq_host_ops spider_host_ops = { 211 .match = spider_host_match, 212 .map = spider_host_map, 213 .xlate = spider_host_xlate, 214}; 215 216static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) 217{ 218 struct spider_pic *pic = desc->handler_data; 219 unsigned int cs, virq; 220 221 cs = in_be32(pic->regs + TIR_CS) >> 24; 222 if (cs == SPIDER_IRQ_INVALID) 223 virq = NO_IRQ; 224 else 225 virq = irq_linear_revmap(pic->host, cs); 226 if (virq != NO_IRQ) 227 generic_handle_irq(virq); 228 desc->chip->eoi(irq); 229} 230 231/* For hooking up the cascace we have a problem. Our device-tree is 232 * crap and we don't know on which BE iic interrupt we are hooked on at 233 * least not the "standard" way. We can reconstitute it based on two 234 * informations though: which BE node we are connected to and wether 235 * we are connected to IOIF0 or IOIF1. Right now, we really only care 236 * about the IBM cell blade and we know that its firmware gives us an 237 * interrupt-map property which is pretty strange. 238 */ 239static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic) 240{ 241 unsigned int virq; 242 const u32 *imap, *tmp; 243 int imaplen, intsize, unit; 244 struct device_node *iic; 245 246 /* First, we check wether we have a real "interrupts" in the device 247 * tree in case the device-tree is ever fixed 248 */ 249 struct of_irq oirq; 250 if (of_irq_map_one(pic->of_node, 0, &oirq) == 0) { 251 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 252 oirq.size); 253 return virq; 254 } 255 256 /* Now do the horrible hacks */ 257 tmp = of_get_property(pic->of_node, "#interrupt-cells", NULL); 258 if (tmp == NULL) 259 return NO_IRQ; 260 intsize = *tmp; 261 imap = of_get_property(pic->of_node, "interrupt-map", &imaplen); 262 if (imap == NULL || imaplen < (intsize + 1)) 263 return NO_IRQ; 264 iic = of_find_node_by_phandle(imap[intsize]); 265 if (iic == NULL) 266 return NO_IRQ; 267 imap += intsize + 1; 268 tmp = of_get_property(iic, "#interrupt-cells", NULL); 269 if (tmp == NULL) 270 return NO_IRQ; 271 intsize = *tmp; 272 /* Assume unit is last entry of interrupt specifier */ 273 unit = imap[intsize - 1]; 274 /* Ok, we have a unit, now let's try to get the node */ 275 tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL); 276 if (tmp == NULL) { 277 of_node_put(iic); 278 return NO_IRQ; 279 } 280 /* ugly as hell but works for now */ 281 pic->node_id = (*tmp) >> 1; 282 of_node_put(iic); 283 284 /* Ok, now let's get cracking. You may ask me why I just didn't match 285 * the iic host from the iic OF node, but that way I'm still compatible 286 * with really really old old firmwares for which we don't have a node 287 */ 288 /* Manufacture an IIC interrupt number of class 2 */ 289 virq = irq_create_mapping(NULL, 290 (pic->node_id << IIC_IRQ_NODE_SHIFT) | 291 (2 << IIC_IRQ_CLASS_SHIFT) | 292 unit); 293 if (virq == NO_IRQ) 294 printk(KERN_ERR "spider_pic: failed to map cascade !"); 295 return virq; 296} 297 298 299static void __init spider_init_one(struct device_node *of_node, int chip, 300 unsigned long addr) 301{ 302 struct spider_pic *pic = &spider_pics[chip]; 303 int i, virq; 304 305 /* Map registers */ 306 pic->regs = ioremap(addr, 0x1000); 307 if (pic->regs == NULL) 308 panic("spider_pic: can't map registers !"); 309 310 /* Allocate a host */ 311 pic->host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, SPIDER_SRC_COUNT, 312 &spider_host_ops, SPIDER_IRQ_INVALID); 313 if (pic->host == NULL) 314 panic("spider_pic: can't allocate irq host !"); 315 pic->host->host_data = pic; 316 317 /* Fill out other bits */ 318 pic->of_node = of_node_get(of_node); 319 320 /* Go through all sources and disable them */ 321 for (i = 0; i < SPIDER_SRC_COUNT; i++) { 322 void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i; 323 out_be32(cfg, in_be32(cfg) & ~0x30000000u); 324 } 325 326 /* do not mask any interrupts because of level */ 327 out_be32(pic->regs + TIR_MSK, 0x0); 328 329 /* enable interrupt packets to be output */ 330 out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1); 331 332 /* Hook up the cascade interrupt to the iic and nodeid */ 333 virq = spider_find_cascade_and_node(pic); 334 if (virq == NO_IRQ) 335 return; 336 set_irq_data(virq, pic); 337 set_irq_chained_handler(virq, spider_irq_cascade); 338 339 printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", 340 pic->node_id, addr, of_node->full_name); 341 342 /* Enable the interrupt detection enable bit. Do this last! */ 343 out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1); 344} 345 346void __init spider_init_IRQ(void) 347{ 348 struct resource r; 349 struct device_node *dn; 350 int chip = 0; 351 352 for (dn = NULL; 353 (dn = of_find_node_by_name(dn, "interrupt-controller"));) { 354 if (of_device_is_compatible(dn, "CBEA,platform-spider-pic")) { 355 if (of_address_to_resource(dn, 0, &r)) { 356 printk(KERN_WARNING "spider-pic: Failed\n"); 357 continue; 358 } 359 } else if (of_device_is_compatible(dn, "sti,platform-spider-pic") 360 && (chip < 2)) { 361 static long hard_coded_pics[] = 362 { 0x24000008000ul, 0x34000008000ul}; 363 r.start = hard_coded_pics[chip]; 364 } else 365 continue; 366 spider_init_one(dn, chip++, r.start); 367 } 368} 369