1/* 2 * A collection of structures, addresses, and values associated with 3 * the Freescale MPC86xADS board. 4 * Copied from the FADS stuff. 5 * 6 * Author: MontaVista Software, Inc. 7 * source@mvista.com 8 * 9 * 2005 (c) MontaVista Software, Inc. This file is licensed under the 10 * terms of the GNU General Public License version 2. This program is licensed 11 * "as is" without any warranty of any kind, whether express or implied. 12 */ 13 14#ifdef __KERNEL__ 15#ifndef __ASM_MPC86XADS_H__ 16#define __ASM_MPC86XADS_H__ 17 18#include <asm/ppcboot.h> 19#include <sysdev/fsl_soc.h> 20 21/* U-Boot maps BCSR to 0xff080000 */ 22#define BCSR_ADDR ((uint)0xff080000) 23#define BCSR_SIZE ((uint)32) 24#define BCSR0 ((uint)(BCSR_ADDR + 0x00)) 25#define BCSR1 ((uint)(BCSR_ADDR + 0x04)) 26#define BCSR2 ((uint)(BCSR_ADDR + 0x08)) 27#define BCSR3 ((uint)(BCSR_ADDR + 0x0c)) 28#define BCSR4 ((uint)(BCSR_ADDR + 0x10)) 29 30#define CFG_PHYDEV_ADDR ((uint)0xff0a0000) 31#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300)) 32 33#define IMAP_ADDR (get_immrbase()) 34#define IMAP_SIZE ((uint)(64 * 1024)) 35 36#define MPC8xx_CPM_OFFSET (0x9c0) 37#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) 38#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver 39 40#define PCMCIA_MEM_ADDR ((uint)0xff020000) 41#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) 42 43/* Bits of interest in the BCSRs. 44 */ 45#define BCSR1_ETHEN ((uint)0x20000000) 46#define BCSR1_IRDAEN ((uint)0x10000000) 47#define BCSR1_RS232EN_1 ((uint)0x01000000) 48#define BCSR1_PCCEN ((uint)0x00800000) 49#define BCSR1_PCCVCC0 ((uint)0x00400000) 50#define BCSR1_PCCVPP0 ((uint)0x00200000) 51#define BCSR1_PCCVPP1 ((uint)0x00100000) 52#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1) 53#define BCSR1_RS232EN_2 ((uint)0x00040000) 54#define BCSR1_PCCVCC1 ((uint)0x00010000) 55#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1) 56 57#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/ 58#define BCSR4_USB_LO_SPD ((uint)0x04000000) 59#define BCSR4_USB_VCC ((uint)0x02000000) 60#define BCSR4_USB_FULL_SPD ((uint)0x00040000) 61#define BCSR4_USB_EN ((uint)0x00020000) 62 63#define BCSR5_MII2_EN 0x40 64#define BCSR5_MII2_RST 0x20 65#define BCSR5_T1_RST 0x10 66#define BCSR5_ATM155_RST 0x08 67#define BCSR5_ATM25_RST 0x04 68#define BCSR5_MII1_EN 0x02 69#define BCSR5_MII1_RST 0x01 70 71/* Interrupt level assignments */ 72#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */ 73#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */ 74#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */ 75 76/* We don't use the 8259 */ 77#define NR_8259_INTS 0 78 79/* CPM Ethernet through SCC1 */ 80#define PA_ENET_RXD ((ushort)0x0001) 81#define PA_ENET_TXD ((ushort)0x0002) 82#define PA_ENET_TCLK ((ushort)0x0100) 83#define PA_ENET_RCLK ((ushort)0x0200) 84#define PB_ENET_TENA ((uint)0x00001000) 85#define PC_ENET_CLSN ((ushort)0x0010) 86#define PC_ENET_RENA ((ushort)0x0020) 87 88/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to 89 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 90 */ 91#define SICR_ENET_MASK ((uint)0x000000ff) 92#define SICR_ENET_CLKRT ((uint)0x0000002c) 93 94#endif /* __ASM_MPC86XADS_H__ */ 95#endif /* __KERNEL__ */ 96