1/* 2 * linux/arch/parisc/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King 6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) 7 * 8 * 1994-07-02 Alan Modra 9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 11 * "A Kernel Model for Precision Timekeeping" by Dave Mills 12 */ 13#include <linux/errno.h> 14#include <linux/module.h> 15#include <linux/sched.h> 16#include <linux/kernel.h> 17#include <linux/param.h> 18#include <linux/string.h> 19#include <linux/mm.h> 20#include <linux/interrupt.h> 21#include <linux/time.h> 22#include <linux/init.h> 23#include <linux/smp.h> 24#include <linux/profile.h> 25#include <linux/clocksource.h> 26 27#include <asm/uaccess.h> 28#include <asm/io.h> 29#include <asm/irq.h> 30#include <asm/param.h> 31#include <asm/pdc.h> 32#include <asm/led.h> 33 34#include <linux/timex.h> 35 36static unsigned long clocktick __read_mostly; /* timer cycles per tick */ 37 38/* 39 * We keep time on PA-RISC Linux by using the Interval Timer which is 40 * a pair of registers; one is read-only and one is write-only; both 41 * accessed through CR16. The read-only register is 32 or 64 bits wide, 42 * and increments by 1 every CPU clock tick. The architecture only 43 * guarantees us a rate between 0.5 and 2, but all implementations use a 44 * rate of 1. The write-only register is 32-bits wide. When the lowest 45 * 32 bits of the read-only register compare equal to the write-only 46 * register, it raises a maskable external interrupt. Each processor has 47 * an Interval Timer of its own and they are not synchronised. 48 * 49 * We want to generate an interrupt every 1/HZ seconds. So we program 50 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data 51 * is programmed with the intended time of the next tick. We can be 52 * held off for an arbitrarily long period of time by interrupts being 53 * disabled, so we may miss one or more ticks. 54 */ 55irqreturn_t timer_interrupt(int irq, void *dev_id) 56{ 57 unsigned long now; 58 unsigned long next_tick; 59 unsigned long cycles_elapsed, ticks_elapsed; 60 unsigned long cycles_remainder; 61 unsigned int cpu = smp_processor_id(); 62 struct cpuinfo_parisc *cpuinfo = &cpu_data[cpu]; 63 64 /* gcc can optimize for "read-only" case with a local clocktick */ 65 unsigned long cpt = clocktick; 66 67 profile_tick(CPU_PROFILING); 68 69 /* Initialize next_tick to the expected tick time. */ 70 next_tick = cpuinfo->it_value; 71 72 /* Get current interval timer. 73 * CR16 reads as 64 bits in CPU wide mode. 74 * CR16 reads as 32 bits in CPU narrow mode. 75 */ 76 now = mfctl(16); 77 78 cycles_elapsed = now - next_tick; 79 80 if ((cycles_elapsed >> 5) < cpt) { 81 /* use "cheap" math (add/subtract) instead 82 * of the more expensive div/mul method 83 */ 84 cycles_remainder = cycles_elapsed; 85 ticks_elapsed = 1; 86 while (cycles_remainder > cpt) { 87 cycles_remainder -= cpt; 88 ticks_elapsed++; 89 } 90 } else { 91 cycles_remainder = cycles_elapsed % cpt; 92 ticks_elapsed = 1 + cycles_elapsed / cpt; 93 } 94 95 /* Can we differentiate between "early CR16" (aka Scenario 1) and 96 * "long delay" (aka Scenario 3)? I don't think so. 97 * 98 * We expected timer_interrupt to be delivered at least a few hundred 99 * cycles after the IT fires. But it's arbitrary how much time passes 100 * before we call it "late". I've picked one second. 101 */ 102 if (unlikely(ticks_elapsed > HZ)) { 103 /* Scenario 3: very long delay? bad in any case */ 104 printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!" 105 " cycles %lX rem %lX " 106 " next/now %lX/%lX\n", 107 cpu, 108 cycles_elapsed, cycles_remainder, 109 next_tick, now ); 110 } 111 112 /* convert from "division remainder" to "remainder of clock tick" */ 113 cycles_remainder = cpt - cycles_remainder; 114 115 /* Determine when (in CR16 cycles) next IT interrupt will fire. 116 * We want IT to fire modulo clocktick even if we miss/skip some. 117 * But those interrupts don't in fact get delivered that regularly. 118 */ 119 next_tick = now + cycles_remainder; 120 121 cpuinfo->it_value = next_tick; 122 123 /* Skip one clocktick on purpose if we are likely to miss next_tick. 124 * We want to avoid the new next_tick being less than CR16. 125 * If that happened, itimer wouldn't fire until CR16 wrapped. 126 * We'll catch the tick we missed on the tick after that. 127 */ 128 if (!(cycles_remainder >> 13)) 129 next_tick += cpt; 130 131 /* Program the IT when to deliver the next interrupt. */ 132 /* Only bottom 32-bits of next_tick are written to cr16. */ 133 mtctl(next_tick, 16); 134 135 136 /* Done mucking with unreliable delivery of interrupts. 137 * Go do system house keeping. 138 */ 139 140 if (!--cpuinfo->prof_counter) { 141 cpuinfo->prof_counter = cpuinfo->prof_multiplier; 142 update_process_times(user_mode(get_irq_regs())); 143 } 144 145 if (cpu == 0) { 146 write_seqlock(&xtime_lock); 147 do_timer(ticks_elapsed); 148 write_sequnlock(&xtime_lock); 149 } 150 151 return IRQ_HANDLED; 152} 153 154 155unsigned long profile_pc(struct pt_regs *regs) 156{ 157 unsigned long pc = instruction_pointer(regs); 158 159 if (regs->gr[0] & PSW_N) 160 pc -= 4; 161 162#ifdef CONFIG_SMP 163 if (in_lock_functions(pc)) 164 pc = regs->gr[2]; 165#endif 166 167 return pc; 168} 169EXPORT_SYMBOL(profile_pc); 170 171 172/* clock source code */ 173 174static cycle_t read_cr16(void) 175{ 176 return get_cycles(); 177} 178 179static struct clocksource clocksource_cr16 = { 180 .name = "cr16", 181 .rating = 300, 182 .read = read_cr16, 183 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 184 .mult = 0, /* to be set */ 185 .shift = 22, 186 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 187}; 188 189#ifdef CONFIG_SMP 190int update_cr16_clocksource(void) 191{ 192 int change = 0; 193 194 /* since the cr16 cycle counters are not synchronized across CPUs, 195 we'll check if we should switch to a safe clocksource: */ 196 if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) { 197 clocksource_change_rating(&clocksource_cr16, 0); 198 change = 1; 199 } 200 201 return change; 202} 203#else 204int update_cr16_clocksource(void) 205{ 206 return 0; /* no change */ 207} 208#endif /*CONFIG_SMP*/ 209 210void __init start_cpu_itimer(void) 211{ 212 unsigned int cpu = smp_processor_id(); 213 unsigned long next_tick = mfctl(16) + clocktick; 214 215 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 216 217 cpu_data[cpu].it_value = next_tick; 218} 219 220void __init time_init(void) 221{ 222 static struct pdc_tod tod_data; 223 unsigned long current_cr16_khz; 224 225 clocktick = (100 * PAGE0->mem_10msec) / HZ; 226 227 start_cpu_itimer(); /* get CPU 0 started */ 228 229 /* register at clocksource framework */ 230 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ 231 clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz, 232 clocksource_cr16.shift); 233 clocksource_register(&clocksource_cr16); 234 235 if (pdc_tod_read(&tod_data) == 0) { 236 unsigned long flags; 237 238 write_seqlock_irqsave(&xtime_lock, flags); 239 xtime.tv_sec = tod_data.tod_sec; 240 xtime.tv_nsec = tod_data.tod_usec * 1000; 241 set_normalized_timespec(&wall_to_monotonic, 242 -xtime.tv_sec, -xtime.tv_nsec); 243 write_sequnlock_irqrestore(&xtime_lock, flags); 244 } else { 245 printk(KERN_ERR "Error reading tod clock\n"); 246 xtime.tv_sec = 0; 247 xtime.tv_nsec = 0; 248 } 249} 250