1/* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License 4 * as published by the Free Software Foundation; either version 2 5 * of the License, or (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 15 * 16 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation 17 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> 18 * Copyright (C) 2007 MIPS Technologies, Inc. 19 * written by Ralf Baechle <ralf@linux-mips.org> 20 */ 21 22#undef DEBUG 23 24#include <linux/device.h> 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/init.h> 29#include <linux/interrupt.h> 30#include <linux/slab.h> 31#include <linux/vmalloc.h> 32#include <linux/fs.h> 33#include <linux/errno.h> 34#include <linux/wait.h> 35#include <asm/io.h> 36#include <asm/sibyte/sb1250.h> 37 38#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 39#include <asm/sibyte/bcm1480_regs.h> 40#include <asm/sibyte/bcm1480_scd.h> 41#include <asm/sibyte/bcm1480_int.h> 42#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 43#include <asm/sibyte/sb1250_regs.h> 44#include <asm/sibyte/sb1250_scd.h> 45#include <asm/sibyte/sb1250_int.h> 46#else 47#error invalid SiByte UART configuation 48#endif 49 50#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 51#undef K_INT_TRACE_FREEZE 52#define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE 53#undef K_INT_PERF_CNT 54#define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT 55#endif 56 57#include <asm/system.h> 58#include <asm/uaccess.h> 59 60#define SBPROF_TB_MAJOR 240 61 62typedef u64 tb_sample_t[6*256]; 63 64enum open_status { 65 SB_CLOSED, 66 SB_OPENING, 67 SB_OPEN 68}; 69 70struct sbprof_tb { 71 wait_queue_head_t tb_sync; 72 wait_queue_head_t tb_read; 73 struct mutex lock; 74 enum open_status open; 75 tb_sample_t *sbprof_tbbuf; 76 int next_tb_sample; 77 78 volatile int tb_enable; 79 volatile int tb_armed; 80 81}; 82 83static struct sbprof_tb sbp; 84 85#define MAX_SAMPLE_BYTES (24*1024*1024) 86#define MAX_TBSAMPLE_BYTES (12*1024*1024) 87 88#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t)) 89#define TB_SAMPLE_SIZE (sizeof(tb_sample_t)) 90#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE) 91 92/* ioctls */ 93#define SBPROF_ZBSTART _IOW('s', 0, int) 94#define SBPROF_ZBSTOP _IOW('s', 1, int) 95#define SBPROF_ZBWAITFULL _IOW('s', 2, int) 96 97/* 98 * Routines for using 40-bit SCD cycle counter 99 * 100 * Client responsible for either handling interrupts or making sure 101 * the cycles counter never saturates, e.g., by doing 102 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs. 103 */ 104 105/* 106 * Configures SCD counter 0 to count ZCLKs starting from val; 107 * Configures SCD counters1,2,3 to count nothing. 108 * Must not be called while gathering ZBbus profiles. 109 */ 110 111#define zclk_timer_init(val) \ 112 __asm__ __volatile__ (".set push;" \ 113 ".set mips64;" \ 114 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ 115 "sd %0, 0x10($8);" /* write val to counter0 */ \ 116 "sd %1, 0($8);" /* config counter0 for zclks*/ \ 117 ".set pop" \ 118 : /* no outputs */ \ 119 /* enable, counter0 */ \ 120 : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \ 121 : /* modifies */ "$8" ) 122 123 124/* Reads SCD counter 0 and puts result in value 125 unsigned long long val; */ 126#define zclk_get(val) \ 127 __asm__ __volatile__ (".set push;" \ 128 ".set mips64;" \ 129 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ 130 "ld %0, 0x10($8);" /* write val to counter0 */ \ 131 ".set pop" \ 132 : /* outputs */ "=r"(val) \ 133 : /* inputs */ \ 134 : /* modifies */ "$8" ) 135 136#define DEVNAME "sb_tbprof" 137 138#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES) 139 140/* 141 * Support for ZBbus sampling using the trace buffer 142 * 143 * We use the SCD performance counter interrupt, caused by a Zclk counter 144 * overflow, to trigger the start of tracing. 145 * 146 * We set the trace buffer to sample everything and freeze on 147 * overflow. 148 * 149 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0. 150 * 151 */ 152 153static u64 tb_period; 154 155static void arm_tb(void) 156{ 157 u64 scdperfcnt; 158 u64 next = (1ULL << 40) - tb_period; 159 u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; 160 161 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); 162 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 163 164 /* 165 * Unfortunately, in Pass 2 we must clear all counters to knock down 166 * a previous interrupt request. This means that bus profiling 167 * requires ALL of the SCD perf counters. 168 */ 169#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 170 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | 171 /* keep counters 0,2,3,4,5,6,7 as is */ 172 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 173 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0)); 174 __raw_writeq( 175 M_SPC_CFG_ENABLE | /* enable counting */ 176 M_SPC_CFG_CLEAR | /* clear all counters */ 177 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 178 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1)); 179#else 180 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | 181 /* keep counters 0,2,3 as is */ 182 M_SPC_CFG_ENABLE | /* enable counting */ 183 M_SPC_CFG_CLEAR | /* clear all counters */ 184 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 185 IOADDR(A_SCD_PERF_CNT_CFG)); 186#endif 187 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); 188 /* Reset the trace buffer */ 189 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 190 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); 191 sbp.tb_armed = 1; 192} 193 194static irqreturn_t sbprof_tb_intr(int irq, void *dev_id) 195{ 196 int i; 197 198 pr_debug(DEVNAME ": tb_intr\n"); 199 200 if (sbp.next_tb_sample < MAX_TB_SAMPLES) { 201 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; 202 /* Read out trace */ 203 __raw_writeq(M_SCD_TRACE_CFG_START_READ, 204 IOADDR(A_SCD_TRACE_CFG)); 205 __asm__ __volatile__ ("sync" : : : "memory"); 206 /* Loop runs backwards because bundles are read out in reverse order */ 207 for (i = 256 * 6; i > 0; i -= 6) { 208 /* Subscripts decrease to put bundle in the order */ 209 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */ 210 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 211 /* read t2 hi */ 212 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 213 /* read t2 lo */ 214 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 215 /* read t1 hi */ 216 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 217 /* read t1 lo */ 218 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 219 /* read t0 hi */ 220 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 221 /* read t0 lo */ 222 } 223 if (!sbp.tb_enable) { 224 pr_debug(DEVNAME ": tb_intr shutdown\n"); 225 __raw_writeq(M_SCD_TRACE_CFG_RESET, 226 IOADDR(A_SCD_TRACE_CFG)); 227 sbp.tb_armed = 0; 228 wake_up_interruptible(&sbp.tb_sync); 229 } else { 230 /* knock down current interrupt and get another one later */ 231 arm_tb(); 232 } 233 } else { 234 /* No more trace buffer samples */ 235 pr_debug(DEVNAME ": tb_intr full\n"); 236 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 237 sbp.tb_armed = 0; 238 if (!sbp.tb_enable) 239 wake_up_interruptible(&sbp.tb_sync); 240 wake_up_interruptible(&sbp.tb_read); 241 } 242 return IRQ_HANDLED; 243} 244 245static irqreturn_t sbprof_pc_intr(int irq, void *dev_id) 246{ 247 printk(DEVNAME ": unexpected pc_intr"); 248 return IRQ_NONE; 249} 250 251/* 252 * Requires: Already called zclk_timer_init with a value that won't 253 * saturate 40 bits. No subsequent use of SCD performance counters 254 * or trace buffer. 255 */ 256 257static int sbprof_zbprof_start(struct file *filp) 258{ 259 u64 scdperfcnt; 260 int err; 261 262 if (xchg(&sbp.tb_enable, 1)) 263 return -EBUSY; 264 265 pr_debug(DEVNAME ": starting\n"); 266 267 sbp.next_tb_sample = 0; 268 filp->f_pos = 0; 269 270 err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, 271 DEVNAME " trace freeze", &sbp); 272 if (err) 273 return -EBUSY; 274 275 /* Make sure there isn't a perf-cnt interrupt waiting */ 276 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 277 /* Disable and clear counters, override SRC_1 */ 278 __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | 279 M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), 280 IOADDR(A_SCD_PERF_CNT_CFG)); 281 282 /* 283 * We grab this interrupt to prevent others from trying to use 284 * it, even though we don't want to service the interrupts 285 * (they only feed into the trace-on-interrupt mechanism) 286 */ 287 if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) { 288 free_irq(K_INT_TRACE_FREEZE, &sbp); 289 return -EBUSY; 290 } 291 292 /* 293 * I need the core to mask these, but the interrupt mapper to 294 * pass them through. I am exploiting my knowledge that 295 * cp0_status masks out IP[5]. krw 296 */ 297#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 298 __raw_writeq(K_BCM1480_INT_MAP_I3, 299 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + 300 ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3))); 301#else 302 __raw_writeq(K_INT_MAP_I3, 303 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 304 (K_INT_PERF_CNT << 3))); 305#endif 306 307 /* Initialize address traps */ 308 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); 309 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); 310 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); 311 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); 312 313 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); 314 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); 315 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); 316 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); 317 318 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); 319 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); 320 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); 321 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); 322 323 /* Initialize Trace Event 0-7 */ 324 /* when interrupt */ 325 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); 326 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); 327 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); 328 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); 329 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); 330 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); 331 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); 332 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); 333 334 /* Initialize Trace Sequence 0-7 */ 335 /* Start on event 0 (interrupt) */ 336 __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, 337 IOADDR(A_SCD_TRACE_SEQUENCE_0)); 338 /* dsamp when d used | asamp when a used */ 339 __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | 340 K_SCD_TRSEQ_TRIGGER_ALL, 341 IOADDR(A_SCD_TRACE_SEQUENCE_1)); 342 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); 343 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); 344 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); 345 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); 346 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); 347 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); 348 349 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ 350#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 351 __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f), 352 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L))); 353#else 354 __raw_writeq(1ULL << K_INT_PERF_CNT, 355 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); 356#endif 357 arm_tb(); 358 359 pr_debug(DEVNAME ": done starting\n"); 360 361 return 0; 362} 363 364static int sbprof_zbprof_stop(void) 365{ 366 int err = 0; 367 368 pr_debug(DEVNAME ": stopping\n"); 369 370 if (sbp.tb_enable) { 371 /* 372 * XXXKW there is a window here where the intr handler may run, 373 * see the disable, and do the wake_up before this sleep 374 * happens. 375 */ 376 pr_debug(DEVNAME ": wait for disarm\n"); 377 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed); 378 pr_debug(DEVNAME ": disarm complete, stat %d\n", err); 379 380 if (err) 381 return err; 382 383 sbp.tb_enable = 0; 384 free_irq(K_INT_TRACE_FREEZE, &sbp); 385 free_irq(K_INT_PERF_CNT, &sbp); 386 } 387 388 pr_debug(DEVNAME ": done stopping\n"); 389 390 return err; 391} 392 393static int sbprof_tb_open(struct inode *inode, struct file *filp) 394{ 395 int minor; 396 397 minor = iminor(inode); 398 if (minor != 0) 399 return -ENODEV; 400 401 if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED) 402 return -EBUSY; 403 404 memset(&sbp, 0, sizeof(struct sbprof_tb)); 405 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); 406 if (!sbp.sbprof_tbbuf) 407 return -ENOMEM; 408 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); 409 init_waitqueue_head(&sbp.tb_sync); 410 init_waitqueue_head(&sbp.tb_read); 411 mutex_init(&sbp.lock); 412 413 sbp.open = SB_OPEN; 414 415 return 0; 416} 417 418static int sbprof_tb_release(struct inode *inode, struct file *filp) 419{ 420 int minor; 421 422 minor = iminor(inode); 423 if (minor != 0 || !sbp.open) 424 return -ENODEV; 425 426 mutex_lock(&sbp.lock); 427 428 if (sbp.tb_armed || sbp.tb_enable) 429 sbprof_zbprof_stop(); 430 431 vfree(sbp.sbprof_tbbuf); 432 sbp.open = 0; 433 434 mutex_unlock(&sbp.lock); 435 436 return 0; 437} 438 439static ssize_t sbprof_tb_read(struct file *filp, char *buf, 440 size_t size, loff_t *offp) 441{ 442 int cur_sample, sample_off, cur_count, sample_left; 443 char *src; 444 int count = 0; 445 char *dest = buf; 446 long cur_off = *offp; 447 448 if (!access_ok(VERIFY_WRITE, buf, size)) 449 return -EFAULT; 450 451 mutex_lock(&sbp.lock); 452 453 count = 0; 454 cur_sample = cur_off / TB_SAMPLE_SIZE; 455 sample_off = cur_off % TB_SAMPLE_SIZE; 456 sample_left = TB_SAMPLE_SIZE - sample_off; 457 458 while (size && (cur_sample < sbp.next_tb_sample)) { 459 int err; 460 461 cur_count = size < sample_left ? size : sample_left; 462 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off); 463 err = __copy_to_user(dest, src, cur_count); 464 if (err) { 465 *offp = cur_off + cur_count - err; 466 mutex_unlock(&sbp.lock); 467 return err; 468 } 469 pr_debug(DEVNAME ": read from sample %d, %d bytes\n", 470 cur_sample, cur_count); 471 size -= cur_count; 472 sample_left -= cur_count; 473 if (!sample_left) { 474 cur_sample++; 475 sample_off = 0; 476 sample_left = TB_SAMPLE_SIZE; 477 } else { 478 sample_off += cur_count; 479 } 480 cur_off += cur_count; 481 dest += cur_count; 482 count += cur_count; 483 } 484 *offp = cur_off; 485 mutex_unlock(&sbp.lock); 486 487 return count; 488} 489 490static long sbprof_tb_ioctl(struct file *filp, 491 unsigned int command, 492 unsigned long arg) 493{ 494 int err = 0; 495 496 switch (command) { 497 case SBPROF_ZBSTART: 498 mutex_lock(&sbp.lock); 499 err = sbprof_zbprof_start(filp); 500 mutex_unlock(&sbp.lock); 501 break; 502 503 case SBPROF_ZBSTOP: 504 mutex_lock(&sbp.lock); 505 err = sbprof_zbprof_stop(); 506 mutex_unlock(&sbp.lock); 507 break; 508 509 case SBPROF_ZBWAITFULL: { 510 err = wait_event_interruptible(sbp.tb_read, TB_FULL); 511 if (err) 512 break; 513 514 err = put_user(TB_FULL, (int *) arg); 515 break; 516 } 517 518 default: 519 err = -EINVAL; 520 break; 521 } 522 523 return err; 524} 525 526static const struct file_operations sbprof_tb_fops = { 527 .owner = THIS_MODULE, 528 .open = sbprof_tb_open, 529 .release = sbprof_tb_release, 530 .read = sbprof_tb_read, 531 .unlocked_ioctl = sbprof_tb_ioctl, 532 .compat_ioctl = sbprof_tb_ioctl, 533 .mmap = NULL, 534}; 535 536static struct class *tb_class; 537static struct device *tb_dev; 538 539static int __init sbprof_tb_init(void) 540{ 541 struct device *dev; 542 struct class *tbc; 543 int err; 544 545 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) { 546 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n", 547 SBPROF_TB_MAJOR); 548 return -EIO; 549 } 550 551 tbc = class_create(THIS_MODULE, "sb_tracebuffer"); 552 if (IS_ERR(tbc)) { 553 err = PTR_ERR(tbc); 554 goto out_chrdev; 555 } 556 557 tb_class = tbc; 558 559 dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), "tb"); 560 if (IS_ERR(dev)) { 561 err = PTR_ERR(dev); 562 goto out_class; 563 } 564 tb_dev = dev; 565 566 sbp.open = 0; 567 tb_period = zbbus_mhz * 10000LL; 568 pr_info(DEVNAME ": initialized - tb_period = %lld\n", 569 (long long) tb_period); 570 return 0; 571 572out_class: 573 class_destroy(tb_class); 574out_chrdev: 575 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); 576 577 return err; 578} 579 580static void __exit sbprof_tb_cleanup(void) 581{ 582 device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0)); 583 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); 584 class_destroy(tb_class); 585} 586 587module_init(sbprof_tb_init); 588module_exit(sbprof_tb_cleanup); 589 590MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR); 591MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 592MODULE_LICENSE("GPL"); 593