1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de) 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10#include <linux/init.h> 11#include <linux/kernel.h> 12#include <linux/pci.h> 13#include <asm/sn/arch.h> 14#include <asm/pci/bridge.h> 15#include <asm/paccess.h> 16#include <asm/sn/intr.h> 17#include <asm/sn/sn0/hub.h> 18 19/* 20 * Max #PCI busses we can handle; ie, max #PCI bridges. 21 */ 22#define MAX_PCI_BUSSES 40 23 24/* 25 * Max #PCI devices (like scsi controllers) we handle on a bus. 26 */ 27#define MAX_DEVICES_PER_PCIBUS 8 28 29static struct bridge_controller bridges[MAX_PCI_BUSSES]; 30 31/* 32 * Translate from irq to software PCI bus number and PCI slot. 33 */ 34struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 35int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; 36 37extern struct pci_ops bridge_pci_ops; 38 39int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid) 40{ 41 unsigned long offset = NODE_OFFSET(nasid); 42 struct bridge_controller *bc; 43 static int num_bridges = 0; 44 bridge_t *bridge; 45 int slot; 46 47 printk("a bridge\n"); 48 49 if (!num_bridges) 50 ioport_resource.end = ~0UL; 51 52 bc = &bridges[num_bridges]; 53 54 bc->pc.pci_ops = &bridge_pci_ops; 55 bc->pc.mem_resource = &bc->mem; 56 bc->pc.io_resource = &bc->io; 57 58 bc->pc.index = num_bridges; 59 60 bc->mem.name = "Bridge PCI MEM"; 61 bc->pc.mem_offset = offset; 62 bc->mem.start = 0; 63 bc->mem.end = ~0UL; 64 bc->mem.flags = IORESOURCE_MEM; 65 66 bc->io.name = "Bridge IO MEM"; 67 bc->pc.io_offset = offset; 68 bc->io.start = 0UL; 69 bc->io.end = ~0UL; 70 bc->io.flags = IORESOURCE_IO; 71 72 bc->irq_cpu = smp_processor_id(); 73 bc->widget_id = widget_id; 74 bc->nasid = nasid; 75 76 bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR; 77 78 /* 79 * point to this bridge 80 */ 81 bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); 82 83 /* 84 * Clear all pending interrupts. 85 */ 86 bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; 87 88 /* 89 * Until otherwise set up, assume all interrupts are from slot 0 90 */ 91 bridge->b_int_device = 0x0; 92 93 /* 94 * swap pio's to pci mem and io space (big windows) 95 */ 96 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 97 BRIDGE_CTRL_MEM_SWAP; 98 99 /* 100 * Hmm... IRIX sets additional bits in the address which 101 * are documented as reserved in the bridge docs. 102 */ 103 bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); 104 bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ 105 bridge->b_dir_map = (masterwid << 20); /* DMA */ 106 bridge->b_int_enable = 0; 107 108 for (slot = 0; slot < 8; slot ++) { 109 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 110 bc->pci_int[slot] = -1; 111 } 112 bridge->b_wid_tflush; /* wait until Bridge PIO complete */ 113 114 bc->base = bridge; 115 116 register_pci_controller(&bc->pc); 117 118 num_bridges++; 119 120 return 0; 121} 122 123/* 124 * All observed requests have pin == 1. We could have a global here, that 125 * gets incremented and returned every time - unfortunately, pci_map_irq 126 * may be called on the same device over and over, and need to return the 127 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. 128 * 129 * A given PCI device, in general, should be able to intr any of the cpus 130 * on any one of the hubs connected to its xbow. 131 */ 132int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 133{ 134 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 135 int irq = bc->pci_int[slot]; 136 137 if (irq == -1) { 138 irq = bc->pci_int[slot] = request_bridge_irq(bc); 139 if (irq < 0) 140 panic("Can't allocate interrupt for PCI device %s\n", 141 pci_name(dev)); 142 } 143 144 irq_to_bridge[irq] = bc; 145 irq_to_slot[irq] = slot; 146 147 return irq; 148} 149 150/* Do platform specific device initialization at pci_enable_device() time */ 151int pcibios_plat_dev_init(struct pci_dev *dev) 152{ 153 return 0; 154} 155 156 157static inline void pci_disable_swapping(struct pci_dev *dev) 158{ 159 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 160 bridge_t *bridge = bc->base; 161 int slot = PCI_SLOT(dev->devfn); 162 163 /* Turn off byte swapping */ 164 bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; 165 bridge->b_widget.w_tflush; /* Flush */ 166} 167 168static inline void pci_enable_swapping(struct pci_dev *dev) 169{ 170 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 171 bridge_t *bridge = bc->base; 172 int slot = PCI_SLOT(dev->devfn); 173 174 /* Turn on byte swapping */ 175 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 176 bridge->b_widget.w_tflush; /* Flush */ 177} 178 179static void __init pci_fixup_ioc3(struct pci_dev *d) 180{ 181 pci_disable_swapping(d); 182} 183 184int pcibus_to_node(struct pci_bus *bus) 185{ 186 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 187 188 return bc->nasid; 189} 190 191DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 192 pci_fixup_ioc3); 193