1#include <linux/compiler.h>
2#include <linux/mm.h>
3#include <linux/signal.h>
4#include <linux/smp.h>
5
6#include <asm/asm.h>
7#include <asm/bootinfo.h>
8#include <asm/byteorder.h>
9#include <asm/cpu.h>
10#include <asm/inst.h>
11#include <asm/processor.h>
12#include <asm/uaccess.h>
13#include <asm/branch.h>
14#include <asm/mipsregs.h>
15#include <asm/system.h>
16#include <asm/cacheflush.h>
17
18#include <asm/fpu_emulator.h>
19
20#include "ieee754.h"
21#include "dsemul.h"
22
23/* Strap kernel emulator for full MIPS IV emulation */
24
25#ifdef __mips
26#undef __mips
27#endif
28#define __mips 4
29
30/*
31 * Emulate the arbritrary instruction ir at xcp->cp0_epc.  Required when
32 * we have to emulate the instruction in a COP1 branch delay slot.  Do
33 * not change cp0_epc due to the instruction
34 *
35 * According to the spec:
36 * 1) it shouldnt be a branch :-)
37 * 2) it can be a COP instruction :-(
38 * 3) if we are tring to run a protected memory space we must take
39 *    special care on memory access instructions :-(
40 */
41
42/*
43 * "Trampoline" return routine to catch exception following
44 *  execution of delay-slot instruction execution.
45 */
46
47struct emuframe {
48	mips_instruction	emul;
49	mips_instruction	badinst;
50	mips_instruction	cookie;
51	unsigned long		epc;
52};
53
54int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
55{
56	extern asmlinkage void handle_dsemulret(void);
57	mips_instruction *dsemul_insns;
58	struct emuframe *fr;
59	int err;
60
61	if (ir == 0) {		/* a nop is easy */
62		regs->cp0_epc = cpc;
63		regs->cp0_cause &= ~CAUSEF_BD;
64		return 0;
65	}
66#ifdef DSEMUL_TRACE
67	printk("dsemul %lx %lx\n", regs->cp0_epc, cpc);
68
69#endif
70
71	/*
72	 * The strategy is to push the instruction onto the user stack
73	 * and put a trap after it which we can catch and jump to
74	 * the required address any alternative apart from full
75	 * instruction emulation!!.
76	 *
77	 * Algorithmics used a system call instruction, and
78	 * borrowed that vector.  MIPS/Linux version is a bit
79	 * more heavyweight in the interests of portability and
80	 * multiprocessor support.  For Linux we generate a
81	 * an unaligned access and force an address error exception.
82	 *
83	 * For embedded systems (stand-alone) we prefer to use a
84	 * non-existing CP1 instruction. This prevents us from emulating
85	 * branches, but gives us a cleaner interface to the exception
86	 * handler (single entry point).
87	 */
88
89	/* Ensure that the two instructions are in the same cache line */
90	dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
91	fr = (struct emuframe *) dsemul_insns;
92
93	/* Verify that the stack pointer is not competely insane */
94	if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
95		return SIGBUS;
96
97	err = __put_user(ir, &fr->emul);
98	err |= __put_user((mips_instruction)BADINST, &fr->badinst);
99	err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
100	err |= __put_user(cpc, &fr->epc);
101
102	if (unlikely(err)) {
103		fpuemustats.errors++;
104		return SIGBUS;
105	}
106
107	regs->cp0_epc = (unsigned long) &fr->emul;
108
109	flush_cache_sigtramp((unsigned long)&fr->badinst);
110
111	return SIGILL;		/* force out of emulation loop */
112}
113
114int do_dsemulret(struct pt_regs *xcp)
115{
116	struct emuframe *fr;
117	unsigned long epc;
118	u32 insn, cookie;
119	int err = 0;
120
121	fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction));
122
123	/*
124	 * If we can't even access the area, something is very wrong, but we'll
125	 * leave that to the default handling
126	 */
127	if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
128		return 0;
129
130	/*
131	 * Do some sanity checking on the stackframe:
132	 *
133	 *  - Is the instruction pointed to by the EPC an BADINST?
134	 *  - Is the following memory word the BD_COOKIE?
135	 */
136	err = __get_user(insn, &fr->badinst);
137	err |= __get_user(cookie, &fr->cookie);
138
139	if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) {
140		fpuemustats.errors++;
141		return 0;
142	}
143
144	/*
145	 * At this point, we are satisfied that it's a BD emulation trap.  Yes,
146	 * a user might have deliberately put two malformed and useless
147	 * instructions in a row in his program, in which case he's in for a
148	 * nasty surprise - the next instruction will be treated as a
149	 * continuation address!  Alas, this seems to be the only way that we
150	 * can handle signals, recursion, and longjmps() in the context of
151	 * emulating the branch delay instruction.
152	 */
153
154#ifdef DSEMUL_TRACE
155	printk("dsemulret\n");
156#endif
157	if (__get_user(epc, &fr->epc)) {		/* Saved EPC */
158		/* This is not a good situation to be in */
159		force_sig(SIGBUS, current);
160
161		return 0;
162	}
163
164	/* Set EPC to return to post-branch instruction */
165	xcp->cp0_epc = epc;
166
167	return 1;
168}
169