1/* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: MontaVista Software, Inc. 4 * ahennessy@mvista.com 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 2000-2001 Toshiba Corporation 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * You should have received a copy of the GNU General Public License along 29 * with this program; if not, write to the Free Software Foundation, Inc., 30 * 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32#include <linux/init.h> 33#include <linux/sched.h> 34#include <linux/types.h> 35#include <linux/interrupt.h> 36 37#include <asm/io.h> 38#include <asm/mipsregs.h> 39#include <asm/system.h> 40 41#include <asm/processor.h> 42#include <asm/jmr3927/jmr3927.h> 43 44#if JMR3927_IRQ_END > NR_IRQS 45#error JMR3927_IRQ_END > NR_IRQS 46#endif 47 48#define irc_dlevel 0 49#define irc_elevel 1 50 51static unsigned char irc_level[TX3927_NUM_IR] = { 52 5, 5, 5, 5, 5, 5, /* INT[5:0] */ 53 7, 7, /* SIO */ 54 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ 55 6, 6, 6 /* TMR */ 56}; 57 58/* 59 * CP0_STATUS is a thread's resource (saved/restored on context switch). 60 * So disable_irq/enable_irq MUST handle IOC/IRC registers. 61 */ 62static void mask_irq_ioc(unsigned int irq) 63{ 64 /* 0: mask */ 65 unsigned int irq_nr = irq - JMR3927_IRQ_IOC; 66 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); 67 unsigned int bit = 1 << irq_nr; 68 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); 69 /* flush write buffer */ 70 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 71} 72static void unmask_irq_ioc(unsigned int irq) 73{ 74 /* 0: mask */ 75 unsigned int irq_nr = irq - JMR3927_IRQ_IOC; 76 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); 77 unsigned int bit = 1 << irq_nr; 78 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); 79 /* flush write buffer */ 80 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); 81} 82 83static void mask_irq_irc(unsigned int irq) 84{ 85 unsigned int irq_nr = irq - JMR3927_IRQ_IRC; 86 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2]; 87 if (irq_nr & 1) 88 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8); 89 else 90 *ilrp = (*ilrp & 0xff00) | irc_dlevel; 91 /* update IRCSR */ 92 tx3927_ircptr->imr = 0; 93 tx3927_ircptr->imr = irc_elevel; 94 /* flush write buffer */ 95 (void)tx3927_ircptr->ssr; 96} 97 98static void unmask_irq_irc(unsigned int irq) 99{ 100 unsigned int irq_nr = irq - JMR3927_IRQ_IRC; 101 volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2]; 102 if (irq_nr & 1) 103 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8); 104 else 105 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr]; 106 /* update IRCSR */ 107 tx3927_ircptr->imr = 0; 108 tx3927_ircptr->imr = irc_elevel; 109} 110 111asmlinkage void plat_irq_dispatch(void) 112{ 113 unsigned long cp0_cause = read_c0_cause(); 114 int irq; 115 116 if ((cp0_cause & CAUSEF_IP7) == 0) 117 return; 118 irq = (cp0_cause >> CAUSEB_IP2) & 0x0f; 119 120 do_IRQ(irq + JMR3927_IRQ_IRC); 121} 122 123static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id) 124{ 125 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); 126 int i; 127 128 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { 129 if (istat & (1 << i)) { 130 irq = JMR3927_IRQ_IOC + i; 131 do_IRQ(irq); 132 } 133 } 134 return IRQ_HANDLED; 135} 136 137static struct irqaction ioc_action = { 138 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, 139}; 140 141static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 142{ 143 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); 144 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", 145 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); 146 147 return IRQ_HANDLED; 148} 149static struct irqaction pcierr_action = { 150 jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL, 151}; 152 153static void __init jmr3927_irq_init(void); 154 155void __init arch_init_irq(void) 156{ 157 /* Now, interrupt control disabled, */ 158 /* all IRC interrupts are masked, */ 159 /* all IRC interrupt mode are Low Active. */ 160 161 /* mask all IOC interrupts */ 162 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); 163 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ 164 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); 165 166 /* clear PCI Soft interrupts */ 167 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); 168 /* clear PCI Reset interrupts */ 169 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 170 171 /* enable interrupt control */ 172 tx3927_ircptr->cer = TX3927_IRCER_ICE; 173 tx3927_ircptr->imr = irc_elevel; 174 175 jmr3927_irq_init(); 176 177 /* setup IOC interrupt 1 (PCI, MODEM) */ 178 setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); 179 180#ifdef CONFIG_PCI 181 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); 182#endif 183 184 /* enable all CPU interrupt bits. */ 185 set_c0_status(ST0_IM); /* IE bit is still 0. */ 186} 187 188static struct irq_chip jmr3927_irq_ioc = { 189 .name = "jmr3927_ioc", 190 .ack = mask_irq_ioc, 191 .mask = mask_irq_ioc, 192 .mask_ack = mask_irq_ioc, 193 .unmask = unmask_irq_ioc, 194}; 195 196static struct irq_chip jmr3927_irq_irc = { 197 .name = "jmr3927_irc", 198 .ack = mask_irq_irc, 199 .mask = mask_irq_irc, 200 .mask_ack = mask_irq_irc, 201 .unmask = unmask_irq_irc, 202}; 203 204static void __init jmr3927_irq_init(void) 205{ 206 u32 i; 207 208 for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++) 209 set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq); 210 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) 211 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); 212} 213