1/* 2 * Macintosh interrupts 3 * 4 * General design: 5 * In contrary to the Amiga and Atari platforms, the Mac hardware seems to 6 * exclusively use the autovector interrupts (the 'generic level0-level7' 7 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels 8 * are used: 9 * 1 - VIA1 10 * - slot 0: one second interrupt (CA2) 11 * - slot 1: VBlank (CA1) 12 * - slot 2: ADB data ready (SR full) 13 * - slot 3: ADB data (CB2) 14 * - slot 4: ADB clock (CB1) 15 * - slot 5: timer 2 16 * - slot 6: timer 1 17 * - slot 7: status of IRQ; signals 'any enabled int.' 18 * 19 * 2 - VIA2 or RBV 20 * - slot 0: SCSI DRQ (CA2) 21 * - slot 1: NUBUS IRQ (CA1) need to read port A to find which 22 * - slot 2: /EXP IRQ (only on IIci) 23 * - slot 3: SCSI IRQ (CB2) 24 * - slot 4: ASC IRQ (CB1) 25 * - slot 5: timer 2 (not on IIci) 26 * - slot 6: timer 1 (not on IIci) 27 * - slot 7: status of IRQ; signals 'any enabled int.' 28 * 29 * 2 - OSS (IIfx only?) 30 * - slot 0: SCSI interrupt 31 * - slot 1: Sound interrupt 32 * 33 * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes: 34 * 35 * 3 - unused (?) 36 * 37 * 4 - SCC (slot number determined by reading RR3 on the SSC itself) 38 * - slot 1: SCC channel A 39 * - slot 2: SCC channel B 40 * 41 * 5 - unused (?) 42 * [serial errors or special conditions seem to raise level 6 43 * interrupts on some models (LC4xx?)] 44 * 45 * 6 - off switch (?) 46 * 47 * For OSS Macintoshes (IIfx only at this point): 48 * 49 * 3 - Nubus interrupt 50 * - slot 0: Slot $9 51 * - slot 1: Slot $A 52 * - slot 2: Slot $B 53 * - slot 3: Slot $C 54 * - slot 4: Slot $D 55 * - slot 5: Slot $E 56 * 57 * 4 - SCC IOP 58 * - slot 1: SCC channel A 59 * - slot 2: SCC channel B 60 * 61 * 5 - ISM IOP (ADB?) 62 * 63 * 6 - unused 64 * 65 * For PSC Macintoshes (660AV, 840AV): 66 * 67 * 3 - PSC level 3 68 * - slot 0: MACE 69 * 70 * 4 - PSC level 4 71 * - slot 1: SCC channel A interrupt 72 * - slot 2: SCC channel B interrupt 73 * - slot 3: MACE DMA 74 * 75 * 5 - PSC level 5 76 * 77 * 6 - PSC level 6 78 * 79 * Finally we have good 'ole level 7, the non-maskable interrupt: 80 * 81 * 7 - NMI (programmer's switch on the back of some Macs) 82 * Also RAM parity error on models which support it (IIc, IIfx?) 83 * 84 * The current interrupt logic looks something like this: 85 * 86 * - We install dispatchers for the autovector interrupts (1-7). These 87 * dispatchers are responsible for querying the hardware (the 88 * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using 89 * this information a machspec interrupt number is generated by placing the 90 * index of the interrupt hardware into the low three bits and the original 91 * autovector interrupt number in the upper 5 bits. The handlers for the 92 * resulting machspec interrupt are then called. 93 * 94 * - Nubus is a special case because its interrupts are hidden behind two 95 * layers of hardware. Nubus interrupts come in as index 1 on VIA #2, 96 * which translates to IRQ number 17. In this spot we install _another_ 97 * dispatcher. This dispatcher finds the interrupting slot number (9-F) and 98 * then forms a new machspec interrupt number as above with the slot number 99 * minus 9 in the low three bits and the pseudo-level 7 in the upper five 100 * bits. The handlers for this new machspec interrupt number are then 101 * called. This puts Nubus interrupts into the range 56-62. 102 * 103 * - The Baboon interrupts (used on some PowerBooks) are an even more special 104 * case. They're hidden behind the Nubus slot $C interrupt thus adding a 105 * third layer of indirection. Why oh why did the Apple engineers do that? 106 * 107 * - We support "fast" and "slow" handlers, just like the Amiga port. The 108 * fast handlers are called first and with all interrupts disabled. They 109 * are expected to execute quickly (hence the name). The slow handlers are 110 * called last with interrupts enabled and the interrupt level restored. 111 * They must therefore be reentrant. 112 * 113 * TODO: 114 * 115 */ 116 117#include <linux/types.h> 118#include <linux/kernel.h> 119#include <linux/sched.h> 120#include <linux/kernel_stat.h> 121#include <linux/interrupt.h> /* for intr_count */ 122#include <linux/delay.h> 123#include <linux/seq_file.h> 124 125#include <asm/system.h> 126#include <asm/irq.h> 127#include <asm/traps.h> 128#include <asm/bootinfo.h> 129#include <asm/machw.h> 130#include <asm/macintosh.h> 131#include <asm/mac_via.h> 132#include <asm/mac_psc.h> 133#include <asm/hwtest.h> 134#include <asm/errno.h> 135#include <asm/macints.h> 136#include <asm/irq_regs.h> 137 138#define DEBUG_SPURIOUS 139#define SHUTUP_SONIC 140 141/* SCC interrupt mask */ 142 143static int scc_mask; 144 145/* 146 * VIA/RBV hooks 147 */ 148 149extern void via_init(void); 150extern void via_register_interrupts(void); 151extern void via_irq_enable(int); 152extern void via_irq_disable(int); 153extern void via_irq_clear(int); 154extern int via_irq_pending(int); 155 156/* 157 * OSS hooks 158 */ 159 160extern int oss_present; 161 162extern void oss_init(void); 163extern void oss_register_interrupts(void); 164extern void oss_irq_enable(int); 165extern void oss_irq_disable(int); 166extern void oss_irq_clear(int); 167extern int oss_irq_pending(int); 168 169/* 170 * PSC hooks 171 */ 172 173extern int psc_present; 174 175extern void psc_init(void); 176extern void psc_register_interrupts(void); 177extern void psc_irq_enable(int); 178extern void psc_irq_disable(int); 179extern void psc_irq_clear(int); 180extern int psc_irq_pending(int); 181 182/* 183 * IOP hooks 184 */ 185 186extern void iop_register_interrupts(void); 187 188/* 189 * Baboon hooks 190 */ 191 192extern int baboon_present; 193 194extern void baboon_init(void); 195extern void baboon_register_interrupts(void); 196extern void baboon_irq_enable(int); 197extern void baboon_irq_disable(int); 198extern void baboon_irq_clear(int); 199extern int baboon_irq_pending(int); 200 201/* 202 * SCC interrupt routines 203 */ 204 205static void scc_irq_enable(unsigned int); 206static void scc_irq_disable(unsigned int); 207 208/* 209 * console_loglevel determines NMI handler function 210 */ 211 212irqreturn_t mac_nmi_handler(int, void *); 213irqreturn_t mac_debug_handler(int, void *); 214 215/* #define DEBUG_MACINTS */ 216 217static void mac_enable_irq(unsigned int irq); 218static void mac_disable_irq(unsigned int irq); 219 220static struct irq_controller mac_irq_controller = { 221 .name = "mac", 222 .lock = __SPIN_LOCK_UNLOCKED(mac_irq_controller.lock), 223 .enable = mac_enable_irq, 224 .disable = mac_disable_irq, 225}; 226 227void mac_init_IRQ(void) 228{ 229#ifdef DEBUG_MACINTS 230 printk("mac_init_IRQ(): Setting things up...\n"); 231#endif 232 scc_mask = 0; 233 234 m68k_setup_irq_controller(&mac_irq_controller, IRQ_USER, 235 NUM_MAC_SOURCES - IRQ_USER); 236 /* Make sure the SONIC interrupt is cleared or things get ugly */ 237#ifdef SHUTUP_SONIC 238 printk("Killing onboard sonic... "); 239 /* This address should hopefully be mapped already */ 240 if (hwreg_present((void*)(0x50f0a000))) { 241 *(long *)(0x50f0a014) = 0x7fffL; 242 *(long *)(0x50f0a010) = 0L; 243 } 244 printk("Done.\n"); 245#endif /* SHUTUP_SONIC */ 246 247 /* 248 * Now register the handlers for the master IRQ handlers 249 * at levels 1-7. Most of the work is done elsewhere. 250 */ 251 252 if (oss_present) 253 oss_register_interrupts(); 254 else 255 via_register_interrupts(); 256 if (psc_present) 257 psc_register_interrupts(); 258 if (baboon_present) 259 baboon_register_interrupts(); 260 iop_register_interrupts(); 261 request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI", 262 mac_nmi_handler); 263#ifdef DEBUG_MACINTS 264 printk("mac_init_IRQ(): Done!\n"); 265#endif 266} 267 268/* 269 * mac_enable_irq - enable an interrupt source 270 * mac_disable_irq - disable an interrupt source 271 * mac_clear_irq - clears a pending interrupt 272 * mac_pending_irq - Returns the pending status of an IRQ (nonzero = pending) 273 * 274 * These routines are just dispatchers to the VIA/OSS/PSC routines. 275 */ 276 277static void mac_enable_irq(unsigned int irq) 278{ 279 int irq_src = IRQ_SRC(irq); 280 281 switch(irq_src) { 282 case 1: 283 via_irq_enable(irq); 284 break; 285 case 2: 286 case 7: 287 if (oss_present) 288 oss_irq_enable(irq); 289 else 290 via_irq_enable(irq); 291 break; 292 case 3: 293 case 4: 294 case 5: 295 case 6: 296 if (psc_present) 297 psc_irq_enable(irq); 298 else if (oss_present) 299 oss_irq_enable(irq); 300 else if (irq_src == 4) 301 scc_irq_enable(irq); 302 break; 303 case 8: 304 if (baboon_present) 305 baboon_irq_enable(irq); 306 break; 307 } 308} 309 310static void mac_disable_irq(unsigned int irq) 311{ 312 int irq_src = IRQ_SRC(irq); 313 314 switch(irq_src) { 315 case 1: 316 via_irq_disable(irq); 317 break; 318 case 2: 319 case 7: 320 if (oss_present) 321 oss_irq_disable(irq); 322 else 323 via_irq_disable(irq); 324 break; 325 case 3: 326 case 4: 327 case 5: 328 case 6: 329 if (psc_present) 330 psc_irq_disable(irq); 331 else if (oss_present) 332 oss_irq_disable(irq); 333 else if (irq_src == 4) 334 scc_irq_disable(irq); 335 break; 336 case 8: 337 if (baboon_present) 338 baboon_irq_disable(irq); 339 break; 340 } 341} 342 343void mac_clear_irq(unsigned int irq) 344{ 345 switch(IRQ_SRC(irq)) { 346 case 1: 347 via_irq_clear(irq); 348 break; 349 case 2: 350 case 7: 351 if (oss_present) 352 oss_irq_clear(irq); 353 else 354 via_irq_clear(irq); 355 break; 356 case 3: 357 case 4: 358 case 5: 359 case 6: 360 if (psc_present) 361 psc_irq_clear(irq); 362 else if (oss_present) 363 oss_irq_clear(irq); 364 break; 365 case 8: 366 if (baboon_present) 367 baboon_irq_clear(irq); 368 break; 369 } 370} 371 372int mac_irq_pending(unsigned int irq) 373{ 374 switch(IRQ_SRC(irq)) { 375 case 1: 376 return via_irq_pending(irq); 377 case 2: 378 case 7: 379 if (oss_present) 380 return oss_irq_pending(irq); 381 else 382 return via_irq_pending(irq); 383 case 3: 384 case 4: 385 case 5: 386 case 6: 387 if (psc_present) 388 return psc_irq_pending(irq); 389 else if (oss_present) 390 return oss_irq_pending(irq); 391 } 392 return 0; 393} 394 395static int num_debug[8]; 396 397irqreturn_t mac_debug_handler(int irq, void *dev_id) 398{ 399 if (num_debug[irq] < 10) { 400 printk("DEBUG: Unexpected IRQ %d\n", irq); 401 num_debug[irq]++; 402 } 403 return IRQ_HANDLED; 404} 405 406static int in_nmi; 407static volatile int nmi_hold; 408 409irqreturn_t mac_nmi_handler(int irq, void *dev_id) 410{ 411 int i; 412 /* 413 * generate debug output on NMI switch if 'debug' kernel option given 414 * (only works with Penguin!) 415 */ 416 417 in_nmi++; 418 for (i=0; i<100; i++) 419 udelay(1000); 420 421 if (in_nmi == 1) { 422 nmi_hold = 1; 423 printk("... pausing, press NMI to resume ..."); 424 } else { 425 printk(" ok!\n"); 426 nmi_hold = 0; 427 } 428 429 barrier(); 430 431 while (nmi_hold == 1) 432 udelay(1000); 433 434 if (console_loglevel >= 8) { 435 /* printk("NMI "); */ 436 } 437 in_nmi--; 438 return IRQ_HANDLED; 439} 440 441/* 442 * Simple routines for masking and unmasking 443 * SCC interrupts in cases where this can't be 444 * done in hardware (only the PSC can do that.) 445 */ 446 447static void scc_irq_enable(unsigned int irq) 448{ 449 int irq_idx = IRQ_IDX(irq); 450 451 scc_mask |= (1 << irq_idx); 452} 453 454static void scc_irq_disable(unsigned int irq) 455{ 456 int irq_idx = IRQ_IDX(irq); 457 458 scc_mask &= ~(1 << irq_idx); 459} 460 461/* 462 * SCC master interrupt handler. We have to do a bit of magic here 463 * to figure out what channel gave us the interrupt; putting this 464 * here is cleaner than hacking it into drivers/char/macserial.c. 465 */ 466 467void mac_scc_dispatch(int irq, void *dev_id) 468{ 469 volatile unsigned char *scc = (unsigned char *) mac_bi_data.sccbase + 2; 470 unsigned char reg; 471 unsigned long flags; 472 473 /* Read RR3 from the chip. Always do this on channel A */ 474 /* This must be an atomic operation so disable irqs. */ 475 476 local_irq_save(flags); 477 *scc = 3; 478 reg = *scc; 479 local_irq_restore(flags); 480 481 /* Now dispatch. Bits 0-2 are for channel B and */ 482 /* bits 3-5 are for channel A. We can safely */ 483 /* ignore the remaining bits here. */ 484 /* */ 485 /* Note that we're ignoring scc_mask for now. */ 486 /* If we actually mask the ints then we tend to */ 487 /* get hammered by very persistent SCC irqs, */ 488 /* and since they're autovector interrupts they */ 489 /* pretty much kill the system. */ 490 491 if (reg & 0x38) 492 m68k_handle_int(IRQ_SCCA); 493 if (reg & 0x07) 494 m68k_handle_int(IRQ_SCCB); 495} 496