1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved. 7 */ 8 9#include <linux/module.h> 10#include <linux/init.h> 11#include <linux/delay.h> 12#include <linux/kernel.h> 13#include <linux/kdev_t.h> 14#include <linux/string.h> 15#include <linux/screen_info.h> 16#include <linux/console.h> 17#include <linux/timex.h> 18#include <linux/sched.h> 19#include <linux/ioport.h> 20#include <linux/mm.h> 21#include <linux/serial.h> 22#include <linux/irq.h> 23#include <linux/bootmem.h> 24#include <linux/mmzone.h> 25#include <linux/interrupt.h> 26#include <linux/acpi.h> 27#include <linux/compiler.h> 28#include <linux/sched.h> 29#include <linux/root_dev.h> 30#include <linux/nodemask.h> 31#include <linux/pm.h> 32#include <linux/efi.h> 33 34#include <asm/io.h> 35#include <asm/sal.h> 36#include <asm/machvec.h> 37#include <asm/system.h> 38#include <asm/processor.h> 39#include <asm/vga.h> 40#include <asm/sn/arch.h> 41#include <asm/sn/addrs.h> 42#include <asm/sn/pda.h> 43#include <asm/sn/nodepda.h> 44#include <asm/sn/sn_cpuid.h> 45#include <asm/sn/simulator.h> 46#include <asm/sn/leds.h> 47#include <asm/sn/bte.h> 48#include <asm/sn/shub_mmr.h> 49#include <asm/sn/clksupport.h> 50#include <asm/sn/sn_sal.h> 51#include <asm/sn/geo.h> 52#include <asm/sn/sn_feature_sets.h> 53#include "xtalk/xwidgetdev.h" 54#include "xtalk/hubdev.h" 55#include <asm/sn/klconfig.h> 56 57 58DEFINE_PER_CPU(struct pda_s, pda_percpu); 59 60#define MAX_PHYS_MEMORY (1UL << IA64_MAX_PHYS_BITS) /* Max physical address supported */ 61 62extern void bte_init_node(nodepda_t *, cnodeid_t); 63 64extern void sn_timer_init(void); 65extern unsigned long last_time_offset; 66extern void (*ia64_mark_idle) (int); 67extern void snidle(int); 68extern unsigned long long (*ia64_printk_clock)(void); 69 70unsigned long sn_rtc_cycles_per_second; 71EXPORT_SYMBOL(sn_rtc_cycles_per_second); 72 73DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info); 74EXPORT_PER_CPU_SYMBOL(__sn_hub_info); 75 76DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]); 77EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid); 78 79DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda); 80EXPORT_PER_CPU_SYMBOL(__sn_nodepda); 81 82char sn_system_serial_number_string[128]; 83EXPORT_SYMBOL(sn_system_serial_number_string); 84u64 sn_partition_serial_number; 85EXPORT_SYMBOL(sn_partition_serial_number); 86u8 sn_partition_id; 87EXPORT_SYMBOL(sn_partition_id); 88u8 sn_system_size; 89EXPORT_SYMBOL(sn_system_size); 90u8 sn_sharing_domain_size; 91EXPORT_SYMBOL(sn_sharing_domain_size); 92u8 sn_coherency_id; 93EXPORT_SYMBOL(sn_coherency_id); 94u8 sn_region_size; 95EXPORT_SYMBOL(sn_region_size); 96int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */ 97 98short physical_node_map[MAX_NUMALINK_NODES]; 99static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS]; 100 101EXPORT_SYMBOL(physical_node_map); 102 103int num_cnodes; 104 105static void sn_init_pdas(char **); 106static void build_cnode_tables(void); 107 108static nodepda_t *nodepdaindr[MAX_COMPACT_NODES]; 109 110/* 111 * The format of "screen_info" is strange, and due to early i386-setup 112 * code. This is just enough to make the console code think we're on a 113 * VGA color display. 114 */ 115struct screen_info sn_screen_info = { 116 .orig_x = 0, 117 .orig_y = 0, 118 .orig_video_mode = 3, 119 .orig_video_cols = 80, 120 .orig_video_ega_bx = 3, 121 .orig_video_lines = 25, 122 .orig_video_isVGA = 1, 123 .orig_video_points = 16 124}; 125 126/* 127 * This routine can only be used during init, since 128 * smp_boot_data is an init data structure. 129 * We have to use smp_boot_data.cpu_phys_id to find 130 * the physical id of the processor because the normal 131 * cpu_physical_id() relies on data structures that 132 * may not be initialized yet. 133 */ 134 135static int __init pxm_to_nasid(int pxm) 136{ 137 int i; 138 int nid; 139 140 nid = pxm_to_node(pxm); 141 for (i = 0; i < num_node_memblks; i++) { 142 if (node_memblk[i].nid == nid) { 143 return NASID_GET(node_memblk[i].start_paddr); 144 } 145 } 146 return -1; 147} 148 149/** 150 * early_sn_setup - early setup routine for SN platforms 151 * 152 * Sets up an initial console to aid debugging. Intended primarily 153 * for bringup. See start_kernel() in init/main.c. 154 */ 155 156void __init early_sn_setup(void) 157{ 158 efi_system_table_t *efi_systab; 159 efi_config_table_t *config_tables; 160 struct ia64_sal_systab *sal_systab; 161 struct ia64_sal_desc_entry_point *ep; 162 char *p; 163 int i, j; 164 165 /* 166 * Parse enough of the SAL tables to locate the SAL entry point. Since, console 167 * IO on SN2 is done via SAL calls, early_printk won't work without this. 168 * 169 * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c. 170 * Any changes to those file may have to be made here as well. 171 */ 172 efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab); 173 config_tables = __va(efi_systab->tables); 174 for (i = 0; i < efi_systab->nr_tables; i++) { 175 if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == 176 0) { 177 sal_systab = __va(config_tables[i].table); 178 p = (char *)(sal_systab + 1); 179 for (j = 0; j < sal_systab->entry_count; j++) { 180 if (*p == SAL_DESC_ENTRY_POINT) { 181 ep = (struct ia64_sal_desc_entry_point 182 *)p; 183 ia64_sal_handler_init(__va 184 (ep->sal_proc), 185 __va(ep->gp)); 186 return; 187 } 188 p += SAL_DESC_SIZE(*p); 189 } 190 } 191 } 192 /* Uh-oh, SAL not available?? */ 193 printk(KERN_ERR "failed to find SAL entry point\n"); 194} 195 196extern int platform_intr_list[]; 197static int __cpuinitdata shub_1_1_found; 198 199/* 200 * sn_check_for_wars 201 * 202 * Set flag for enabling shub specific wars 203 */ 204 205static inline int __init is_shub_1_1(int nasid) 206{ 207 unsigned long id; 208 int rev; 209 210 if (is_shub2()) 211 return 0; 212 id = REMOTE_HUB_L(nasid, SH1_SHUB_ID); 213 rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT; 214 return rev <= 2; 215} 216 217static void __init sn_check_for_wars(void) 218{ 219 int cnode; 220 221 if (is_shub2()) { 222 /* none yet */ 223 } else { 224 for_each_online_node(cnode) { 225 if (is_shub_1_1(cnodeid_to_nasid(cnode))) 226 shub_1_1_found = 1; 227 } 228 } 229} 230 231/* 232 * Scan the EFI PCDP table (if it exists) for an acceptable VGA console 233 * output device. If one exists, pick it and set sn_legacy_{io,mem} to 234 * reflect the bus offsets needed to address it. 235 * 236 * Since pcdp support in SN is not supported in the 2.4 kernel (or at least 237 * the one lbs is based on) just declare the needed structs here. 238 * 239 * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf 240 * 241 * Returns 0 if no acceptable vga is found, !0 otherwise. 242 * 243 * Note: This stuff is duped here because Altix requires the PCDP to 244 * locate a usable VGA device due to lack of proper ACPI support. Structures 245 * could be used from drivers/firmware/pcdp.h, but it was decided that moving 246 * this file to a more public location just for Altix use was undesireable. 247 */ 248 249struct hcdp_uart_desc { 250 u8 pad[45]; 251}; 252 253struct pcdp { 254 u8 signature[4]; /* should be 'HCDP' */ 255 u32 length; 256 u8 rev; /* should be >=3 for pcdp, <3 for hcdp */ 257 u8 sum; 258 u8 oem_id[6]; 259 u64 oem_tableid; 260 u32 oem_rev; 261 u32 creator_id; 262 u32 creator_rev; 263 u32 num_type0; 264 struct hcdp_uart_desc uart[0]; /* num_type0 of these */ 265 /* pcdp descriptors follow */ 266} __attribute__((packed)); 267 268struct pcdp_device_desc { 269 u8 type; 270 u8 primary; 271 u16 length; 272 u16 index; 273 /* interconnect specific structure follows */ 274 /* device specific structure follows that */ 275} __attribute__((packed)); 276 277struct pcdp_interface_pci { 278 u8 type; /* 1 == pci */ 279 u8 reserved; 280 u16 length; 281 u8 segment; 282 u8 bus; 283 u8 dev; 284 u8 fun; 285 u16 devid; 286 u16 vendid; 287 u32 acpi_interrupt; 288 u64 mmio_tra; 289 u64 ioport_tra; 290 u8 flags; 291 u8 translation; 292} __attribute__((packed)); 293 294struct pcdp_vga_device { 295 u8 num_eas_desc; 296 /* ACPI Extended Address Space Desc follows */ 297} __attribute__((packed)); 298 299/* from pcdp_device_desc.primary */ 300#define PCDP_PRIMARY_CONSOLE 0x01 301 302/* from pcdp_device_desc.type */ 303#define PCDP_CONSOLE_INOUT 0x0 304#define PCDP_CONSOLE_DEBUG 0x1 305#define PCDP_CONSOLE_OUT 0x2 306#define PCDP_CONSOLE_IN 0x3 307#define PCDP_CONSOLE_TYPE_VGA 0x8 308 309#define PCDP_CONSOLE_VGA (PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT) 310 311/* from pcdp_interface_pci.type */ 312#define PCDP_IF_PCI 1 313 314/* from pcdp_interface_pci.translation */ 315#define PCDP_PCI_TRANS_IOPORT 0x02 316#define PCDP_PCI_TRANS_MMIO 0x01 317 318#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 319static void 320sn_scan_pcdp(void) 321{ 322 u8 *bp; 323 struct pcdp *pcdp; 324 struct pcdp_device_desc device; 325 struct pcdp_interface_pci if_pci; 326 extern struct efi efi; 327 328 if (efi.hcdp == EFI_INVALID_TABLE_ADDR) 329 return; /* no hcdp/pcdp table */ 330 331 pcdp = __va(efi.hcdp); 332 333 if (pcdp->rev < 3) 334 return; /* only support PCDP (rev >= 3) */ 335 336 for (bp = (u8 *)&pcdp->uart[pcdp->num_type0]; 337 bp < (u8 *)pcdp + pcdp->length; 338 bp += device.length) { 339 memcpy(&device, bp, sizeof(device)); 340 if (! (device.primary & PCDP_PRIMARY_CONSOLE)) 341 continue; /* not primary console */ 342 343 if (device.type != PCDP_CONSOLE_VGA) 344 continue; /* not VGA descriptor */ 345 346 memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci)); 347 if (if_pci.type != PCDP_IF_PCI) 348 continue; /* not PCI interconnect */ 349 350 if (if_pci.translation & PCDP_PCI_TRANS_IOPORT) 351 vga_console_iobase = if_pci.ioport_tra; 352 353 if (if_pci.translation & PCDP_PCI_TRANS_MMIO) 354 vga_console_membase = 355 if_pci.mmio_tra | __IA64_UNCACHED_OFFSET; 356 357 break; /* once we find the primary, we're done */ 358 } 359} 360#endif 361 362static unsigned long sn2_rtc_initial; 363 364static unsigned long long ia64_sn2_printk_clock(void) 365{ 366 unsigned long rtc_now = rtc_time(); 367 368 return (rtc_now - sn2_rtc_initial) * 369 (1000000000 / sn_rtc_cycles_per_second); 370} 371 372/** 373 * sn_setup - SN platform setup routine 374 * @cmdline_p: kernel command line 375 * 376 * Handles platform setup for SN machines. This includes determining 377 * the RTC frequency (via a SAL call), initializing secondary CPUs, and 378 * setting up per-node data areas. The console is also initialized here. 379 */ 380void __init sn_setup(char **cmdline_p) 381{ 382 long status, ticks_per_sec, drift; 383 u32 version = sn_sal_rev(); 384 extern void sn_cpu_init(void); 385 386 sn2_rtc_initial = rtc_time(); 387 ia64_sn_plat_set_error_handling_features(); // obsolete 388 ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV); 389 ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES); 390 /* 391 * Note: The calls to notify the PROM of ACPI and PCI Segment 392 * support must be done prior to acpi_load_tables(), as 393 * an ACPI capable PROM will rebuild the DSDT as result 394 * of the call. 395 */ 396 ia64_sn_set_os_feature(OSF_PCISEGMENT_ENABLE); 397 ia64_sn_set_os_feature(OSF_ACPI_ENABLE); 398 399 /* Load the new DSDT and SSDT tables into the global table list. */ 400 acpi_table_init(); 401 402#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 403 404 if (! vga_console_membase) 405 sn_scan_pcdp(); 406 407 /* 408 * Setup legacy IO space. 409 * vga_console_iobase maps to PCI IO Space address 0 on the 410 * bus containing the VGA console. 411 */ 412 if (vga_console_iobase) { 413 io_space[0].mmio_base = 414 (unsigned long) ioremap(vga_console_iobase, 0); 415 io_space[0].sparse = 0; 416 } 417 418 if (vga_console_membase) { 419 /* usable vga ... make tty0 the preferred default console */ 420 if (!strstr(*cmdline_p, "console=")) 421 add_preferred_console("tty", 0, NULL); 422 } else { 423 printk(KERN_DEBUG "SGI: Disabling VGA console\n"); 424 if (!strstr(*cmdline_p, "console=")) 425 add_preferred_console("ttySG", 0, NULL); 426#ifdef CONFIG_DUMMY_CONSOLE 427 conswitchp = &dummy_con; 428#else 429 conswitchp = NULL; 430#endif /* CONFIG_DUMMY_CONSOLE */ 431 } 432#endif /* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */ 433 434 MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY; 435 436 /* 437 * Build the tables for managing cnodes. 438 */ 439 build_cnode_tables(); 440 441 status = 442 ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, 443 &drift); 444 if (status != 0 || ticks_per_sec < 100000) { 445 printk(KERN_WARNING 446 "unable to determine platform RTC clock frequency, guessing.\n"); 447 /* PROM gives wrong value for clock freq. so guess */ 448 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 449 } else 450 sn_rtc_cycles_per_second = ticks_per_sec; 451 452 platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR; 453 454 ia64_printk_clock = ia64_sn2_printk_clock; 455 456 printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF); 457 458 /* 459 * we set the default root device to /dev/hda 460 * to make simulation easy 461 */ 462 ROOT_DEV = Root_HDA1; 463 464 /* 465 * Create the PDAs and NODEPDAs for all the cpus. 466 */ 467 sn_init_pdas(cmdline_p); 468 469 ia64_mark_idle = &snidle; 470 471 /* 472 * For the bootcpu, we do this here. All other cpus will make the 473 * call as part of cpu_init in slave cpu initialization. 474 */ 475 sn_cpu_init(); 476 477#ifdef CONFIG_SMP 478 init_smp_config(); 479#endif 480 screen_info = sn_screen_info; 481 482 sn_timer_init(); 483 484 /* 485 * set pm_power_off to a SAL call to allow 486 * sn machines to power off. The SAL call can be replaced 487 * by an ACPI interface call when ACPI is fully implemented 488 * for sn. 489 */ 490 pm_power_off = ia64_sn_power_down; 491 current->thread.flags |= IA64_THREAD_MIGRATION; 492} 493 494/** 495 * sn_init_pdas - setup node data areas 496 * 497 * One time setup for Node Data Area. Called by sn_setup(). 498 */ 499static void __init sn_init_pdas(char **cmdline_p) 500{ 501 cnodeid_t cnode; 502 503 /* 504 * Allocate & initalize the nodepda for each node. 505 */ 506 for_each_online_node(cnode) { 507 nodepdaindr[cnode] = 508 alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t)); 509 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); 510 memset(nodepdaindr[cnode]->phys_cpuid, -1, 511 sizeof(nodepdaindr[cnode]->phys_cpuid)); 512 spin_lock_init(&nodepdaindr[cnode]->ptc_lock); 513 } 514 515 /* 516 * Allocate & initialize nodepda for TIOs. For now, put them on node 0. 517 */ 518 for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) { 519 nodepdaindr[cnode] = 520 alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t)); 521 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); 522 } 523 524 /* 525 * Now copy the array of nodepda pointers to each nodepda. 526 */ 527 for (cnode = 0; cnode < num_cnodes; cnode++) 528 memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr, 529 sizeof(nodepdaindr)); 530 531 /* 532 * Set up IO related platform-dependent nodepda fields. 533 * The following routine actually sets up the hubinfo struct 534 * in nodepda. 535 */ 536 for_each_online_node(cnode) { 537 bte_init_node(nodepdaindr[cnode], cnode); 538 } 539 540 /* 541 * Initialize the per node hubdev. This includes IO Nodes and 542 * headless/memless nodes. 543 */ 544 for (cnode = 0; cnode < num_cnodes; cnode++) { 545 hubdev_init_node(nodepdaindr[cnode], cnode); 546 } 547} 548 549/** 550 * sn_cpu_init - initialize per-cpu data areas 551 * @cpuid: cpuid of the caller 552 * 553 * Called during cpu initialization on each cpu as it starts. 554 * Currently, initializes the per-cpu data area for SNIA. 555 * Also sets up a few fields in the nodepda. Also known as 556 * platform_cpu_init() by the ia64 machvec code. 557 */ 558void __cpuinit sn_cpu_init(void) 559{ 560 int cpuid; 561 int cpuphyid; 562 int nasid; 563 int subnode; 564 int slice; 565 int cnode; 566 int i; 567 static int wars_have_been_checked, set_cpu0_number; 568 569 cpuid = smp_processor_id(); 570 if (cpuid == 0 && IS_MEDUSA()) { 571 if (ia64_sn_is_fake_prom()) 572 sn_prom_type = 2; 573 else 574 sn_prom_type = 1; 575 printk(KERN_INFO "Running on medusa with %s PROM\n", 576 (sn_prom_type == 1) ? "real" : "fake"); 577 } 578 579 memset(pda, 0, sizeof(pda)); 580 if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, 581 &sn_hub_info->nasid_bitmask, 582 &sn_hub_info->nasid_shift, 583 &sn_system_size, &sn_sharing_domain_size, 584 &sn_partition_id, &sn_coherency_id, 585 &sn_region_size)) 586 BUG(); 587 sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2; 588 589 /* 590 * Don't check status. The SAL call is not supported on all PROMs 591 * but a failure is harmless. 592 * Architechtuallly, cpu_init is always called twice on cpu 0. We 593 * should set cpu_number on cpu 0 once. 594 */ 595 if (cpuid == 0) { 596 if (!set_cpu0_number) { 597 (void) ia64_sn_set_cpu_number(cpuid); 598 set_cpu0_number = 1; 599 } 600 } else 601 (void) ia64_sn_set_cpu_number(cpuid); 602 603 /* 604 * The boot cpu makes this call again after platform initialization is 605 * complete. 606 */ 607 if (nodepdaindr[0] == NULL) 608 return; 609 610 for (i = 0; i < MAX_PROM_FEATURE_SETS; i++) 611 if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0) 612 break; 613 614 cpuphyid = get_sapicid(); 615 616 if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice)) 617 BUG(); 618 619 for (i=0; i < MAX_NUMNODES; i++) { 620 if (nodepdaindr[i]) { 621 nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid; 622 nodepdaindr[i]->phys_cpuid[cpuid].slice = slice; 623 nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode; 624 } 625 } 626 627 cnode = nasid_to_cnodeid(nasid); 628 629 sn_nodepda = nodepdaindr[cnode]; 630 631 pda->led_address = 632 (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT)); 633 pda->led_state = LED_ALWAYS_SET; 634 pda->hb_count = HZ / 2; 635 pda->hb_state = 0; 636 pda->idle_flag = 0; 637 638 if (cpuid != 0) { 639 /* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */ 640 memcpy(sn_cnodeid_to_nasid, 641 (&per_cpu(__sn_cnodeid_to_nasid, 0)), 642 sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid))); 643 } 644 645 /* 646 * Check for WARs. 647 * Only needs to be done once, on BSP. 648 * Has to be done after loop above, because it uses this cpu's 649 * sn_cnodeid_to_nasid table which was just initialized if this 650 * isn't cpu 0. 651 * Has to be done before assignment below. 652 */ 653 if (!wars_have_been_checked) { 654 sn_check_for_wars(); 655 wars_have_been_checked = 1; 656 } 657 sn_hub_info->shub_1_1_found = shub_1_1_found; 658 659 /* 660 * Set up addresses of PIO/MEM write status registers. 661 */ 662 { 663 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0}; 664 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2, 665 SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3}; 666 u64 *pio; 667 pio = is_shub1() ? pio1 : pio2; 668 pda->pio_write_status_addr = 669 (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]); 670 pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0; 671 } 672 673 /* 674 * WAR addresses for SHUB 1.x. 675 */ 676 if (local_node_data->active_cpu_count++ == 0 && is_shub1()) { 677 int buddy_nasid; 678 buddy_nasid = 679 cnodeid_to_nasid(numa_node_id() == 680 num_online_nodes() - 1 ? 0 : numa_node_id() + 1); 681 pda->pio_shub_war_cam_addr = 682 (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, 683 SH1_PI_CAM_CONTROL); 684 } 685} 686 687/* 688 * Build tables for converting between NASIDs and cnodes. 689 */ 690static inline int __init board_needs_cnode(int type) 691{ 692 return (type == KLTYPE_SNIA || type == KLTYPE_TIO); 693} 694 695void __init build_cnode_tables(void) 696{ 697 int nasid; 698 int node; 699 lboard_t *brd; 700 701 memset(physical_node_map, -1, sizeof(physical_node_map)); 702 memset(sn_cnodeid_to_nasid, -1, 703 sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid))); 704 705 /* 706 * First populate the tables with C/M bricks. This ensures that 707 * cnode == node for all C & M bricks. 708 */ 709 for_each_online_node(node) { 710 nasid = pxm_to_nasid(node_to_pxm(node)); 711 sn_cnodeid_to_nasid[node] = nasid; 712 physical_node_map[nasid] = node; 713 } 714 715 /* 716 * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node 717 * limit on the number of nodes, we can't use the generic node numbers 718 * for this. Note that num_cnodes is incremented below as TIOs or 719 * headless/memoryless nodes are discovered. 720 */ 721 num_cnodes = num_online_nodes(); 722 723 /* fakeprom does not support klgraph */ 724 if (IS_RUNNING_ON_FAKE_PROM()) 725 return; 726 727 /* Find TIOs & headless/memoryless nodes and add them to the tables */ 728 for_each_online_node(node) { 729 kl_config_hdr_t *klgraph_header; 730 nasid = cnodeid_to_nasid(node); 731 klgraph_header = ia64_sn_get_klconfig_addr(nasid); 732 if (klgraph_header == NULL) 733 BUG(); 734 brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info); 735 while (brd) { 736 if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) { 737 sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid; 738 physical_node_map[brd->brd_nasid] = num_cnodes++; 739 } 740 brd = find_lboard_next(brd); 741 } 742 } 743} 744 745int 746nasid_slice_to_cpuid(int nasid, int slice) 747{ 748 long cpu; 749 750 for (cpu = 0; cpu < NR_CPUS; cpu++) 751 if (cpuid_to_nasid(cpu) == nasid && 752 cpuid_to_slice(cpu) == slice) 753 return cpu; 754 755 return -1; 756} 757 758int sn_prom_feature_available(int id) 759{ 760 if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS) 761 return 0; 762 return test_bit(id, sn_prom_features); 763} 764 765void 766sn_kernel_launch_event(void) 767{ 768 /* ignore status until we understand possible failure, if any*/ 769 if (ia64_sn_kernel_launch_event()) 770 printk(KERN_ERR "KEXEC is not supported in this PROM, Please update the PROM.\n"); 771} 772EXPORT_SYMBOL(sn_prom_feature_available); 773