1#include <linux/clocksource.h> 2#include <linux/clockchips.h> 3#include <linux/errno.h> 4#include <linux/hpet.h> 5#include <linux/init.h> 6#include <linux/sysdev.h> 7#include <linux/pm.h> 8 9#include <asm/hpet.h> 10#include <asm/io.h> 11 12extern struct clock_event_device *global_clock_event; 13 14#define HPET_MASK CLOCKSOURCE_MASK(32) 15#define HPET_SHIFT 22 16 17/* FSEC = 10^-15 NSEC = 10^-9 */ 18#define FSEC_PER_NSEC 1000000 19 20/* 21 * HPET address is set in acpi/boot.c, when an ACPI entry exists 22 */ 23unsigned long hpet_address; 24static void __iomem * hpet_virt_address; 25 26static inline unsigned long hpet_readl(unsigned long a) 27{ 28 return readl(hpet_virt_address + a); 29} 30 31static inline void hpet_writel(unsigned long d, unsigned long a) 32{ 33 writel(d, hpet_virt_address + a); 34} 35 36/* 37 * HPET command line enable / disable 38 */ 39static int boot_hpet_disable; 40 41static int __init hpet_setup(char* str) 42{ 43 if (str) { 44 if (!strncmp("disable", str, 7)) 45 boot_hpet_disable = 1; 46 } 47 return 1; 48} 49__setup("hpet=", hpet_setup); 50 51static inline int is_hpet_capable(void) 52{ 53 return (!boot_hpet_disable && hpet_address); 54} 55 56/* 57 * HPET timer interrupt enable / disable 58 */ 59static int hpet_legacy_int_enabled; 60 61/** 62 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 63 */ 64int is_hpet_enabled(void) 65{ 66 return is_hpet_capable() && hpet_legacy_int_enabled; 67} 68 69/* 70 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 71 * timer 0 and timer 1 in case of RTC emulation. 72 */ 73#ifdef CONFIG_HPET 74static void hpet_reserve_platform_timers(unsigned long id) 75{ 76 struct hpet __iomem *hpet = hpet_virt_address; 77 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 78 unsigned int nrtimers, i; 79 struct hpet_data hd; 80 81 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 82 83 memset(&hd, 0, sizeof (hd)); 84 hd.hd_phys_address = hpet_address; 85 hd.hd_address = hpet_virt_address; 86 hd.hd_nirqs = nrtimers; 87 hd.hd_flags = HPET_DATA_PLATFORM; 88 hpet_reserve_timer(&hd, 0); 89 90#ifdef CONFIG_HPET_EMULATE_RTC 91 hpet_reserve_timer(&hd, 1); 92#endif 93 94 hd.hd_irq[0] = HPET_LEGACY_8254; 95 hd.hd_irq[1] = HPET_LEGACY_RTC; 96 97 for (i = 2; i < nrtimers; timer++, i++) 98 hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> 99 Tn_INT_ROUTE_CNF_SHIFT; 100 101 hpet_alloc(&hd); 102 103} 104#else 105static void hpet_reserve_platform_timers(unsigned long id) { } 106#endif 107 108/* 109 * Common hpet info 110 */ 111static unsigned long hpet_period; 112 113static void hpet_set_mode(enum clock_event_mode mode, 114 struct clock_event_device *evt); 115static int hpet_next_event(unsigned long delta, 116 struct clock_event_device *evt); 117 118/* 119 * The hpet clock event device 120 */ 121static struct clock_event_device hpet_clockevent = { 122 .name = "hpet", 123 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 124 .set_mode = hpet_set_mode, 125 .set_next_event = hpet_next_event, 126 .shift = 32, 127 .irq = 0, 128}; 129 130static void hpet_start_counter(void) 131{ 132 unsigned long cfg = hpet_readl(HPET_CFG); 133 134 cfg &= ~HPET_CFG_ENABLE; 135 hpet_writel(cfg, HPET_CFG); 136 hpet_writel(0, HPET_COUNTER); 137 hpet_writel(0, HPET_COUNTER + 4); 138 cfg |= HPET_CFG_ENABLE; 139 hpet_writel(cfg, HPET_CFG); 140} 141 142static void hpet_enable_int(void) 143{ 144 unsigned long cfg = hpet_readl(HPET_CFG); 145 146 cfg |= HPET_CFG_LEGACY; 147 hpet_writel(cfg, HPET_CFG); 148 hpet_legacy_int_enabled = 1; 149} 150 151static void hpet_set_mode(enum clock_event_mode mode, 152 struct clock_event_device *evt) 153{ 154 unsigned long cfg, cmp, now; 155 uint64_t delta; 156 157 switch(mode) { 158 case CLOCK_EVT_MODE_PERIODIC: 159 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; 160 delta >>= hpet_clockevent.shift; 161 now = hpet_readl(HPET_COUNTER); 162 cmp = now + (unsigned long) delta; 163 cfg = hpet_readl(HPET_T0_CFG); 164 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 165 HPET_TN_SETVAL | HPET_TN_32BIT; 166 hpet_writel(cfg, HPET_T0_CFG); 167 /* 168 * The first write after writing TN_SETVAL to the 169 * config register sets the counter value, the second 170 * write sets the period. 171 */ 172 hpet_writel(cmp, HPET_T0_CMP); 173 udelay(1); 174 hpet_writel((unsigned long) delta, HPET_T0_CMP); 175 break; 176 177 case CLOCK_EVT_MODE_ONESHOT: 178 cfg = hpet_readl(HPET_T0_CFG); 179 cfg &= ~HPET_TN_PERIODIC; 180 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 181 hpet_writel(cfg, HPET_T0_CFG); 182 break; 183 184 case CLOCK_EVT_MODE_UNUSED: 185 case CLOCK_EVT_MODE_SHUTDOWN: 186 cfg = hpet_readl(HPET_T0_CFG); 187 cfg &= ~HPET_TN_ENABLE; 188 hpet_writel(cfg, HPET_T0_CFG); 189 break; 190 } 191} 192 193static int hpet_next_event(unsigned long delta, 194 struct clock_event_device *evt) 195{ 196 unsigned long cnt; 197 198 cnt = hpet_readl(HPET_COUNTER); 199 cnt += delta; 200 hpet_writel(cnt, HPET_T0_CMP); 201 202 return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0; 203} 204 205/* 206 * Clock source related code 207 */ 208static cycle_t read_hpet(void) 209{ 210 return (cycle_t)hpet_readl(HPET_COUNTER); 211} 212 213static struct clocksource clocksource_hpet = { 214 .name = "hpet", 215 .rating = 250, 216 .read = read_hpet, 217 .mask = HPET_MASK, 218 .shift = HPET_SHIFT, 219 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 220}; 221 222/* 223 * Try to setup the HPET timer 224 */ 225int __init hpet_enable(void) 226{ 227 unsigned long id; 228 uint64_t hpet_freq; 229 u64 tmp; 230 231 if (!is_hpet_capable()) 232 return 0; 233 234 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 235 236 /* 237 * Read the period and check for a sane value: 238 */ 239 hpet_period = hpet_readl(HPET_PERIOD); 240 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 241 goto out_nohpet; 242 243 /* 244 * The period is a femto seconds value. We need to calculate the 245 * scaled math multiplication factor for nanosecond to hpet tick 246 * conversion. 247 */ 248 hpet_freq = 1000000000000000ULL; 249 do_div(hpet_freq, hpet_period); 250 hpet_clockevent.mult = div_sc((unsigned long) hpet_freq, 251 NSEC_PER_SEC, 32); 252 /* Calculate the min / max delta */ 253 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 254 &hpet_clockevent); 255 hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30, 256 &hpet_clockevent); 257 258 /* 259 * Read the HPET ID register to retrieve the IRQ routing 260 * information and the number of channels 261 */ 262 id = hpet_readl(HPET_ID); 263 264#ifdef CONFIG_HPET_EMULATE_RTC 265 /* 266 * The legacy routing mode needs at least two channels, tick timer 267 * and the rtc emulation channel. 268 */ 269 if (!(id & HPET_ID_NUMBER)) 270 goto out_nohpet; 271#endif 272 273 /* Start the counter */ 274 hpet_start_counter(); 275 276 /* Initialize and register HPET clocksource 277 * 278 * hpet period is in femto seconds per cycle 279 * so we need to convert this to ns/cyc units 280 * aproximated by mult/2^shift 281 * 282 * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift 283 * fsec/cyc * 1ns/1000000fsec * 2^shift = mult 284 * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult 285 * (fsec/cyc << shift)/1000000 = mult 286 * (hpet_period << shift)/FSEC_PER_NSEC = mult 287 */ 288 tmp = (u64)hpet_period << HPET_SHIFT; 289 do_div(tmp, FSEC_PER_NSEC); 290 clocksource_hpet.mult = (u32)tmp; 291 292 clocksource_register(&clocksource_hpet); 293 294 295 if (id & HPET_ID_LEGSUP) { 296 hpet_enable_int(); 297 hpet_reserve_platform_timers(id); 298 /* 299 * Start hpet with the boot cpu mask and make it 300 * global after the IO_APIC has been initialized. 301 */ 302 hpet_clockevent.cpumask =cpumask_of_cpu(0); 303 clockevents_register_device(&hpet_clockevent); 304 global_clock_event = &hpet_clockevent; 305 return 1; 306 } 307 return 0; 308 309out_nohpet: 310 iounmap(hpet_virt_address); 311 hpet_virt_address = NULL; 312 boot_hpet_disable = 1; 313 return 0; 314} 315 316 317#ifdef CONFIG_HPET_EMULATE_RTC 318 319/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 320 * is enabled, we support RTC interrupt functionality in software. 321 * RTC has 3 kinds of interrupts: 322 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 323 * is updated 324 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 325 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 326 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 327 * (1) and (2) above are implemented using polling at a frequency of 328 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 329 * overhead. (DEFAULT_RTC_INT_FREQ) 330 * For (3), we use interrupts at 64Hz or user specified periodic 331 * frequency, whichever is higher. 332 */ 333#include <linux/mc146818rtc.h> 334#include <linux/rtc.h> 335 336#define DEFAULT_RTC_INT_FREQ 64 337#define DEFAULT_RTC_SHIFT 6 338#define RTC_NUM_INTS 1 339 340static unsigned long hpet_rtc_flags; 341static unsigned long hpet_prev_update_sec; 342static struct rtc_time hpet_alarm_time; 343static unsigned long hpet_pie_count; 344static unsigned long hpet_t1_cmp; 345static unsigned long hpet_default_delta; 346static unsigned long hpet_pie_delta; 347static unsigned long hpet_pie_limit; 348 349/* 350 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 351 * is not supported by all HPET implementations for timer 1. 352 * 353 * hpet_rtc_timer_init() is called when the rtc is initialized. 354 */ 355int hpet_rtc_timer_init(void) 356{ 357 unsigned long cfg, cnt, delta, flags; 358 359 if (!is_hpet_enabled()) 360 return 0; 361 362 if (!hpet_default_delta) { 363 uint64_t clc; 364 365 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 366 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 367 hpet_default_delta = (unsigned long) clc; 368 } 369 370 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 371 delta = hpet_default_delta; 372 else 373 delta = hpet_pie_delta; 374 375 local_irq_save(flags); 376 377 cnt = delta + hpet_readl(HPET_COUNTER); 378 hpet_writel(cnt, HPET_T1_CMP); 379 hpet_t1_cmp = cnt; 380 381 cfg = hpet_readl(HPET_T1_CFG); 382 cfg &= ~HPET_TN_PERIODIC; 383 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 384 hpet_writel(cfg, HPET_T1_CFG); 385 386 local_irq_restore(flags); 387 388 return 1; 389} 390 391/* 392 * The functions below are called from rtc driver. 393 * Return 0 if HPET is not being used. 394 * Otherwise do the necessary changes and return 1. 395 */ 396int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 397{ 398 if (!is_hpet_enabled()) 399 return 0; 400 401 hpet_rtc_flags &= ~bit_mask; 402 return 1; 403} 404 405int hpet_set_rtc_irq_bit(unsigned long bit_mask) 406{ 407 unsigned long oldbits = hpet_rtc_flags; 408 409 if (!is_hpet_enabled()) 410 return 0; 411 412 hpet_rtc_flags |= bit_mask; 413 414 if (!oldbits) 415 hpet_rtc_timer_init(); 416 417 return 1; 418} 419 420int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 421 unsigned char sec) 422{ 423 if (!is_hpet_enabled()) 424 return 0; 425 426 hpet_alarm_time.tm_hour = hrs; 427 hpet_alarm_time.tm_min = min; 428 hpet_alarm_time.tm_sec = sec; 429 430 return 1; 431} 432 433int hpet_set_periodic_freq(unsigned long freq) 434{ 435 uint64_t clc; 436 437 if (!is_hpet_enabled()) 438 return 0; 439 440 if (freq <= DEFAULT_RTC_INT_FREQ) 441 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 442 else { 443 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 444 do_div(clc, freq); 445 clc >>= hpet_clockevent.shift; 446 hpet_pie_delta = (unsigned long) clc; 447 } 448 return 1; 449} 450 451int hpet_rtc_dropped_irq(void) 452{ 453 return is_hpet_enabled(); 454} 455 456static void hpet_rtc_timer_reinit(void) 457{ 458 unsigned long cfg, delta; 459 int lost_ints = -1; 460 461 if (unlikely(!hpet_rtc_flags)) { 462 cfg = hpet_readl(HPET_T1_CFG); 463 cfg &= ~HPET_TN_ENABLE; 464 hpet_writel(cfg, HPET_T1_CFG); 465 return; 466 } 467 468 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 469 delta = hpet_default_delta; 470 else 471 delta = hpet_pie_delta; 472 473 /* 474 * Increment the comparator value until we are ahead of the 475 * current count. 476 */ 477 do { 478 hpet_t1_cmp += delta; 479 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 480 lost_ints++; 481 } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); 482 483 if (lost_ints) { 484 if (hpet_rtc_flags & RTC_PIE) 485 hpet_pie_count += lost_ints; 486 if (printk_ratelimit()) 487 printk(KERN_WARNING "rtc: lost %d interrupts\n", 488 lost_ints); 489 } 490} 491 492irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 493{ 494 struct rtc_time curr_time; 495 unsigned long rtc_int_flag = 0; 496 497 hpet_rtc_timer_reinit(); 498 499 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 500 rtc_get_rtc_time(&curr_time); 501 502 if (hpet_rtc_flags & RTC_UIE && 503 curr_time.tm_sec != hpet_prev_update_sec) { 504 rtc_int_flag = RTC_UF; 505 hpet_prev_update_sec = curr_time.tm_sec; 506 } 507 508 if (hpet_rtc_flags & RTC_PIE && 509 ++hpet_pie_count >= hpet_pie_limit) { 510 rtc_int_flag |= RTC_PF; 511 hpet_pie_count = 0; 512 } 513 514 if (hpet_rtc_flags & RTC_PIE && 515 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 516 (curr_time.tm_min == hpet_alarm_time.tm_min) && 517 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 518 rtc_int_flag |= RTC_AF; 519 520 if (rtc_int_flag) { 521 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 522 rtc_interrupt(rtc_int_flag, dev_id); 523 } 524 return IRQ_HANDLED; 525} 526#endif 527 528 529/* 530 * Suspend/resume part 531 */ 532 533#ifdef CONFIG_PM 534 535static int hpet_suspend(struct sys_device *sys_device, pm_message_t state) 536{ 537 unsigned long cfg = hpet_readl(HPET_CFG); 538 539 cfg &= ~(HPET_CFG_ENABLE|HPET_CFG_LEGACY); 540 hpet_writel(cfg, HPET_CFG); 541 542 return 0; 543} 544 545static int hpet_resume(struct sys_device *sys_device) 546{ 547 unsigned int id; 548 549 hpet_start_counter(); 550 551 id = hpet_readl(HPET_ID); 552 553 if (id & HPET_ID_LEGSUP) 554 hpet_enable_int(); 555 556 return 0; 557} 558 559static struct sysdev_class hpet_class = { 560 set_kset_name("hpet"), 561 .suspend = hpet_suspend, 562 .resume = hpet_resume, 563}; 564 565static struct sys_device hpet_device = { 566 .id = 0, 567 .cls = &hpet_class, 568}; 569 570 571static __init int hpet_register_sysfs(void) 572{ 573 int err; 574 575 if (!is_hpet_capable()) 576 return 0; 577 578 err = sysdev_class_register(&hpet_class); 579 580 if (!err) { 581 err = sysdev_register(&hpet_device); 582 if (err) 583 sysdev_class_unregister(&hpet_class); 584 } 585 586 return err; 587} 588 589device_initcall(hpet_register_sysfs); 590 591#endif 592