1/* unaligned.c: unalignment fixup handler for CPUs on which it is supported (FR451 only) 2 * 3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/sched.h> 13#include <linux/signal.h> 14#include <linux/kernel.h> 15#include <linux/mm.h> 16#include <linux/types.h> 17#include <linux/user.h> 18#include <linux/string.h> 19#include <linux/linkage.h> 20#include <linux/init.h> 21 22#include <asm/setup.h> 23#include <asm/system.h> 24#include <asm/uaccess.h> 25 26#define kdebug(fmt, ...) do {} while(0) 27 28#define _MA_SIGNED 0x01 29#define _MA_HALF 0x02 30#define _MA_WORD 0x04 31#define _MA_DWORD 0x08 32#define _MA_SZ_MASK 0x0e 33#define _MA_LOAD 0x10 34#define _MA_STORE 0x20 35#define _MA_UPDATE 0x40 36#define _MA_IMM 0x80 37 38#define _MA_LDxU _MA_LOAD | _MA_UPDATE 39#define _MA_LDxI _MA_LOAD | _MA_IMM 40#define _MA_STxU _MA_STORE | _MA_UPDATE 41#define _MA_STxI _MA_STORE | _MA_IMM 42 43static const uint8_t tbl_LDGRk_reg[0x40] = { 44 [0x02] = _MA_LOAD | _MA_HALF | _MA_SIGNED, /* LDSH @(GRi,GRj),GRk */ 45 [0x03] = _MA_LOAD | _MA_HALF, /* LDUH @(GRi,GRj),GRk */ 46 [0x04] = _MA_LOAD | _MA_WORD, /* LD @(GRi,GRj),GRk */ 47 [0x05] = _MA_LOAD | _MA_DWORD, /* LDD @(GRi,GRj),GRk */ 48 [0x12] = _MA_LDxU | _MA_HALF | _MA_SIGNED, /* LDSHU @(GRi,GRj),GRk */ 49 [0x13] = _MA_LDxU | _MA_HALF, /* LDUHU @(GRi,GRj),GRk */ 50 [0x14] = _MA_LDxU | _MA_WORD, /* LDU @(GRi,GRj),GRk */ 51 [0x15] = _MA_LDxU | _MA_DWORD, /* LDDU @(GRi,GRj),GRk */ 52}; 53 54static const uint8_t tbl_STGRk_reg[0x40] = { 55 [0x01] = _MA_STORE | _MA_HALF, /* STH @(GRi,GRj),GRk */ 56 [0x02] = _MA_STORE | _MA_WORD, /* ST @(GRi,GRj),GRk */ 57 [0x03] = _MA_STORE | _MA_DWORD, /* STD @(GRi,GRj),GRk */ 58 [0x11] = _MA_STxU | _MA_HALF, /* STHU @(GRi,GRj),GRk */ 59 [0x12] = _MA_STxU | _MA_WORD, /* STU @(GRi,GRj),GRk */ 60 [0x13] = _MA_STxU | _MA_DWORD, /* STDU @(GRi,GRj),GRk */ 61}; 62 63static const uint8_t tbl_LDSTGRk_imm[0x80] = { 64 [0x31] = _MA_LDxI | _MA_HALF | _MA_SIGNED, /* LDSHI @(GRi,d12),GRk */ 65 [0x32] = _MA_LDxI | _MA_WORD, /* LDI @(GRi,d12),GRk */ 66 [0x33] = _MA_LDxI | _MA_DWORD, /* LDDI @(GRi,d12),GRk */ 67 [0x36] = _MA_LDxI | _MA_HALF, /* LDUHI @(GRi,d12),GRk */ 68 [0x51] = _MA_STxI | _MA_HALF, /* STHI @(GRi,d12),GRk */ 69 [0x52] = _MA_STxI | _MA_WORD, /* STI @(GRi,d12),GRk */ 70 [0x53] = _MA_STxI | _MA_DWORD, /* STDI @(GRi,d12),GRk */ 71}; 72 73 74/*****************************************************************************/ 75/* 76 * see if we can handle the exception by fixing up a misaligned memory access 77 */ 78int handle_misalignment(unsigned long esr0, unsigned long ear0, unsigned long epcr0) 79{ 80 unsigned long insn, addr, *greg; 81 int GRi, GRj, GRk, D12, op; 82 83 union { 84 uint64_t _64; 85 uint32_t _32[2]; 86 uint16_t _16; 87 uint8_t _8[8]; 88 } x; 89 90 if (!(esr0 & ESR0_EAV) || !(epcr0 & EPCR0_V) || !(ear0 & 7)) 91 return -EAGAIN; 92 93 epcr0 &= EPCR0_PC; 94 95 if (__frame->pc != epcr0) { 96 kdebug("MISALIGN: Execution not halted on excepting instruction\n"); 97 BUG(); 98 } 99 100 if (__get_user(insn, (unsigned long *) epcr0) < 0) 101 return -EFAULT; 102 103 /* determine the instruction type first */ 104 switch ((insn >> 18) & 0x7f) { 105 case 0x2: 106 /* LDx @(GRi,GRj),GRk */ 107 op = tbl_LDGRk_reg[(insn >> 6) & 0x3f]; 108 break; 109 110 case 0x3: 111 /* STx GRk,@(GRi,GRj) */ 112 op = tbl_STGRk_reg[(insn >> 6) & 0x3f]; 113 break; 114 115 default: 116 op = tbl_LDSTGRk_imm[(insn >> 18) & 0x7f]; 117 break; 118 } 119 120 if (!op) 121 return -EAGAIN; 122 123 kdebug("MISALIGN: pc=%08lx insn=%08lx ad=%08lx op=%02x\n", epcr0, insn, ear0, op); 124 125 memset(&x, 0xba, 8); 126 127 /* validate the instruction parameters */ 128 greg = (unsigned long *) &__frame->tbr; 129 130 GRi = (insn >> 12) & 0x3f; 131 GRk = (insn >> 25) & 0x3f; 132 133 if (GRi > 31 || GRk > 31) 134 return -ENOENT; 135 136 if (op & _MA_DWORD && GRk & 1) 137 return -EINVAL; 138 139 if (op & _MA_IMM) { 140 D12 = insn & 0xfff; 141 asm ("slli %0,#20,%0 ! srai %0,#20,%0" : "=r"(D12) : "0"(D12)); /* sign extend */ 142 addr = (GRi ? greg[GRi] : 0) + D12; 143 } 144 else { 145 GRj = (insn >> 0) & 0x3f; 146 if (GRj > 31) 147 return -ENOENT; 148 addr = (GRi ? greg[GRi] : 0) + (GRj ? greg[GRj] : 0); 149 } 150 151 if (addr != ear0) { 152 kdebug("MISALIGN: Calculated addr (%08lx) does not match EAR0 (%08lx)\n", 153 addr, ear0); 154 return -EFAULT; 155 } 156 157 /* check the address is okay */ 158 if (user_mode(__frame) && ___range_ok(ear0, 8) < 0) 159 return -EFAULT; 160 161 /* perform the memory op */ 162 if (op & _MA_STORE) { 163 /* perform a store */ 164 x._32[0] = 0; 165 if (GRk != 0) { 166 if (op & _MA_HALF) { 167 x._16 = greg[GRk]; 168 } 169 else { 170 x._32[0] = greg[GRk]; 171 } 172 } 173 if (op & _MA_DWORD) 174 x._32[1] = greg[GRk + 1]; 175 176 kdebug("MISALIGN: Store GR%d { %08x:%08x } -> %08lx (%dB)\n", 177 GRk, x._32[1], x._32[0], addr, op & _MA_SZ_MASK); 178 179 if (__memcpy_user((void *) addr, &x, op & _MA_SZ_MASK) != 0) 180 return -EFAULT; 181 } 182 else { 183 /* perform a load */ 184 if (__memcpy_user(&x, (void *) addr, op & _MA_SZ_MASK) != 0) 185 return -EFAULT; 186 187 if (op & _MA_HALF) { 188 if (op & _MA_SIGNED) 189 asm ("slli %0,#16,%0 ! srai %0,#16,%0" 190 : "=r"(x._32[0]) : "0"(x._16)); 191 else 192 asm ("sethi #0,%0" 193 : "=r"(x._32[0]) : "0"(x._16)); 194 } 195 196 kdebug("MISALIGN: Load %08lx (%dB) -> GR%d, { %08x:%08x }\n", 197 addr, op & _MA_SZ_MASK, GRk, x._32[1], x._32[0]); 198 199 if (GRk != 0) 200 greg[GRk] = x._32[0]; 201 if (op & _MA_DWORD) 202 greg[GRk + 1] = x._32[1]; 203 } 204 205 /* update the base pointer if required */ 206 if (op & _MA_UPDATE) 207 greg[GRi] = addr; 208 209 /* well... we've done that insn */ 210 __frame->pc = __frame->pc + 4; 211 212 return 0; 213} /* end handle_misalignment() */ 214