1/* linux/arch/arm/plat-s3c24xx/devs.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 *	Ben Dooks <ben@simtec.co.uk>
5 *
6 * Base S3C24XX platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26#include <asm/arch/fb.h>
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30
31#include <asm/arch/regs-serial.h>
32#include <asm/arch/udc.h>
33
34#include <asm/plat-s3c24xx/devs.h>
35#include <asm/plat-s3c24xx/cpu.h>
36#include <asm/arch/regs-spi.h>
37
38/* Serial port registrations */
39
40static struct resource s3c2410_uart0_resource[] = {
41	[0] = {
42		.start = S3C2410_PA_UART0,
43		.end   = S3C2410_PA_UART0 + 0x3fff,
44		.flags = IORESOURCE_MEM,
45	},
46	[1] = {
47		.start = IRQ_S3CUART_RX0,
48		.end   = IRQ_S3CUART_ERR0,
49		.flags = IORESOURCE_IRQ,
50	}
51};
52
53static struct resource s3c2410_uart1_resource[] = {
54	[0] = {
55		.start = S3C2410_PA_UART1,
56		.end   = S3C2410_PA_UART1 + 0x3fff,
57		.flags = IORESOURCE_MEM,
58	},
59	[1] = {
60		.start = IRQ_S3CUART_RX1,
61		.end   = IRQ_S3CUART_ERR1,
62		.flags = IORESOURCE_IRQ,
63	}
64};
65
66static struct resource s3c2410_uart2_resource[] = {
67	[0] = {
68		.start = S3C2410_PA_UART2,
69		.end   = S3C2410_PA_UART2 + 0x3fff,
70		.flags = IORESOURCE_MEM,
71	},
72	[1] = {
73		.start = IRQ_S3CUART_RX2,
74		.end   = IRQ_S3CUART_ERR2,
75		.flags = IORESOURCE_IRQ,
76	}
77};
78
79struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
80	[0] = {
81		.resources	= s3c2410_uart0_resource,
82		.nr_resources	= ARRAY_SIZE(s3c2410_uart0_resource),
83	},
84	[1] = {
85		.resources	= s3c2410_uart1_resource,
86		.nr_resources	= ARRAY_SIZE(s3c2410_uart1_resource),
87	},
88	[2] = {
89		.resources	= s3c2410_uart2_resource,
90		.nr_resources	= ARRAY_SIZE(s3c2410_uart2_resource),
91	},
92};
93
94/* yart devices */
95
96static struct platform_device s3c24xx_uart_device0 = {
97	.id		= 0,
98};
99
100static struct platform_device s3c24xx_uart_device1 = {
101	.id		= 1,
102};
103
104static struct platform_device s3c24xx_uart_device2 = {
105	.id		= 2,
106};
107
108struct platform_device *s3c24xx_uart_src[3] = {
109	&s3c24xx_uart_device0,
110	&s3c24xx_uart_device1,
111	&s3c24xx_uart_device2,
112};
113
114struct platform_device *s3c24xx_uart_devs[3] = {
115};
116
117/* USB Host Controller */
118
119static struct resource s3c_usb_resource[] = {
120	[0] = {
121		.start = S3C24XX_PA_USBHOST,
122		.end   = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
123		.flags = IORESOURCE_MEM,
124	},
125	[1] = {
126		.start = IRQ_USBH,
127		.end   = IRQ_USBH,
128		.flags = IORESOURCE_IRQ,
129	}
130};
131
132static u64 s3c_device_usb_dmamask = 0xffffffffUL;
133
134struct platform_device s3c_device_usb = {
135	.name		  = "s3c2410-ohci",
136	.id		  = -1,
137	.num_resources	  = ARRAY_SIZE(s3c_usb_resource),
138	.resource	  = s3c_usb_resource,
139	.dev              = {
140		.dma_mask = &s3c_device_usb_dmamask,
141		.coherent_dma_mask = 0xffffffffUL
142	}
143};
144
145EXPORT_SYMBOL(s3c_device_usb);
146
147/* LCD Controller */
148
149static struct resource s3c_lcd_resource[] = {
150	[0] = {
151		.start = S3C24XX_PA_LCD,
152		.end   = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
153		.flags = IORESOURCE_MEM,
154	},
155	[1] = {
156		.start = IRQ_LCD,
157		.end   = IRQ_LCD,
158		.flags = IORESOURCE_IRQ,
159	}
160
161};
162
163static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
164
165struct platform_device s3c_device_lcd = {
166	.name		  = "s3c2410-lcd",
167	.id		  = -1,
168	.num_resources	  = ARRAY_SIZE(s3c_lcd_resource),
169	.resource	  = s3c_lcd_resource,
170	.dev              = {
171		.dma_mask		= &s3c_device_lcd_dmamask,
172		.coherent_dma_mask	= 0xffffffffUL
173	}
174};
175
176EXPORT_SYMBOL(s3c_device_lcd);
177
178void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
179{
180	struct s3c2410fb_mach_info *npd;
181
182	npd = kmalloc(sizeof(*npd), GFP_KERNEL);
183	if (npd) {
184		memcpy(npd, pd, sizeof(*npd));
185		s3c_device_lcd.dev.platform_data = npd;
186	} else {
187		printk(KERN_ERR "no memory for LCD platform data\n");
188	}
189}
190
191/* NAND Controller */
192
193static struct resource s3c_nand_resource[] = {
194	[0] = {
195		.start = S3C2410_PA_NAND,
196		.end   = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
197		.flags = IORESOURCE_MEM,
198	}
199};
200
201struct platform_device s3c_device_nand = {
202	.name		  = "s3c2410-nand",
203	.id		  = -1,
204	.num_resources	  = ARRAY_SIZE(s3c_nand_resource),
205	.resource	  = s3c_nand_resource,
206};
207
208EXPORT_SYMBOL(s3c_device_nand);
209
210/* USB Device (Gadget)*/
211
212static struct resource s3c_usbgadget_resource[] = {
213	[0] = {
214		.start = S3C24XX_PA_USBDEV,
215		.end   = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
216		.flags = IORESOURCE_MEM,
217	},
218	[1] = {
219		.start = IRQ_USBD,
220		.end   = IRQ_USBD,
221		.flags = IORESOURCE_IRQ,
222	}
223
224};
225
226struct platform_device s3c_device_usbgadget = {
227	.name		  = "s3c2410-usbgadget",
228	.id		  = -1,
229	.num_resources	  = ARRAY_SIZE(s3c_usbgadget_resource),
230	.resource	  = s3c_usbgadget_resource,
231};
232
233EXPORT_SYMBOL(s3c_device_usbgadget);
234
235void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
236{
237	struct s3c2410_udc_mach_info *npd;
238
239	npd = kmalloc(sizeof(*npd), GFP_KERNEL);
240	if (npd) {
241		memcpy(npd, pd, sizeof(*npd));
242		s3c_device_usbgadget.dev.platform_data = npd;
243	} else {
244		printk(KERN_ERR "no memory for udc platform data\n");
245	}
246}
247
248
249/* Watchdog */
250
251static struct resource s3c_wdt_resource[] = {
252	[0] = {
253		.start = S3C24XX_PA_WATCHDOG,
254		.end   = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
255		.flags = IORESOURCE_MEM,
256	},
257	[1] = {
258		.start = IRQ_WDT,
259		.end   = IRQ_WDT,
260		.flags = IORESOURCE_IRQ,
261	}
262
263};
264
265struct platform_device s3c_device_wdt = {
266	.name		  = "s3c2410-wdt",
267	.id		  = -1,
268	.num_resources	  = ARRAY_SIZE(s3c_wdt_resource),
269	.resource	  = s3c_wdt_resource,
270};
271
272EXPORT_SYMBOL(s3c_device_wdt);
273
274/* I2C */
275
276static struct resource s3c_i2c_resource[] = {
277	[0] = {
278		.start = S3C24XX_PA_IIC,
279		.end   = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
280		.flags = IORESOURCE_MEM,
281	},
282	[1] = {
283		.start = IRQ_IIC,
284		.end   = IRQ_IIC,
285		.flags = IORESOURCE_IRQ,
286	}
287
288};
289
290struct platform_device s3c_device_i2c = {
291	.name		  = "s3c2410-i2c",
292	.id		  = -1,
293	.num_resources	  = ARRAY_SIZE(s3c_i2c_resource),
294	.resource	  = s3c_i2c_resource,
295};
296
297EXPORT_SYMBOL(s3c_device_i2c);
298
299/* IIS */
300
301static struct resource s3c_iis_resource[] = {
302	[0] = {
303		.start = S3C24XX_PA_IIS,
304		.end   = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
305		.flags = IORESOURCE_MEM,
306	}
307};
308
309static u64 s3c_device_iis_dmamask = 0xffffffffUL;
310
311struct platform_device s3c_device_iis = {
312	.name		  = "s3c2410-iis",
313	.id		  = -1,
314	.num_resources	  = ARRAY_SIZE(s3c_iis_resource),
315	.resource	  = s3c_iis_resource,
316	.dev              = {
317		.dma_mask = &s3c_device_iis_dmamask,
318		.coherent_dma_mask = 0xffffffffUL
319	}
320};
321
322EXPORT_SYMBOL(s3c_device_iis);
323
324/* RTC */
325
326static struct resource s3c_rtc_resource[] = {
327	[0] = {
328		.start = S3C24XX_PA_RTC,
329		.end   = S3C24XX_PA_RTC + 0xff,
330		.flags = IORESOURCE_MEM,
331	},
332	[1] = {
333		.start = IRQ_RTC,
334		.end   = IRQ_RTC,
335		.flags = IORESOURCE_IRQ,
336	},
337	[2] = {
338		.start = IRQ_TICK,
339		.end   = IRQ_TICK,
340		.flags = IORESOURCE_IRQ
341	}
342};
343
344struct platform_device s3c_device_rtc = {
345	.name		  = "s3c2410-rtc",
346	.id		  = -1,
347	.num_resources	  = ARRAY_SIZE(s3c_rtc_resource),
348	.resource	  = s3c_rtc_resource,
349};
350
351EXPORT_SYMBOL(s3c_device_rtc);
352
353/* ADC */
354
355static struct resource s3c_adc_resource[] = {
356	[0] = {
357		.start = S3C24XX_PA_ADC,
358		.end   = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
359		.flags = IORESOURCE_MEM,
360	},
361	[1] = {
362		.start = IRQ_TC,
363		.end   = IRQ_TC,
364		.flags = IORESOURCE_IRQ,
365	},
366	[2] = {
367		.start = IRQ_ADC,
368		.end   = IRQ_ADC,
369		.flags = IORESOURCE_IRQ,
370	}
371
372};
373
374struct platform_device s3c_device_adc = {
375	.name		  = "s3c2410-adc",
376	.id		  = -1,
377	.num_resources	  = ARRAY_SIZE(s3c_adc_resource),
378	.resource	  = s3c_adc_resource,
379};
380
381/* SDI */
382
383static struct resource s3c_sdi_resource[] = {
384	[0] = {
385		.start = S3C2410_PA_SDI,
386		.end   = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
387		.flags = IORESOURCE_MEM,
388	},
389	[1] = {
390		.start = IRQ_SDI,
391		.end   = IRQ_SDI,
392		.flags = IORESOURCE_IRQ,
393	}
394
395};
396
397struct platform_device s3c_device_sdi = {
398	.name		  = "s3c2410-sdi",
399	.id		  = -1,
400	.num_resources	  = ARRAY_SIZE(s3c_sdi_resource),
401	.resource	  = s3c_sdi_resource,
402};
403
404EXPORT_SYMBOL(s3c_device_sdi);
405
406/* High-speed MMC/SD */
407
408static struct resource s3c_hsmmc_resource[] = {
409	[0] = {
410		.start = S3C2443_PA_HSMMC,
411		.end   = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
412		.flags = IORESOURCE_MEM,
413	},
414	[1] = {
415		.start = IRQ_S3C2443_HSMMC,
416		.end   = IRQ_S3C2443_HSMMC,
417		.flags = IORESOURCE_IRQ,
418	}
419};
420
421static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
422
423struct platform_device s3c_device_hsmmc = {
424	.name		  = "s3c-sdhci",
425	.id		  = -1,
426	.num_resources	  = ARRAY_SIZE(s3c_hsmmc_resource),
427	.resource	  = s3c_hsmmc_resource,
428	.dev              = {
429		.dma_mask = &s3c_device_hsmmc_dmamask,
430		.coherent_dma_mask = 0xffffffffUL
431	}
432};
433
434
435
436/* SPI (0) */
437
438static struct resource s3c_spi0_resource[] = {
439	[0] = {
440		.start = S3C24XX_PA_SPI,
441		.end   = S3C24XX_PA_SPI + 0x1f,
442		.flags = IORESOURCE_MEM,
443	},
444	[1] = {
445		.start = IRQ_SPI0,
446		.end   = IRQ_SPI0,
447		.flags = IORESOURCE_IRQ,
448	}
449
450};
451
452static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
453
454struct platform_device s3c_device_spi0 = {
455	.name		  = "s3c2410-spi",
456	.id		  = 0,
457	.num_resources	  = ARRAY_SIZE(s3c_spi0_resource),
458	.resource	  = s3c_spi0_resource,
459        .dev              = {
460                .dma_mask = &s3c_device_spi0_dmamask,
461                .coherent_dma_mask = 0xffffffffUL
462        }
463};
464
465EXPORT_SYMBOL(s3c_device_spi0);
466
467/* SPI (1) */
468
469static struct resource s3c_spi1_resource[] = {
470	[0] = {
471		.start = S3C24XX_PA_SPI + S3C2410_SPI1,
472		.end   = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
473		.flags = IORESOURCE_MEM,
474	},
475	[1] = {
476		.start = IRQ_SPI1,
477		.end   = IRQ_SPI1,
478		.flags = IORESOURCE_IRQ,
479	}
480
481};
482
483static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
484
485struct platform_device s3c_device_spi1 = {
486	.name		  = "s3c2410-spi",
487	.id		  = 1,
488	.num_resources	  = ARRAY_SIZE(s3c_spi1_resource),
489	.resource	  = s3c_spi1_resource,
490        .dev              = {
491                .dma_mask = &s3c_device_spi1_dmamask,
492                .coherent_dma_mask = 0xffffffffUL
493        }
494};
495
496EXPORT_SYMBOL(s3c_device_spi1);
497
498/* pwm timer blocks */
499
500static struct resource s3c_timer0_resource[] = {
501	[0] = {
502		.start = S3C24XX_PA_TIMER + 0x0C,
503		.end   = S3C24XX_PA_TIMER + 0x0C + 0xB,
504		.flags = IORESOURCE_MEM,
505	},
506	[1] = {
507		.start = IRQ_TIMER0,
508		.end   = IRQ_TIMER0,
509		.flags = IORESOURCE_IRQ,
510	}
511
512};
513
514struct platform_device s3c_device_timer0 = {
515	.name		  = "s3c2410-timer",
516	.id		  = 0,
517	.num_resources	  = ARRAY_SIZE(s3c_timer0_resource),
518	.resource	  = s3c_timer0_resource,
519};
520
521EXPORT_SYMBOL(s3c_device_timer0);
522
523/* timer 1 */
524
525static struct resource s3c_timer1_resource[] = {
526	[0] = {
527		.start = S3C24XX_PA_TIMER + 0x18,
528		.end   = S3C24XX_PA_TIMER + 0x23,
529		.flags = IORESOURCE_MEM,
530	},
531	[1] = {
532		.start = IRQ_TIMER1,
533		.end   = IRQ_TIMER1,
534		.flags = IORESOURCE_IRQ,
535	}
536
537};
538
539struct platform_device s3c_device_timer1 = {
540	.name		  = "s3c2410-timer",
541	.id		  = 1,
542	.num_resources	  = ARRAY_SIZE(s3c_timer1_resource),
543	.resource	  = s3c_timer1_resource,
544};
545
546EXPORT_SYMBOL(s3c_device_timer1);
547
548/* timer 2 */
549
550static struct resource s3c_timer2_resource[] = {
551	[0] = {
552		.start = S3C24XX_PA_TIMER + 0x24,
553		.end   = S3C24XX_PA_TIMER + 0x2F,
554		.flags = IORESOURCE_MEM,
555	},
556	[1] = {
557		.start = IRQ_TIMER2,
558		.end   = IRQ_TIMER2,
559		.flags = IORESOURCE_IRQ,
560	}
561
562};
563
564struct platform_device s3c_device_timer2 = {
565	.name		  = "s3c2410-timer",
566	.id		  = 2,
567	.num_resources	  = ARRAY_SIZE(s3c_timer2_resource),
568	.resource	  = s3c_timer2_resource,
569};
570
571EXPORT_SYMBOL(s3c_device_timer2);
572
573/* timer 3 */
574
575static struct resource s3c_timer3_resource[] = {
576	[0] = {
577		.start = S3C24XX_PA_TIMER + 0x30,
578		.end   = S3C24XX_PA_TIMER + 0x3B,
579		.flags = IORESOURCE_MEM,
580	},
581	[1] = {
582		.start = IRQ_TIMER3,
583		.end   = IRQ_TIMER3,
584		.flags = IORESOURCE_IRQ,
585	}
586
587};
588
589struct platform_device s3c_device_timer3 = {
590	.name		  = "s3c2410-timer",
591	.id		  = 3,
592	.num_resources	  = ARRAY_SIZE(s3c_timer3_resource),
593	.resource	  = s3c_timer3_resource,
594};
595
596EXPORT_SYMBOL(s3c_device_timer3);
597
598#ifdef CONFIG_CPU_S3C2440
599
600/* Camif Controller */
601
602static struct resource s3c_camif_resource[] = {
603	[0] = {
604		.start = S3C2440_PA_CAMIF,
605		.end   = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
606		.flags = IORESOURCE_MEM,
607	},
608	[1] = {
609		.start = IRQ_CAM,
610		.end   = IRQ_CAM,
611		.flags = IORESOURCE_IRQ,
612	}
613
614};
615
616static u64 s3c_device_camif_dmamask = 0xffffffffUL;
617
618struct platform_device s3c_device_camif = {
619	.name		  = "s3c2440-camif",
620	.id		  = -1,
621	.num_resources	  = ARRAY_SIZE(s3c_camif_resource),
622	.resource	  = s3c_camif_resource,
623	.dev              = {
624		.dma_mask = &s3c_device_camif_dmamask,
625		.coherent_dma_mask = 0xffffffffUL
626	}
627};
628
629EXPORT_SYMBOL(s3c_device_camif);
630
631#endif // CONFIG_CPU_S32440
632