1/* 2 * linux/arch/arm/plat-omap/mux.c 3 * 4 * Utility to set the Omap MUX and PULL_DWN registers from a table in mux.h 5 * 6 * Copyright (C) 2003 - 2005 Nokia Corporation 7 * 8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25#include <linux/module.h> 26#include <linux/init.h> 27#include <linux/kernel.h> 28#include <asm/system.h> 29#include <asm/io.h> 30#include <linux/spinlock.h> 31#include <asm/arch/mux.h> 32 33#ifdef CONFIG_OMAP_MUX 34 35#define OMAP24XX_L4_BASE 0x48000000 36#define OMAP24XX_PULL_ENA (1 << 3) 37#define OMAP24XX_PULL_UP (1 << 4) 38 39static struct pin_config * pin_table; 40static unsigned long pin_table_sz; 41 42extern struct pin_config * omap730_pins; 43extern struct pin_config * omap1xxx_pins; 44extern struct pin_config * omap24xx_pins; 45 46int __init omap_mux_register(struct pin_config * pins, unsigned long size) 47{ 48 pin_table = pins; 49 pin_table_sz = size; 50 51 return 0; 52} 53 54/* 55 * Sets the Omap MUX and PULL_DWN registers based on the table 56 */ 57int __init_or_module omap_cfg_reg(const unsigned long index) 58{ 59 static DEFINE_SPINLOCK(mux_spin_lock); 60 61 unsigned long flags; 62 struct pin_config *cfg; 63 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, 64 pull_orig = 0, pull = 0; 65 unsigned int mask, warn = 0; 66 67 if (!pin_table) 68 BUG(); 69 70 if (index >= pin_table_sz) { 71 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", 72 index, pin_table_sz); 73 dump_stack(); 74 return -ENODEV; 75 } 76 77 cfg = (struct pin_config *)&pin_table[index]; 78 if (cpu_is_omap24xx()) { 79 u8 reg = 0; 80 81 reg |= cfg->mask & 0x7; 82 if (cfg->pull_val) 83 reg |= OMAP24XX_PULL_ENA; 84 if(cfg->pu_pd_val) 85 reg |= OMAP24XX_PULL_UP; 86#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 87 { 88 u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); 89 u8 debug = 0; 90 91#ifdef CONFIG_OMAP_MUX_DEBUG 92 debug = cfg->debug; 93#endif 94 warn = (orig != reg); 95 if (debug || warn) 96 printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", 97 cfg->name, 98 OMAP24XX_L4_BASE + cfg->mux_reg, 99 orig, reg); 100 } 101#endif 102 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); 103 104 return 0; 105 } 106 107 /* Check the mux register in question */ 108 if (cfg->mux_reg) { 109 unsigned tmp1, tmp2; 110 111 spin_lock_irqsave(&mux_spin_lock, flags); 112 reg_orig = omap_readl(cfg->mux_reg); 113 114 /* The mux registers always seem to be 3 bits long */ 115 mask = (0x7 << cfg->mask_offset); 116 tmp1 = reg_orig & mask; 117 reg = reg_orig & ~mask; 118 119 tmp2 = (cfg->mask << cfg->mask_offset); 120 reg |= tmp2; 121 122 if (tmp1 != tmp2) 123 warn = 1; 124 125 omap_writel(reg, cfg->mux_reg); 126 spin_unlock_irqrestore(&mux_spin_lock, flags); 127 } 128 129 /* Check for pull up or pull down selection on 1610 */ 130 if (!cpu_is_omap15xx()) { 131 if (cfg->pu_pd_reg && cfg->pull_val) { 132 spin_lock_irqsave(&mux_spin_lock, flags); 133 pu_pd_orig = omap_readl(cfg->pu_pd_reg); 134 mask = 1 << cfg->pull_bit; 135 136 if (cfg->pu_pd_val) { 137 if (!(pu_pd_orig & mask)) 138 warn = 1; 139 /* Use pull up */ 140 pu_pd = pu_pd_orig | mask; 141 } else { 142 if (pu_pd_orig & mask) 143 warn = 1; 144 /* Use pull down */ 145 pu_pd = pu_pd_orig & ~mask; 146 } 147 omap_writel(pu_pd, cfg->pu_pd_reg); 148 spin_unlock_irqrestore(&mux_spin_lock, flags); 149 } 150 } 151 152 /* Check for an associated pull down register */ 153 if (cfg->pull_reg) { 154 spin_lock_irqsave(&mux_spin_lock, flags); 155 pull_orig = omap_readl(cfg->pull_reg); 156 mask = 1 << cfg->pull_bit; 157 158 if (cfg->pull_val) { 159 if (pull_orig & mask) 160 warn = 1; 161 /* Low bit = pull enabled */ 162 pull = pull_orig & ~mask; 163 } else { 164 if (!(pull_orig & mask)) 165 warn = 1; 166 /* High bit = pull disabled */ 167 pull = pull_orig | mask; 168 } 169 170 omap_writel(pull, cfg->pull_reg); 171 spin_unlock_irqrestore(&mux_spin_lock, flags); 172 } 173 174 if (warn) { 175#ifdef CONFIG_OMAP_MUX_WARNINGS 176 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); 177#endif 178 } 179 180#ifdef CONFIG_OMAP_MUX_DEBUG 181 if (cfg->debug || warn) { 182 printk("MUX: Setting register %s\n", cfg->name); 183 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", 184 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); 185 186 if (!cpu_is_omap15xx()) { 187 if (cfg->pu_pd_reg && cfg->pull_val) { 188 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", 189 cfg->pu_pd_name, cfg->pu_pd_reg, 190 pu_pd_orig, pu_pd); 191 } 192 } 193 194 if (cfg->pull_reg) 195 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", 196 cfg->pull_name, cfg->pull_reg, pull_orig, pull); 197 } 198#endif 199 200#ifdef CONFIG_OMAP_MUX_ERRORS 201 return warn ? -ETXTBSY : 0; 202#else 203 return 0; 204#endif 205} 206EXPORT_SYMBOL(omap_cfg_reg); 207#else 208#define omap_mux_init() do {} while(0) 209#define omap_cfg_reg(x) do {} while(0) 210#endif /* CONFIG_OMAP_MUX */ 211