1/* 2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S 3 * 4 * Copyright (C) 1999-2001 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm926. 25 * 26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/elf.h> 32#include <asm/pgtable-hwdef.h> 33#include <asm/pgtable.h> 34#include <asm/page.h> 35#include <asm/ptrace.h> 36#include "proc-macros.S" 37 38/* 39 * This is the maximum size of an area which will be invalidated 40 * using the single invalidate entry instructions. Anything larger 41 * than this, and we go for the whole cache. 42 * 43 * This value should be chosen such that we choose the cheapest 44 * alternative. 45 */ 46#define CACHE_DLIMIT 16384 47 48/* 49 * the cache line size of the I and D cache 50 */ 51#define CACHE_DLINESIZE 32 52 53 .text 54/* 55 * cpu_arm926_proc_init() 56 */ 57ENTRY(cpu_arm926_proc_init) 58 mov pc, lr 59 60/* 61 * cpu_arm926_proc_fin() 62 */ 63ENTRY(cpu_arm926_proc_fin) 64 stmfd sp!, {lr} 65 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 66 msr cpsr_c, ip 67 bl arm926_flush_kern_cache_all 68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 69 bic r0, r0, #0x1000 @ ...i............ 70 bic r0, r0, #0x000e @ ............wca. 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 72 ldmfd sp!, {pc} 73 74/* 75 * cpu_arm926_reset(loc) 76 * 77 * Perform a soft reset of the system. Put the CPU into the 78 * same state as it would be if it had been reset, and branch 79 * to what would be the reset vector. 80 * 81 * loc: location to jump to for soft reset 82 */ 83 .align 5 84ENTRY(cpu_arm926_reset) 85 mov ip, #0 86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 87 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88#ifdef CONFIG_MMU 89 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90#endif 91 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 92 bic ip, ip, #0x000f @ ............wcam 93 bic ip, ip, #0x1100 @ ...i...s........ 94 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mov pc, r0 96 97/* 98 * cpu_arm926_do_idle() 99 * 100 * Called with IRQs disabled 101 */ 102 .align 10 103ENTRY(cpu_arm926_do_idle) 104 mov r0, #0 105 mrc p15, 0, r1, c1, c0, 0 @ Read control register 106 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 107 bic r2, r1, #1 << 12 108 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 111 mov pc, lr 112 113/* 114 * flush_user_cache_all() 115 * 116 * Clean and invalidate all cache entries in a particular 117 * address space. 118 */ 119ENTRY(arm926_flush_user_cache_all) 120 /* FALLTHROUGH */ 121 122/* 123 * flush_kern_cache_all() 124 * 125 * Clean and invalidate the entire cache. 126 */ 127ENTRY(arm926_flush_kern_cache_all) 128 mov r2, #VM_EXEC 129 mov ip, #0 130__flush_whole_cache: 131#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 133#else 1341: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 135 bne 1b 136#endif 137 tst r2, #VM_EXEC 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 140 mov pc, lr 141 142/* 143 * flush_user_cache_range(start, end, flags) 144 * 145 * Clean and invalidate a range of cache entries in the 146 * specified address range. 147 * 148 * - start - start address (inclusive) 149 * - end - end address (exclusive) 150 * - flags - vm_flags describing address space 151 */ 152ENTRY(arm926_flush_user_cache_range) 153 mov ip, #0 154 sub r3, r1, r0 @ calculate total size 155 cmp r3, #CACHE_DLIMIT 156 bgt __flush_whole_cache 1571: tst r2, #VM_EXEC 158#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 161 add r0, r0, #CACHE_DLINESIZE 162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 164 add r0, r0, #CACHE_DLINESIZE 165#else 166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 168 add r0, r0, #CACHE_DLINESIZE 169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 171 add r0, r0, #CACHE_DLINESIZE 172#endif 173 cmp r0, r1 174 blo 1b 175 tst r2, #VM_EXEC 176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 177 mov pc, lr 178 179/* 180 * coherent_kern_range(start, end) 181 * 182 * Ensure coherency between the Icache and the Dcache in the 183 * region described by start, end. If you have non-snooping 184 * Harvard caches, you need to implement this function. 185 * 186 * - start - virtual start address 187 * - end - virtual end address 188 */ 189ENTRY(arm926_coherent_kern_range) 190 /* FALLTHROUGH */ 191 192/* 193 * coherent_user_range(start, end) 194 * 195 * Ensure coherency between the Icache and the Dcache in the 196 * region described by start, end. If you have non-snooping 197 * Harvard caches, you need to implement this function. 198 * 199 * - start - virtual start address 200 * - end - virtual end address 201 */ 202ENTRY(arm926_coherent_user_range) 203 bic r0, r0, #CACHE_DLINESIZE - 1 2041: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 206 add r0, r0, #CACHE_DLINESIZE 207 cmp r0, r1 208 blo 1b 209 mcr p15, 0, r0, c7, c10, 4 @ drain WB 210 mov pc, lr 211 212/* 213 * flush_kern_dcache_page(void *page) 214 * 215 * Ensure no D cache aliasing occurs, either with itself or 216 * the I cache 217 * 218 * - addr - page aligned address 219 */ 220ENTRY(arm926_flush_kern_dcache_page) 221 add r1, r0, #PAGE_SZ 2221: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 223 add r0, r0, #CACHE_DLINESIZE 224 cmp r0, r1 225 blo 1b 226 mov r0, #0 227 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 228 mcr p15, 0, r0, c7, c10, 4 @ drain WB 229 mov pc, lr 230 231/* 232 * dma_inv_range(start, end) 233 * 234 * Invalidate (discard) the specified virtual address range. 235 * May not write back any entries. If 'start' or 'end' 236 * are not cache line aligned, those lines must be written 237 * back. 238 * 239 * - start - virtual start address 240 * - end - virtual end address 241 * 242 * (same as v4wb) 243 */ 244ENTRY(arm926_dma_inv_range) 245#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 246 tst r0, #CACHE_DLINESIZE - 1 247 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 248 tst r1, #CACHE_DLINESIZE - 1 249 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 250#endif 251 bic r0, r0, #CACHE_DLINESIZE - 1 2521: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 253 add r0, r0, #CACHE_DLINESIZE 254 cmp r0, r1 255 blo 1b 256 mcr p15, 0, r0, c7, c10, 4 @ drain WB 257 mov pc, lr 258 259/* 260 * dma_clean_range(start, end) 261 * 262 * Clean the specified virtual address range. 263 * 264 * - start - virtual start address 265 * - end - virtual end address 266 * 267 * (same as v4wb) 268 */ 269ENTRY(arm926_dma_clean_range) 270#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 271 bic r0, r0, #CACHE_DLINESIZE - 1 2721: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 273 add r0, r0, #CACHE_DLINESIZE 274 cmp r0, r1 275 blo 1b 276#endif 277 mcr p15, 0, r0, c7, c10, 4 @ drain WB 278 mov pc, lr 279 280/* 281 * dma_flush_range(start, end) 282 * 283 * Clean and invalidate the specified virtual address range. 284 * 285 * - start - virtual start address 286 * - end - virtual end address 287 */ 288ENTRY(arm926_dma_flush_range) 289 bic r0, r0, #CACHE_DLINESIZE - 1 2901: 291#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 292 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 293#else 294 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 295#endif 296 add r0, r0, #CACHE_DLINESIZE 297 cmp r0, r1 298 blo 1b 299 mcr p15, 0, r0, c7, c10, 4 @ drain WB 300 mov pc, lr 301 302ENTRY(arm926_cache_fns) 303 .long arm926_flush_kern_cache_all 304 .long arm926_flush_user_cache_all 305 .long arm926_flush_user_cache_range 306 .long arm926_coherent_kern_range 307 .long arm926_coherent_user_range 308 .long arm926_flush_kern_dcache_page 309 .long arm926_dma_inv_range 310 .long arm926_dma_clean_range 311 .long arm926_dma_flush_range 312 313ENTRY(cpu_arm926_dcache_clean_area) 314#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 3151: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 316 add r0, r0, #CACHE_DLINESIZE 317 subs r1, r1, #CACHE_DLINESIZE 318 bhi 1b 319#endif 320 mcr p15, 0, r0, c7, c10, 4 @ drain WB 321 mov pc, lr 322 323/* =============================== PageTable ============================== */ 324 325/* 326 * cpu_arm926_switch_mm(pgd) 327 * 328 * Set the translation base pointer to be as described by pgd. 329 * 330 * pgd: new page tables 331 */ 332 .align 5 333ENTRY(cpu_arm926_switch_mm) 334#ifdef CONFIG_MMU 335 mov ip, #0 336#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 337 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 338#else 339@ && 'Clean & Invalidate whole DCache' 3401: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 341 bne 1b 342#endif 343 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 344 mcr p15, 0, ip, c7, c10, 4 @ drain WB 345 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 346 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 347#endif 348 mov pc, lr 349 350/* 351 * cpu_arm926_set_pte_ext(ptep, pte, ext) 352 * 353 * Set a PTE and flush it out 354 */ 355 .align 5 356ENTRY(cpu_arm926_set_pte_ext) 357#ifdef CONFIG_MMU 358 str r1, [r0], #-2048 @ linux version 359 360 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 361 362 bic r2, r1, #PTE_SMALL_AP_MASK 363 bic r2, r2, #PTE_TYPE_MASK 364 orr r2, r2, #PTE_TYPE_SMALL 365 366 tst r1, #L_PTE_USER @ User? 367 orrne r2, r2, #PTE_SMALL_AP_URO_SRW 368 369 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 370 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW 371 372 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 373 movne r2, #0 374 375#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 376 eor r3, r2, #0x0a @ C & small page? 377 tst r3, #0x0b 378 biceq r2, r2, #4 379#endif 380 str r2, [r0] @ hardware version 381 mov r0, r0 382#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 383 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 384#endif 385 mcr p15, 0, r0, c7, c10, 4 @ drain WB 386#endif 387 mov pc, lr 388 389 __INIT 390 391 .type __arm926_setup, #function 392__arm926_setup: 393 mov r0, #0 394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 395 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 396#ifdef CONFIG_MMU 397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 398#endif 399 400 401#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 402 mov r0, #4 @ disable write-back on caches explicitly 403 mcr p15, 7, r0, c15, c0, 0 404#endif 405 406 adr r5, arm926_crval 407 ldmia r5, {r5, r6} 408 mrc p15, 0, r0, c1, c0 @ get control register v4 409 bic r0, r0, r5 410 orr r0, r0, r6 411#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 412 orr r0, r0, #0x4000 @ .1.. .... .... .... 413#endif 414 mov pc, lr 415 .size __arm926_setup, . - __arm926_setup 416 417 /* 418 * R 419 * .RVI ZFRS BLDP WCAM 420 * .011 0001 ..11 0101 421 * 422 */ 423 .type arm926_crval, #object 424arm926_crval: 425 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134 426 427 __INITDATA 428 429/* 430 * Purpose : Function pointers used to access above functions - all calls 431 * come through these 432 */ 433 .type arm926_processor_functions, #object 434arm926_processor_functions: 435 .word v5tj_early_abort 436 .word cpu_arm926_proc_init 437 .word cpu_arm926_proc_fin 438 .word cpu_arm926_reset 439 .word cpu_arm926_do_idle 440 .word cpu_arm926_dcache_clean_area 441 .word cpu_arm926_switch_mm 442 .word cpu_arm926_set_pte_ext 443 .size arm926_processor_functions, . - arm926_processor_functions 444 445 .section ".rodata" 446 447 .type cpu_arch_name, #object 448cpu_arch_name: 449 .asciz "armv5tej" 450 .size cpu_arch_name, . - cpu_arch_name 451 452 .type cpu_elf_name, #object 453cpu_elf_name: 454 .asciz "v5" 455 .size cpu_elf_name, . - cpu_elf_name 456 457 .type cpu_arm926_name, #object 458cpu_arm926_name: 459 .asciz "ARM926EJ-S" 460 .size cpu_arm926_name, . - cpu_arm926_name 461 462 .align 463 464 .section ".proc.info.init", #alloc, #execinstr 465 466 .type __arm926_proc_info,#object 467__arm926_proc_info: 468 .long 0x41069260 @ ARM926EJ-S (v5TEJ) 469 .long 0xff0ffff0 470 .long PMD_TYPE_SECT | \ 471 PMD_SECT_BUFFERABLE | \ 472 PMD_SECT_CACHEABLE | \ 473 PMD_BIT4 | \ 474 PMD_SECT_AP_WRITE | \ 475 PMD_SECT_AP_READ 476 .long PMD_TYPE_SECT | \ 477 PMD_BIT4 | \ 478 PMD_SECT_AP_WRITE | \ 479 PMD_SECT_AP_READ 480 b __arm926_setup 481 .long cpu_arch_name 482 .long cpu_elf_name 483 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA 484 .long cpu_arm926_name 485 .long arm926_processor_functions 486 .long v4wbi_tlb_fns 487 .long v4wb_user_fns 488 .long arm926_cache_fns 489 .size __arm926_proc_info, . - __arm926_proc_info 490