1/* 2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm1020e. 25 * 26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/init.h> 30#include <asm/assembler.h> 31#include <asm/asm-offsets.h> 32#include <asm/elf.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/ptrace.h> 36 37#include "proc-macros.S" 38 39/* 40 * This is the maximum size of an area which will be invalidated 41 * using the single invalidate entry instructions. Anything larger 42 * than this, and we go for the whole cache. 43 * 44 * This value should be chosen such that we choose the cheapest 45 * alternative. 46 */ 47#define MAX_AREA_SIZE 32768 48 49/* 50 * The size of one data cache line. 51 */ 52#define CACHE_DLINESIZE 32 53 54/* 55 * The number of data cache segments. 56 */ 57#define CACHE_DSEGMENTS 16 58 59/* 60 * The number of lines in a cache segment. 61 */ 62#define CACHE_DENTRIES 64 63 64/* 65 * This is the size at which it becomes more efficient to 66 * clean the whole cache, rather than using the individual 67 * cache line maintainence instructions. 68 */ 69#define CACHE_DLIMIT 32768 70 71 .text 72/* 73 * cpu_arm1020e_proc_init() 74 */ 75ENTRY(cpu_arm1020e_proc_init) 76 mov pc, lr 77 78/* 79 * cpu_arm1020e_proc_fin() 80 */ 81ENTRY(cpu_arm1020e_proc_fin) 82 stmfd sp!, {lr} 83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 84 msr cpsr_c, ip 85 bl arm1020e_flush_kern_cache_all 86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 87 bic r0, r0, #0x1000 @ ...i............ 88 bic r0, r0, #0x000e @ ............wca. 89 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 ldmfd sp!, {pc} 91 92/* 93 * cpu_arm1020e_reset(loc) 94 * 95 * Perform a soft reset of the system. Put the CPU into the 96 * same state as it would be if it had been reset, and branch 97 * to what would be the reset vector. 98 * 99 * loc: location to jump to for soft reset 100 */ 101 .align 5 102ENTRY(cpu_arm1020e_reset) 103 mov ip, #0 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 106#ifdef CONFIG_MMU 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108#endif 109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 110 bic ip, ip, #0x000f @ ............wcam 111 bic ip, ip, #0x1100 @ ...i...s........ 112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 113 mov pc, r0 114 115/* 116 * cpu_arm1020e_do_idle() 117 */ 118 .align 5 119ENTRY(cpu_arm1020e_do_idle) 120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 121 mov pc, lr 122 123/* ================================= CACHE ================================ */ 124 125 .align 5 126/* 127 * flush_user_cache_all() 128 * 129 * Invalidate all cache entries in a particular address 130 * space. 131 */ 132ENTRY(arm1020e_flush_user_cache_all) 133 /* FALLTHROUGH */ 134/* 135 * flush_kern_cache_all() 136 * 137 * Clean and invalidate the entire cache. 138 */ 139ENTRY(arm1020e_flush_kern_cache_all) 140 mov r2, #VM_EXEC 141 mov ip, #0 142__flush_whole_cache: 143#ifndef CONFIG_CPU_DCACHE_DISABLE 144 mcr p15, 0, ip, c7, c10, 4 @ drain WB 145 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1461: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1472: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 148 subs r3, r3, #1 << 26 149 bcs 2b @ entries 63 to 0 150 subs r1, r1, #1 << 5 151 bcs 1b @ segments 15 to 0 152#endif 153 tst r2, #VM_EXEC 154#ifndef CONFIG_CPU_ICACHE_DISABLE 155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 156#endif 157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 158 mov pc, lr 159 160/* 161 * flush_user_cache_range(start, end, flags) 162 * 163 * Invalidate a range of cache entries in the specified 164 * address space. 165 * 166 * - start - start address (inclusive) 167 * - end - end address (exclusive) 168 * - flags - vm_flags for this space 169 */ 170ENTRY(arm1020e_flush_user_cache_range) 171 mov ip, #0 172 sub r3, r1, r0 @ calculate total size 173 cmp r3, #CACHE_DLIMIT 174 bhs __flush_whole_cache 175 176#ifndef CONFIG_CPU_DCACHE_DISABLE 1771: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 178 add r0, r0, #CACHE_DLINESIZE 179 cmp r0, r1 180 blo 1b 181#endif 182 tst r2, #VM_EXEC 183#ifndef CONFIG_CPU_ICACHE_DISABLE 184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 185#endif 186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 187 mov pc, lr 188 189/* 190 * coherent_kern_range(start, end) 191 * 192 * Ensure coherency between the Icache and the Dcache in the 193 * region described by start. If you have non-snooping 194 * Harvard caches, you need to implement this function. 195 * 196 * - start - virtual start address 197 * - end - virtual end address 198 */ 199ENTRY(arm1020e_coherent_kern_range) 200 /* FALLTHROUGH */ 201/* 202 * coherent_user_range(start, end) 203 * 204 * Ensure coherency between the Icache and the Dcache in the 205 * region described by start. If you have non-snooping 206 * Harvard caches, you need to implement this function. 207 * 208 * - start - virtual start address 209 * - end - virtual end address 210 */ 211ENTRY(arm1020e_coherent_user_range) 212 mov ip, #0 213 bic r0, r0, #CACHE_DLINESIZE - 1 2141: 215#ifndef CONFIG_CPU_DCACHE_DISABLE 216 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 217#endif 218#ifndef CONFIG_CPU_ICACHE_DISABLE 219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 220#endif 221 add r0, r0, #CACHE_DLINESIZE 222 cmp r0, r1 223 blo 1b 224 mcr p15, 0, ip, c7, c10, 4 @ drain WB 225 mov pc, lr 226 227/* 228 * flush_kern_dcache_page(void *page) 229 * 230 * Ensure no D cache aliasing occurs, either with itself or 231 * the I cache 232 * 233 * - page - page aligned address 234 */ 235ENTRY(arm1020e_flush_kern_dcache_page) 236 mov ip, #0 237#ifndef CONFIG_CPU_DCACHE_DISABLE 238 add r1, r0, #PAGE_SZ 2391: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 240 add r0, r0, #CACHE_DLINESIZE 241 cmp r0, r1 242 blo 1b 243#endif 244 mcr p15, 0, ip, c7, c10, 4 @ drain WB 245 mov pc, lr 246 247/* 248 * dma_inv_range(start, end) 249 * 250 * Invalidate (discard) the specified virtual address range. 251 * May not write back any entries. If 'start' or 'end' 252 * are not cache line aligned, those lines must be written 253 * back. 254 * 255 * - start - virtual start address 256 * - end - virtual end address 257 * 258 * (same as v4wb) 259 */ 260ENTRY(arm1020e_dma_inv_range) 261 mov ip, #0 262#ifndef CONFIG_CPU_DCACHE_DISABLE 263 tst r0, #CACHE_DLINESIZE - 1 264 bic r0, r0, #CACHE_DLINESIZE - 1 265 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 266 tst r1, #CACHE_DLINESIZE - 1 267 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2681: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 269 add r0, r0, #CACHE_DLINESIZE 270 cmp r0, r1 271 blo 1b 272#endif 273 mcr p15, 0, ip, c7, c10, 4 @ drain WB 274 mov pc, lr 275 276/* 277 * dma_clean_range(start, end) 278 * 279 * Clean the specified virtual address range. 280 * 281 * - start - virtual start address 282 * - end - virtual end address 283 * 284 * (same as v4wb) 285 */ 286ENTRY(arm1020e_dma_clean_range) 287 mov ip, #0 288#ifndef CONFIG_CPU_DCACHE_DISABLE 289 bic r0, r0, #CACHE_DLINESIZE - 1 2901: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 291 add r0, r0, #CACHE_DLINESIZE 292 cmp r0, r1 293 blo 1b 294#endif 295 mcr p15, 0, ip, c7, c10, 4 @ drain WB 296 mov pc, lr 297 298/* 299 * dma_flush_range(start, end) 300 * 301 * Clean and invalidate the specified virtual address range. 302 * 303 * - start - virtual start address 304 * - end - virtual end address 305 */ 306ENTRY(arm1020e_dma_flush_range) 307 mov ip, #0 308#ifndef CONFIG_CPU_DCACHE_DISABLE 309 bic r0, r0, #CACHE_DLINESIZE - 1 3101: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 311 add r0, r0, #CACHE_DLINESIZE 312 cmp r0, r1 313 blo 1b 314#endif 315 mcr p15, 0, ip, c7, c10, 4 @ drain WB 316 mov pc, lr 317 318ENTRY(arm1020e_cache_fns) 319 .long arm1020e_flush_kern_cache_all 320 .long arm1020e_flush_user_cache_all 321 .long arm1020e_flush_user_cache_range 322 .long arm1020e_coherent_kern_range 323 .long arm1020e_coherent_user_range 324 .long arm1020e_flush_kern_dcache_page 325 .long arm1020e_dma_inv_range 326 .long arm1020e_dma_clean_range 327 .long arm1020e_dma_flush_range 328 329 .align 5 330ENTRY(cpu_arm1020e_dcache_clean_area) 331#ifndef CONFIG_CPU_DCACHE_DISABLE 332 mov ip, #0 3331: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 334 add r0, r0, #CACHE_DLINESIZE 335 subs r1, r1, #CACHE_DLINESIZE 336 bhi 1b 337#endif 338 mov pc, lr 339 340/* =============================== PageTable ============================== */ 341 342/* 343 * cpu_arm1020e_switch_mm(pgd) 344 * 345 * Set the translation base pointer to be as described by pgd. 346 * 347 * pgd: new page tables 348 */ 349 .align 5 350ENTRY(cpu_arm1020e_switch_mm) 351#ifdef CONFIG_MMU 352#ifndef CONFIG_CPU_DCACHE_DISABLE 353 mcr p15, 0, r3, c7, c10, 4 354 mov r1, #0xF @ 16 segments 3551: mov r3, #0x3F @ 64 entries 3562: mov ip, r3, LSL #26 @ shift up entry 357 orr ip, ip, r1, LSL #5 @ shift in/up index 358 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 359 mov ip, #0 360 subs r3, r3, #1 361 cmp r3, #0 362 bge 2b @ entries 3F to 0 363 subs r1, r1, #1 364 cmp r1, #0 365 bge 1b @ segments 15 to 0 366 367#endif 368 mov r1, #0 369#ifndef CONFIG_CPU_ICACHE_DISABLE 370 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 371#endif 372 mcr p15, 0, r1, c7, c10, 4 @ drain WB 373 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 374 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 375#endif 376 mov pc, lr 377 378/* 379 * cpu_arm1020e_set_pte(ptep, pte) 380 * 381 * Set a PTE and flush it out 382 */ 383 .align 5 384ENTRY(cpu_arm1020e_set_pte_ext) 385#ifdef CONFIG_MMU 386 str r1, [r0], #-2048 @ linux version 387 388 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 389 390 bic r2, r1, #PTE_SMALL_AP_MASK 391 bic r2, r2, #PTE_TYPE_MASK 392 orr r2, r2, #PTE_TYPE_SMALL 393 394 tst r1, #L_PTE_USER @ User? 395 orrne r2, r2, #PTE_SMALL_AP_URO_SRW 396 397 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 398 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW 399 400 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 401 movne r2, #0 402 403#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 404 eor r3, r1, #0x0a @ C & small page? 405 tst r3, #0x0b 406 biceq r2, r2, #4 407#endif 408 str r2, [r0] @ hardware version 409 mov r0, r0 410#ifndef CONFIG_CPU_DCACHE_DISABLE 411 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 412#endif 413#endif /* CONFIG_MMU */ 414 mov pc, lr 415 416 __INIT 417 418 .type __arm1020e_setup, #function 419__arm1020e_setup: 420 mov r0, #0 421 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 422 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 423#ifdef CONFIG_MMU 424 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 425#endif 426 adr r5, arm1020e_crval 427 ldmia r5, {r5, r6} 428 mrc p15, 0, r0, c1, c0 @ get control register v4 429 bic r0, r0, r5 430 orr r0, r0, r6 431#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 432 orr r0, r0, #0x4000 @ .R.. .... .... .... 433#endif 434 mov pc, lr 435 .size __arm1020e_setup, . - __arm1020e_setup 436 437 /* 438 * R 439 * .RVI ZFRS BLDP WCAM 440 * .011 1001 ..11 0101 441 */ 442 .type arm1020e_crval, #object 443arm1020e_crval: 444 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930 445 446 __INITDATA 447 448/* 449 * Purpose : Function pointers used to access above functions - all calls 450 * come through these 451 */ 452 .type arm1020e_processor_functions, #object 453arm1020e_processor_functions: 454 .word v4t_early_abort 455 .word cpu_arm1020e_proc_init 456 .word cpu_arm1020e_proc_fin 457 .word cpu_arm1020e_reset 458 .word cpu_arm1020e_do_idle 459 .word cpu_arm1020e_dcache_clean_area 460 .word cpu_arm1020e_switch_mm 461 .word cpu_arm1020e_set_pte_ext 462 .size arm1020e_processor_functions, . - arm1020e_processor_functions 463 464 .section ".rodata" 465 466 .type cpu_arch_name, #object 467cpu_arch_name: 468 .asciz "armv5te" 469 .size cpu_arch_name, . - cpu_arch_name 470 471 .type cpu_elf_name, #object 472cpu_elf_name: 473 .asciz "v5" 474 .size cpu_elf_name, . - cpu_elf_name 475 476 .type cpu_arm1020e_name, #object 477cpu_arm1020e_name: 478 .asciz "ARM1020E" 479 .size cpu_arm1020e_name, . - cpu_arm1020e_name 480 481 .align 482 483 .section ".proc.info.init", #alloc, #execinstr 484 485 .type __arm1020e_proc_info,#object 486__arm1020e_proc_info: 487 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE) 488 .long 0xff0ffff0 489 .long PMD_TYPE_SECT | \ 490 PMD_BIT4 | \ 491 PMD_SECT_AP_WRITE | \ 492 PMD_SECT_AP_READ 493 .long PMD_TYPE_SECT | \ 494 PMD_BIT4 | \ 495 PMD_SECT_AP_WRITE | \ 496 PMD_SECT_AP_READ 497 b __arm1020e_setup 498 .long cpu_arch_name 499 .long cpu_elf_name 500 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP 501 .long cpu_arm1020e_name 502 .long arm1020e_processor_functions 503 .long v4wbi_tlb_fns 504 .long v4wb_user_fns 505 .long arm1020e_cache_fns 506 .size __arm1020e_proc_info, . - __arm1020e_proc_info 507