1/*
2 *  linux/arch/arm/mach-shark/irq.c
3 *
4 * by Alexander Schulz
5 *
6 * derived from linux/arch/ppc/kernel/i8259.c and:
7 * include/asm-arm/arch-ebsa110/irq.h
8 * Copyright (C) 1996-1998 Russell King
9 */
10
11#include <linux/init.h>
12#include <linux/fs.h>
13#include <linux/interrupt.h>
14
15#include <asm/irq.h>
16#include <asm/io.h>
17#include <asm/mach/irq.h>
18
19/*
20 * 8259A PIC functions to handle ISA devices:
21 */
22
23/*
24 * This contains the irq mask for both 8259A irq controllers,
25 * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb)
26 */
27static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };
28
29/*
30 * These have to be protected by the irq controller spinlock
31 * before being called.
32 */
33static void shark_disable_8259A_irq(unsigned int irq)
34{
35	unsigned int mask;
36	if (irq<8) {
37	  mask = 1 << irq;
38	  cached_irq_mask[0] |= mask;
39	  outb(cached_irq_mask[1],0xA1);
40	} else {
41	  mask = 1 << (irq-8);
42	  cached_irq_mask[1] |= mask;
43	  outb(cached_irq_mask[0],0x21);
44	}
45}
46
47static void shark_enable_8259A_irq(unsigned int irq)
48{
49	unsigned int mask;
50	if (irq<8) {
51	  mask = ~(1 << irq);
52	  cached_irq_mask[0] &= mask;
53	  outb(cached_irq_mask[0],0x21);
54	} else {
55	  mask = ~(1 << (irq-8));
56	  cached_irq_mask[1] &= mask;
57	  outb(cached_irq_mask[1],0xA1);
58	}
59}
60
61static void shark_ack_8259A_irq(unsigned int irq){}
62
63static irqreturn_t bogus_int(int irq, void *dev_id)
64{
65	printk("Got interrupt %i!\n",irq);
66	return IRQ_NONE;
67}
68
69static struct irqaction cascade;
70
71static struct irq_chip fb_chip = {
72	.name	= "XT-PIC",
73	.ack	= shark_ack_8259A_irq,
74	.mask	= shark_disable_8259A_irq,
75	.unmask = shark_enable_8259A_irq,
76};
77
78void __init shark_init_irq(void)
79{
80	int irq;
81
82	for (irq = 0; irq < NR_IRQS; irq++) {
83		set_irq_chip(irq, &fb_chip);
84		set_irq_handler(irq, handle_edge_irq);
85		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
86	}
87
88	/* init master interrupt controller */
89	outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/
90	outb(0x00, 0x21); /* Vector base */
91	outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */
92	outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/
93	outb(0x0A, 0x20);
94	/* init slave interrupt controller */
95	outb(0x11, 0xA0); /* Start init sequence, edge triggered */
96	outb(0x08, 0xA1); /* Vector base */
97	outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */
98	outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */
99	outb(0x0A, 0xA0);
100	outb(cached_irq_mask[1],0xA1);
101	outb(cached_irq_mask[0],0x21);
102	//request_region(0x20,0x2,"pic1");
103	//request_region(0xA0,0x2,"pic2");
104
105	cascade.handler = bogus_int;
106	cascade.name = "cascade";
107	setup_irq(2,&cascade);
108}
109