1/*
2 *  linux/arch/arm/mach-pxa/generic.c
3 *
4 *  Author:	Nicolas Pitre
5 *  Created:	Jun 15, 2001
6 *  Copyright:	MontaVista Software Inc.
7 *
8 * Code common to all PXA machines.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first.  This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
17 * need be.
18 */
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h>
25#include <linux/pm.h>
26#include <linux/string.h>
27
28#include <linux/sched.h>
29#include <asm/cnt32_to_63.h>
30#include <asm/div64.h>
31
32#include <asm/hardware.h>
33#include <asm/irq.h>
34#include <asm/system.h>
35#include <asm/pgtable.h>
36#include <asm/mach/map.h>
37
38#include <asm/arch/pxa-regs.h>
39#include <asm/arch/gpio.h>
40#include <asm/arch/udc.h>
41#include <asm/arch/pxafb.h>
42#include <asm/arch/mmc.h>
43#include <asm/arch/irda.h>
44#include <asm/arch/i2c.h>
45
46#include "generic.h"
47
48/*
49 * This is the PXA2xx sched_clock implementation. This has a resolution
50 * of at least 308ns and a maximum value that depends on the value of
51 * CLOCK_TICK_RATE.
52 *
53 * The return value is guaranteed to be monotonic in that range as
54 * long as there is always less than 582 seconds between successive
55 * calls to this function.
56 */
57unsigned long long sched_clock(void)
58{
59	unsigned long long v = cnt32_to_63(OSCR);
60	/* Note: top bit ov v needs cleared unless multiplier is even. */
61
62#if	CLOCK_TICK_RATE == 3686400
63	/* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
64	/* The <<1 is used to get rid of tick.hi top bit */
65	v *= 78125<<1;
66	do_div(v, 288<<1);
67#elif	CLOCK_TICK_RATE == 3250000
68	/* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
69	v *= 4000;
70	do_div(v, 13);
71#elif	CLOCK_TICK_RATE == 3249600
72	/* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
73	v *= 625000;
74	do_div(v, 2031);
75#else
76#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
77	/*
78	 * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
79	 * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
80	 * years range and truncation to unsigned long long limits it to
81	 * sched_clock's max range of ~584 years.  This is nice but with
82	 * higher computation cost.
83	 */
84	{
85		union {
86			unsigned long long val;
87			struct { unsigned long lo, hi; };
88		} x;
89		unsigned long long y;
90
91		x.val = v;
92		x.hi &= 0x7fffffff;
93		y = (unsigned long long)x.lo * NSEC_PER_SEC;
94		x.lo = y;
95		y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
96		x.hi = do_div(y, CLOCK_TICK_RATE);
97		do_div(x.val, CLOCK_TICK_RATE);
98		x.hi += y;
99		v = x.val;
100	}
101#endif
102
103	return v;
104}
105
106/*
107 * Handy function to set GPIO alternate functions
108 */
109
110int pxa_gpio_mode(int gpio_mode)
111{
112	unsigned long flags;
113	int gpio = gpio_mode & GPIO_MD_MASK_NR;
114	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
115	int gafr;
116
117	if (gpio > PXA_LAST_GPIO)
118		return -EINVAL;
119
120	local_irq_save(flags);
121	if (gpio_mode & GPIO_DFLT_LOW)
122		GPCR(gpio) = GPIO_bit(gpio);
123	else if (gpio_mode & GPIO_DFLT_HIGH)
124		GPSR(gpio) = GPIO_bit(gpio);
125	if (gpio_mode & GPIO_MD_MASK_DIR)
126		GPDR(gpio) |= GPIO_bit(gpio);
127	else
128		GPDR(gpio) &= ~GPIO_bit(gpio);
129	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
130	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
131	local_irq_restore(flags);
132
133	return 0;
134}
135
136EXPORT_SYMBOL(pxa_gpio_mode);
137
138/*
139 * Return GPIO level
140 */
141int pxa_gpio_get_value(unsigned gpio)
142{
143	return __gpio_get_value(gpio);
144}
145
146EXPORT_SYMBOL(pxa_gpio_get_value);
147
148/*
149 * Set output GPIO level
150 */
151void pxa_gpio_set_value(unsigned gpio, int value)
152{
153	__gpio_set_value(gpio, value);
154}
155
156EXPORT_SYMBOL(pxa_gpio_set_value);
157
158/*
159 * Routine to safely enable or disable a clock in the CKEN
160 */
161void pxa_set_cken(int clock, int enable)
162{
163	unsigned long flags;
164	local_irq_save(flags);
165
166	if (enable)
167		CKEN |= (1 << clock);
168	else
169		CKEN &= ~(1 << clock);
170
171	local_irq_restore(flags);
172}
173
174EXPORT_SYMBOL(pxa_set_cken);
175
176/*
177 * Intel PXA2xx internal register mapping.
178 *
179 * Note 1: not all PXA2xx variants implement all those addresses.
180 *
181 * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
182 *         and cache flush area.
183 */
184static struct map_desc standard_io_desc[] __initdata = {
185  	{	/* Devs */
186		.virtual	=  0xf2000000,
187		.pfn		= __phys_to_pfn(0x40000000),
188		.length		= 0x02000000,
189		.type		= MT_DEVICE
190	}, {	/* LCD */
191		.virtual	=  0xf4000000,
192		.pfn		= __phys_to_pfn(0x44000000),
193		.length		= 0x00100000,
194		.type		= MT_DEVICE
195	}, {	/* Mem Ctl */
196		.virtual	=  0xf6000000,
197		.pfn		= __phys_to_pfn(0x48000000),
198		.length		= 0x00100000,
199		.type		= MT_DEVICE
200	}, {	/* USB host */
201		.virtual	=  0xf8000000,
202		.pfn		= __phys_to_pfn(0x4c000000),
203		.length		= 0x00100000,
204		.type		= MT_DEVICE
205	}, {	/* Camera */
206		.virtual	=  0xfa000000,
207		.pfn		= __phys_to_pfn(0x50000000),
208		.length		= 0x00100000,
209		.type		= MT_DEVICE
210	}, {	/* IMem ctl */
211		.virtual	=  0xfe000000,
212		.pfn		= __phys_to_pfn(0x58000000),
213		.length		= 0x00100000,
214		.type		= MT_DEVICE
215	}, {	/* UNCACHED_PHYS_0 */
216		.virtual	= 0xff000000,
217		.pfn		= __phys_to_pfn(0x00000000),
218		.length		= 0x00100000,
219		.type		= MT_DEVICE
220	}
221};
222
223void __init pxa_map_io(void)
224{
225	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
226	get_clk_frequency_khz(1);
227}
228
229
230static struct resource pxamci_resources[] = {
231	[0] = {
232		.start	= 0x41100000,
233		.end	= 0x41100fff,
234		.flags	= IORESOURCE_MEM,
235	},
236	[1] = {
237		.start	= IRQ_MMC,
238		.end	= IRQ_MMC,
239		.flags	= IORESOURCE_IRQ,
240	},
241};
242
243static u64 pxamci_dmamask = 0xffffffffUL;
244
245static struct platform_device pxamci_device = {
246	.name		= "pxa2xx-mci",
247	.id		= -1,
248	.dev		= {
249		.dma_mask = &pxamci_dmamask,
250		.coherent_dma_mask = 0xffffffff,
251	},
252	.num_resources	= ARRAY_SIZE(pxamci_resources),
253	.resource	= pxamci_resources,
254};
255
256void __init pxa_set_mci_info(struct pxamci_platform_data *info)
257{
258	pxamci_device.dev.platform_data = info;
259}
260
261
262static struct pxa2xx_udc_mach_info pxa_udc_info;
263
264void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
265{
266	memcpy(&pxa_udc_info, info, sizeof *info);
267}
268
269static struct resource pxa2xx_udc_resources[] = {
270	[0] = {
271		.start	= 0x40600000,
272		.end	= 0x4060ffff,
273		.flags	= IORESOURCE_MEM,
274	},
275	[1] = {
276		.start	= IRQ_USB,
277		.end	= IRQ_USB,
278		.flags	= IORESOURCE_IRQ,
279	},
280};
281
282static u64 udc_dma_mask = ~(u32)0;
283
284static struct platform_device udc_device = {
285	.name		= "pxa2xx-udc",
286	.id		= -1,
287	.resource	= pxa2xx_udc_resources,
288	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
289	.dev		=  {
290		.platform_data	= &pxa_udc_info,
291		.dma_mask	= &udc_dma_mask,
292	}
293};
294
295static struct resource pxafb_resources[] = {
296	[0] = {
297		.start	= 0x44000000,
298		.end	= 0x4400ffff,
299		.flags	= IORESOURCE_MEM,
300	},
301	[1] = {
302		.start	= IRQ_LCD,
303		.end	= IRQ_LCD,
304		.flags	= IORESOURCE_IRQ,
305	},
306};
307
308static u64 fb_dma_mask = ~(u64)0;
309
310static struct platform_device pxafb_device = {
311	.name		= "pxa2xx-fb",
312	.id		= -1,
313	.dev		= {
314		.dma_mask	= &fb_dma_mask,
315		.coherent_dma_mask = 0xffffffff,
316	},
317	.num_resources	= ARRAY_SIZE(pxafb_resources),
318	.resource	= pxafb_resources,
319};
320
321void __init set_pxa_fb_info(struct pxafb_mach_info *info)
322{
323	pxafb_device.dev.platform_data = info;
324}
325
326void __init set_pxa_fb_parent(struct device *parent_dev)
327{
328	pxafb_device.dev.parent = parent_dev;
329}
330
331static struct platform_device ffuart_device = {
332	.name		= "pxa2xx-uart",
333	.id		= 0,
334};
335static struct platform_device btuart_device = {
336	.name		= "pxa2xx-uart",
337	.id		= 1,
338};
339static struct platform_device stuart_device = {
340	.name		= "pxa2xx-uart",
341	.id		= 2,
342};
343static struct platform_device hwuart_device = {
344	.name		= "pxa2xx-uart",
345	.id		= 3,
346};
347
348static struct resource i2c_resources[] = {
349	{
350		.start	= 0x40301680,
351		.end	= 0x403016a3,
352		.flags	= IORESOURCE_MEM,
353	}, {
354		.start	= IRQ_I2C,
355		.end	= IRQ_I2C,
356		.flags	= IORESOURCE_IRQ,
357	},
358};
359
360static struct platform_device i2c_device = {
361	.name		= "pxa2xx-i2c",
362	.id		= 0,
363	.resource	= i2c_resources,
364	.num_resources	= ARRAY_SIZE(i2c_resources),
365};
366
367#ifdef CONFIG_PXA27x
368static struct resource i2c_power_resources[] = {
369	{
370		.start	= 0x40f00180,
371		.end	= 0x40f001a3,
372		.flags	= IORESOURCE_MEM,
373	}, {
374		.start	= IRQ_PWRI2C,
375		.end	= IRQ_PWRI2C,
376		.flags	= IORESOURCE_IRQ,
377	},
378};
379
380static struct platform_device i2c_power_device = {
381	.name		= "pxa2xx-i2c",
382	.id		= 1,
383	.resource	= i2c_power_resources,
384	.num_resources	= ARRAY_SIZE(i2c_resources),
385};
386#endif
387
388void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
389{
390	i2c_device.dev.platform_data = info;
391}
392
393static struct resource i2s_resources[] = {
394	{
395		.start	= 0x40400000,
396		.end	= 0x40400083,
397		.flags	= IORESOURCE_MEM,
398	}, {
399		.start	= IRQ_I2S,
400		.end	= IRQ_I2S,
401		.flags	= IORESOURCE_IRQ,
402	},
403};
404
405static struct platform_device i2s_device = {
406	.name		= "pxa2xx-i2s",
407	.id		= -1,
408	.resource	= i2s_resources,
409	.num_resources	= ARRAY_SIZE(i2s_resources),
410};
411
412static u64 pxaficp_dmamask = ~(u32)0;
413
414static struct platform_device pxaficp_device = {
415	.name		= "pxa2xx-ir",
416	.id		= -1,
417	.dev		= {
418		.dma_mask = &pxaficp_dmamask,
419		.coherent_dma_mask = 0xffffffff,
420	},
421};
422
423void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
424{
425	pxaficp_device.dev.platform_data = info;
426}
427
428static struct platform_device pxartc_device = {
429	.name		= "sa1100-rtc",
430	.id		= -1,
431};
432
433static struct platform_device *devices[] __initdata = {
434	&pxamci_device,
435	&udc_device,
436	&pxafb_device,
437	&ffuart_device,
438	&btuart_device,
439	&stuart_device,
440	&pxaficp_device,
441	&i2c_device,
442#ifdef CONFIG_PXA27x
443	&i2c_power_device,
444#endif
445	&i2s_device,
446	&pxartc_device,
447};
448
449static int __init pxa_init(void)
450{
451	int cpuid, ret;
452
453	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
454	if (ret)
455		return ret;
456
457	/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
458	cpuid = read_cpuid(CPUID_ID);
459	if (((cpuid >> 4) & 0xfff) == 0x2d0 ||
460	    ((cpuid >> 4) & 0xfff) == 0x290)
461		ret = platform_device_register(&hwuart_device);
462
463	return ret;
464}
465
466subsys_initcall(pxa_init);
467