1/* 2 * arch/arm/mach-pnx4008/time.c 3 * 4 * PNX4008 Timers 5 * 6 * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com> 7 * 8 * 2005 (c) MontaVista Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/init.h> 16#include <linux/delay.h> 17#include <linux/interrupt.h> 18#include <linux/sched.h> 19#include <linux/spinlock.h> 20#include <linux/module.h> 21#include <linux/kallsyms.h> 22#include <linux/time.h> 23#include <linux/timex.h> 24#include <linux/irq.h> 25 26#include <asm/system.h> 27#include <asm/hardware.h> 28#include <asm/io.h> 29#include <asm/leds.h> 30#include <asm/mach/time.h> 31#include <asm/errno.h> 32 33/*! Note: all timers are UPCOUNTING */ 34 35/*! 36 * Returns number of us since last clock interrupt. Note that interrupts 37 * will have been disabled by do_gettimeoffset() 38 */ 39static unsigned long pnx4008_gettimeoffset(void) 40{ 41 u32 ticks_to_match = 42 __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER); 43 u32 elapsed = LATCH - ticks_to_match; 44 return (elapsed * (tick_nsec / 1000)) / LATCH; 45} 46 47/*! 48 * IRQ handler for the timer 49 */ 50static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id) 51{ 52 if (__raw_readl(HSTIM_INT) & MATCH0_INT) { 53 54 write_seqlock(&xtime_lock); 55 56 do { 57 timer_tick(); 58 59 /* 60 * this algorithm takes care of possible delay 61 * for this interrupt handling longer than a normal 62 * timer period 63 */ 64 __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH, 65 HSTIM_MATCH0); 66 __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */ 67 68 /* 69 * The goal is to keep incrementing HSTIM_MATCH0 70 * register until HSTIM_MATCH0 indicates time after 71 * what HSTIM_COUNTER indicates. 72 */ 73 } while ((signed) 74 (__raw_readl(HSTIM_MATCH0) - 75 __raw_readl(HSTIM_COUNTER)) < 0); 76 77 write_sequnlock(&xtime_lock); 78 } 79 80 return IRQ_HANDLED; 81} 82 83static struct irqaction pnx4008_timer_irq = { 84 .name = "PNX4008 Tick Timer", 85 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 86 .handler = pnx4008_timer_interrupt 87}; 88 89/*! 90 * Set up timer and timer interrupt. 91 */ 92static __init void pnx4008_setup_timer(void) 93{ 94 __raw_writel(RESET_COUNT, MSTIM_CTRL); 95 while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */ 96 __raw_writel(0, MSTIM_CTRL); /* stop the timer */ 97 __raw_writel(0, MSTIM_MCTRL); 98 99 __raw_writel(RESET_COUNT, HSTIM_CTRL); 100 while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */ 101 __raw_writel(0, HSTIM_CTRL); 102 __raw_writel(0, HSTIM_MCTRL); 103 __raw_writel(0, HSTIM_CCR); 104 __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */ 105 __raw_writel(LATCH, HSTIM_MATCH0); 106 __raw_writel(MR0_INT, HSTIM_MCTRL); 107 108 setup_irq(HSTIMER_INT, &pnx4008_timer_irq); 109 110 __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */ 111} 112 113/* Timer Clock Control in PM register */ 114#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC)) 115#define WATCHDOG_CLK_EN 1 116#define TIMER_CLK_EN 2 /* HS and MS timers? */ 117 118static u32 timclk_ctrl_reg_save; 119 120void pnx4008_timer_suspend(void) 121{ 122 timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG); 123 __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */ 124} 125 126void pnx4008_timer_resume(void) 127{ 128 __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */ 129} 130 131struct sys_timer pnx4008_timer = { 132 .init = pnx4008_setup_timer, 133 .offset = pnx4008_gettimeoffset, 134 .suspend = pnx4008_timer_suspend, 135 .resume = pnx4008_timer_resume, 136}; 137