1/* 2 * SDIO device core hardware definitions. 3 * sdio is a portion of the pcmcia core in core rev 3 - rev 8 4 * 5 * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode. 6 * 7 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 16 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 18 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 19 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 * $Id: sbsdio.h,v 13.34 2009/03/11 20:27:16 Exp $ 22 */ 23 24#ifndef _SBSDIO_H 25#define _SBSDIO_H 26 27#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */ 28 29/* function 1 miscellaneous registers */ 30#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */ 31#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */ 32#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */ 33#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */ 34#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */ 35#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */ 36#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */ 37#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */ 38#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */ 39#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */ 40 41/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */ 42#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */ 43#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */ 44#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */ 45#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */ 46#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */ 47#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */ 48#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */ 49#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */ 50#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */ 51#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */ 52 53#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 54#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */ 55 56/* SBSDIO_SPROM_CS */ 57#define SBSDIO_SPROM_IDLE 0 58#define SBSDIO_SPROM_WRITE 1 59#define SBSDIO_SPROM_READ 2 60#define SBSDIO_SPROM_WEN 4 61#define SBSDIO_SPROM_WDS 7 62#define SBSDIO_SPROM_DONE 8 63 64/* SBSDIO_SPROM_INFO */ 65#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */ 66#define SROM_BLANK 0x04 /* depreciated in corerev 6 */ 67#define SROM_OTP 0x80 /* OTP present */ 68 69/* SBSDIO_CHIP_CTRL */ 70#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu, 71 * 1: power on oscillator 72 * (for 4318 only) 73 */ 74/* SBSDIO_WATERMARK */ 75#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device 76 * to wait before sending data to host 77 */ 78 79/* SBSDIO_DEVICE_CTL */ 80#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when 81 * receiving CMD53 82 */ 83#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is 84 * synchronous to the sdio clock 85 */ 86#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host 87 * except the chipActive (rev 8) 88 */ 89#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put 90 * external pads in tri-state; requires 91 * sdio bus power cycle to clear (rev 9) 92 */ 93#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */ 94#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */ 95#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */ 96#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */ 97 98 99/* SBSDIO_FUNC1_CHIPCLKCSR */ 100#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */ 101#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */ 102#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */ 103#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */ 104#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */ 105#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */ 106#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */ 107#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */ 108/* In rev8, actual avail bits followed original docs */ 109#define SBSDIO_Rev8_HT_AVAIL 0x40 110#define SBSDIO_Rev8_ALP_AVAIL 0x80 111 112#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 113#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 114#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 115#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 116#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \ 117 (alponly ? 1 : SBSDIO_HTAV(regval))) 118 119/* SBSDIO_FUNC1_SDIOPULLUP */ 120#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */ 121#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */ 122#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */ 123#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */ 124#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */ 125 126/* function 1 OCP space */ 127#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */ 128#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 129#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */ 130 131/* some duplication with sbsdpcmdev.h here */ 132/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ 133#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */ 134#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */ 135#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */ 136#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */ 137 138/* direct(mapped) cis space */ 139#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */ 140#ifdef BCMSPI 141#define SBSDIO_CIS_SIZE_LIMIT 0x100 /* maximum bytes in one spi CIS */ 142#else 143#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */ 144#endif /* !BCMSPI */ 145#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */ 146 147#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */ 148 149#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple, 150 * link bytes 151 */ 152 153/* indirect cis access (in sprom) */ 154#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from 155 * 8th byte 156 */ 157 158#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one 159 * data comamnd 160 */ 161 162#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */ 163 164#endif /* _SBSDIO_H */ 165