1/* 2 * HND SiliconBackplane Gigabit Ethernet core registers 3 * 4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: sbgige.h,v 13.1 2005/11/10 20:21:45 Exp $ 19 */ 20 21#ifndef _sbgige_h_ 22#define _sbgige_h_ 23 24#include <typedefs.h> 25#include <sbconfig.h> 26#include <pcicfg.h> 27 28/* cpp contortions to concatenate w/arg prescan */ 29#ifndef PAD 30#define _PADLINE(line) pad ## line 31#define _XSTR(line) _PADLINE(line) 32#define PAD _XSTR(__LINE__) 33#endif /* PAD */ 34 35/* PCI to OCP shim registers */ 36typedef volatile struct { 37 uint32 FlushStatusControl; 38 uint32 FlushReadAddr; 39 uint32 FlushTimeoutCntr; 40 uint32 BarrierReg; 41 uint32 MaocpSIControl; 42 uint32 SiocpMaControl; 43 uint8 PAD[0x02E8]; 44} sbgige_pcishim_t; 45 46/* SB core registers */ 47typedef volatile struct { 48 /* PCI I/O Read/Write registers */ 49 uint8 pciio[0x0400]; 50 51 /* Reserved */ 52 uint8 reserved[0x0400]; 53 54 /* PCI configuration registers */ 55 pci_config_regs pcicfg; 56 uint8 PAD[0x0300]; 57 58 /* PCI to OCP shim registers */ 59 sbgige_pcishim_t pcishim; 60 61 /* Sonics SiliconBackplane registers */ 62 sbconfig_t sbconfig; 63} sbgige_t; 64 65#endif /* _sbgige_h_ */ 66